25 lines
653 B
VHDL
25 lines
653 B
VHDL
ARCHITECTURE studentVersion OF resizer IS
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signal mySignal : unsigned(outputBitNb-1 downto 0);
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--------------------------------------------------------------------------------
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BEGIN
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INPUT_BIGGER: if inputBitNb >= outputBitNb generate
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process(resizeIn)
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begin
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mySignal <= resize(shift_right(resizeIn, inputBitNb - outputBitNb), outputBitNb);
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end process;
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end generate INPUT_BIGGER;
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OUTPUT_BIGGER: if inputBitNb <= outputBitNb generate
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process(resizeIn)
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begin
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mySignal <= shift_left(resize(resizeIn, outputBitNb), outputBitNb - inputBitNb);
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end process;
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end generate OUTPUT_BIGGER;
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resizeOut <= mySignal;
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END ARCHITECTURE studentVersion;
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