22 lines
447 B
VHDL
22 lines
447 B
VHDL
ARCHITECTURE empty OF programRom IS
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subtype memoryWordType is std_ulogic_vector(dataOut'range);
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type memoryArrayType is array (0 to 2**address'length-1) of memoryWordType;
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signal memoryArray : memoryArrayType := (
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others => (others => '0')
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);
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BEGIN
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process (clock)
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begin
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if rising_edge(clock) then
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if en = '1' then
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dataOut <= (others => '0');
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end if;
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end if;
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end process;
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END ARCHITECTURE empty;
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