2335 lines
29 KiB
Plaintext
2335 lines
29 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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)
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(DmPackageRef
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library "AhbLite"
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unitName "ahbLite"
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)
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]
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libraryRefs [
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"ieee"
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"AhbLite"
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]
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)
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version "26.1"
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appVersion "2018.1 (Build 12)"
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model (Symbol
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commonDM (CommonDM
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ldm (LogicalDM
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suid 32,0
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usingSuid 1
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emptyRow *1 (LEmptyRow
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)
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uid 165,0
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optionalChildren [
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*2 (RefLabelRowHdr
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)
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*3 (TitleRowHdr
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)
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*4 (FilterRowHdr
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)
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|
*5 (RefLabelColHdr
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tm "RefLabelColHdrMgr"
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)
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*6 (RowExpandColHdr
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tm "RowExpandColHdrMgr"
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)
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*7 (GroupColHdr
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tm "GroupColHdrMgr"
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)
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*8 (NameColHdr
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tm "NameColHdrMgr"
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)
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*9 (ModeColHdr
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tm "ModeColHdrMgr"
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)
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*10 (TypeColHdr
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tm "TypeColHdrMgr"
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)
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*11 (BoundsColHdr
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tm "BoundsColHdrMgr"
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)
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*12 (InitColHdr
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tm "InitColHdrMgr"
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)
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*13 (EolColHdr
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tm "EolColHdrMgr"
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)
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|
*14 (LogPort
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port (LogicalPort
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|
m 1
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|
decl (Decl
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n "clock"
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t "std_ulogic"
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o 1
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suid 17,0
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)
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)
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uid 323,0
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)
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*15 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "hAddr"
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t "unsigned"
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b "( ahbAddressBitNb-1 DOWNTO 0 )"
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o 2
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suid 18,0
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)
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)
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uid 325,0
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)
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*16 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "hClk"
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t "std_uLogic"
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o 3
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suid 19,0
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)
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)
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uid 327,0
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)
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*17 (LogPort
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port (LogicalPort
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decl (Decl
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n "hRData"
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t "std_ulogic_vector"
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b "(ahbDataBitNb-1 DOWNTO 0)"
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o 4
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suid 20,0
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)
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)
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uid 329,0
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)
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*18 (LogPort
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port (LogicalPort
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decl (Decl
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n "hReady"
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t "std_uLogic"
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o 5
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suid 21,0
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)
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)
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uid 331,0
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)
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*19 (LogPort
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port (LogicalPort
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m 1
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|
decl (Decl
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|
n "hReset_n"
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t "std_uLogic"
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o 6
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suid 22,0
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)
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)
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uid 333,0
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)
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*20 (LogPort
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|
port (LogicalPort
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|
decl (Decl
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n "hResp"
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t "std_uLogic"
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o 7
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suid 23,0
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)
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)
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uid 335,0
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)
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*21 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "hSel"
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t "std_uLogic"
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o 8
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suid 24,0
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)
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)
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uid 337,0
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)
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*22 (LogPort
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port (LogicalPort
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m 1
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decl (Decl
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n "hTrans"
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t "std_ulogic_vector"
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b "(ahbTransBitNb-1 DOWNTO 0)"
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o 9
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suid 25,0
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)
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)
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uid 339,0
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)
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*23 (LogPort
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port (LogicalPort
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|
m 1
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|
decl (Decl
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n "hWData"
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t "std_ulogic_vector"
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|
b "(ahbDataBitNb-1 DOWNTO 0)"
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o 10
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suid 26,0
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)
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)
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uid 341,0
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)
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*24 (LogPort
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port (LogicalPort
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m 1
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|
decl (Decl
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n "hWrite"
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t "std_uLogic"
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o 11
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suid 27,0
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)
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)
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|
uid 343,0
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)
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|
*25 (LogPort
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|
port (LogicalPort
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|
decl (Decl
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|
n "lowpassOutY"
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|
t "unsigned"
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|
b "(signalBitNb-1 DOWNTO 0)"
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o 13
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suid 28,0
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)
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)
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uid 345,0
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)
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*26 (LogPort
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port (LogicalPort
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|
decl (Decl
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|
n "outX"
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t "std_ulogic"
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|
o 14
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suid 29,0
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)
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)
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|
uid 347,0
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)
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|
*27 (LogPort
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|
port (LogicalPort
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|
decl (Decl
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|
n "outY"
|
|
t "std_ulogic"
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|
o 15
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|
suid 30,0
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)
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)
|
|
uid 349,0
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)
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*28 (LogPort
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|
port (LogicalPort
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|
m 1
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|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
o 16
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|
suid 31,0
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)
|
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)
|
|
uid 351,0
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|
)
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|
*29 (LogPort
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|
port (LogicalPort
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|
m 1
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|
decl (Decl
|
|
n "selSinCos"
|
|
t "std_ulogic"
|
|
o 17
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|
suid 32,0
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)
|
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)
|
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uid 353,0
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)
|
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]
|
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)
|
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pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 178,0
|
|
optionalChildren [
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|
*30 (Sheet
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|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
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)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
emptyMRCItem *31 (MRCItem
|
|
litem &1
|
|
pos 3
|
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dimension 20
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)
|
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uid 180,0
|
|
optionalChildren [
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|
*32 (MRCItem
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litem &2
|
|
pos 0
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|
dimension 20
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|
uid 181,0
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)
|
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*33 (MRCItem
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litem &3
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pos 1
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dimension 23
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uid 182,0
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)
|
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*34 (MRCItem
|
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litem &4
|
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pos 2
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hidden 1
|
|
dimension 20
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uid 183,0
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)
|
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*35 (MRCItem
|
|
litem &14
|
|
pos 0
|
|
dimension 20
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|
uid 324,0
|
|
)
|
|
*36 (MRCItem
|
|
litem &15
|
|
pos 1
|
|
dimension 20
|
|
uid 326,0
|
|
)
|
|
*37 (MRCItem
|
|
litem &16
|
|
pos 2
|
|
dimension 20
|
|
uid 328,0
|
|
)
|
|
*38 (MRCItem
|
|
litem &17
|
|
pos 3
|
|
dimension 20
|
|
uid 330,0
|
|
)
|
|
*39 (MRCItem
|
|
litem &18
|
|
pos 4
|
|
dimension 20
|
|
uid 332,0
|
|
)
|
|
*40 (MRCItem
|
|
litem &19
|
|
pos 5
|
|
dimension 20
|
|
uid 334,0
|
|
)
|
|
*41 (MRCItem
|
|
litem &20
|
|
pos 6
|
|
dimension 20
|
|
uid 336,0
|
|
)
|
|
*42 (MRCItem
|
|
litem &21
|
|
pos 7
|
|
dimension 20
|
|
uid 338,0
|
|
)
|
|
*43 (MRCItem
|
|
litem &22
|
|
pos 8
|
|
dimension 20
|
|
uid 340,0
|
|
)
|
|
*44 (MRCItem
|
|
litem &23
|
|
pos 9
|
|
dimension 20
|
|
uid 342,0
|
|
)
|
|
*45 (MRCItem
|
|
litem &24
|
|
pos 10
|
|
dimension 20
|
|
uid 344,0
|
|
)
|
|
*46 (MRCItem
|
|
litem &25
|
|
pos 11
|
|
dimension 20
|
|
uid 346,0
|
|
)
|
|
*47 (MRCItem
|
|
litem &26
|
|
pos 12
|
|
dimension 20
|
|
uid 348,0
|
|
)
|
|
*48 (MRCItem
|
|
litem &27
|
|
pos 13
|
|
dimension 20
|
|
uid 350,0
|
|
)
|
|
*49 (MRCItem
|
|
litem &28
|
|
pos 14
|
|
dimension 20
|
|
uid 352,0
|
|
)
|
|
*50 (MRCItem
|
|
litem &29
|
|
pos 15
|
|
dimension 20
|
|
uid 354,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 184,0
|
|
optionalChildren [
|
|
*51 (MRCItem
|
|
litem &5
|
|
pos 0
|
|
dimension 20
|
|
uid 185,0
|
|
)
|
|
*52 (MRCItem
|
|
litem &7
|
|
pos 1
|
|
dimension 50
|
|
uid 186,0
|
|
)
|
|
*53 (MRCItem
|
|
litem &8
|
|
pos 2
|
|
dimension 100
|
|
uid 187,0
|
|
)
|
|
*54 (MRCItem
|
|
litem &9
|
|
pos 3
|
|
dimension 50
|
|
uid 188,0
|
|
)
|
|
*55 (MRCItem
|
|
litem &10
|
|
pos 4
|
|
dimension 100
|
|
uid 189,0
|
|
)
|
|
*56 (MRCItem
|
|
litem &11
|
|
pos 5
|
|
dimension 100
|
|
uid 190,0
|
|
)
|
|
*57 (MRCItem
|
|
litem &12
|
|
pos 6
|
|
dimension 50
|
|
uid 191,0
|
|
)
|
|
*58 (MRCItem
|
|
litem &13
|
|
pos 7
|
|
dimension 80
|
|
uid 192,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 4
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 179,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 164,0
|
|
)
|
|
genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *59 (LEmptyRow
|
|
)
|
|
uid 194,0
|
|
optionalChildren [
|
|
*60 (RefLabelRowHdr
|
|
)
|
|
*61 (TitleRowHdr
|
|
)
|
|
*62 (FilterRowHdr
|
|
)
|
|
*63 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*64 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*65 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*66 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*67 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*68 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*69 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*70 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
displayShortBounds 1
|
|
editShortBounds 1
|
|
uid 206,0
|
|
optionalChildren [
|
|
*71 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
emptyMRCItem *72 (MRCItem
|
|
litem &59
|
|
pos 3
|
|
dimension 20
|
|
)
|
|
uid 208,0
|
|
optionalChildren [
|
|
*73 (MRCItem
|
|
litem &60
|
|
pos 0
|
|
dimension 20
|
|
uid 209,0
|
|
)
|
|
*74 (MRCItem
|
|
litem &61
|
|
pos 1
|
|
dimension 23
|
|
uid 210,0
|
|
)
|
|
*75 (MRCItem
|
|
litem &62
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 211,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 212,0
|
|
optionalChildren [
|
|
*76 (MRCItem
|
|
litem &63
|
|
pos 0
|
|
dimension 20
|
|
uid 213,0
|
|
)
|
|
*77 (MRCItem
|
|
litem &65
|
|
pos 1
|
|
dimension 50
|
|
uid 214,0
|
|
)
|
|
*78 (MRCItem
|
|
litem &66
|
|
pos 2
|
|
dimension 100
|
|
uid 215,0
|
|
)
|
|
*79 (MRCItem
|
|
litem &67
|
|
pos 3
|
|
dimension 100
|
|
uid 216,0
|
|
)
|
|
*80 (MRCItem
|
|
litem &68
|
|
pos 4
|
|
dimension 50
|
|
uid 217,0
|
|
)
|
|
*81 (MRCItem
|
|
litem &69
|
|
pos 5
|
|
dimension 50
|
|
uid 218,0
|
|
)
|
|
*82 (MRCItem
|
|
litem &70
|
|
pos 6
|
|
dimension 80
|
|
uid 219,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 207,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 193,0
|
|
type 1
|
|
)
|
|
VExpander (VariableExpander
|
|
vvMap [
|
|
(vvPair
|
|
variable "HDLDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip_test/hdl"
|
|
)
|
|
(vvPair
|
|
variable "HDSDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip_test/hds"
|
|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip_test/hds/ahb@beamer_tester1/interface.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip_test/hds/ahb@beamer_tester1/interface.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip_test/hds"
|
|
)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
|
|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "asm_file"
|
|
value "beamer.asm"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
|
|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip_test/hds/ahb@beamer_tester1"
|
|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip_test/hds/ahbBeamer_tester1"
|
|
)
|
|
(vvPair
|
|
variable "date"
|
|
value "03/13/19"
|
|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "Wed"
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "Wednesday"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "13"
|
|
)
|
|
(vvPair
|
|
variable "designName"
|
|
value "$DESIGN_NAME"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "ahbBeamer_tester1"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "03/13/19"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "Aphelia"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "14:30:07"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "Aphelia"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
|
|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "SystemOnChip_test"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "$SCRATCH_DIR/SystemOnChip_test"
|
|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "03"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "ahbBeamer_tester1"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "Mar"
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "March"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip_test/hds/ahb@beamer_tester1/interface"
|
|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/SystemOnChip/Prefs/../SystemOnChip_test/hds/ahbBeamer_tester1/interface"
|
|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "systemOnChip"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "task_AsmPath"
|
|
value "$HEI_LIBS_DIR/NanoBlaze/hdl"
|
|
)
|
|
(vvPair
|
|
variable "task_HDSPath"
|
|
value "$HDS_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEBinPath"
|
|
value "$ISE_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEPath"
|
|
value "$ISE_WORK_DIR"
|
|
)
|
|
(vvPair
|
|
variable "task_ModelSimPath"
|
|
value "$MODELSIM_HOME/modeltech/bin"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "14:30:07"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "ahbBeamer_tester1"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "version"
|
|
value "2018.1 (Build 12)"
|
|
)
|
|
(vvPair
|
|
variable "view"
|
|
value "interface"
|
|
)
|
|
(vvPair
|
|
variable "year"
|
|
value "2019"
|
|
)
|
|
(vvPair
|
|
variable "yy"
|
|
value "19"
|
|
)
|
|
]
|
|
)
|
|
LanguageMgr "Vhdl2008LangMgr"
|
|
uid 163,0
|
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optionalChildren [
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|
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uid 8,0
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optionalChildren [
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uid 243,0
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|
vasetType 1
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uid 245,0
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blo "73250,7000"
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tm "CptPortNameMgr"
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dt (MLText
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|
|
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|
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|
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thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
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n "clock"
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uid 248,0
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shape (Triangle
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uid 249,0
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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tg (CPTG
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uid 250,0
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ps "CptPortTextPlaceStrategy"
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blo "23250,7000"
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tm "CptPortNameMgr"
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dt (MLText
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uid 252,0
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va (VaSet
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st "hAddr : OUT unsigned ( ahbAddressBitNb-1 DOWNTO 0 ) ;
|
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|
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)
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thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
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n "hAddr"
|
|
t "unsigned"
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b "( ahbAddressBitNb-1 DOWNTO 0 )"
|
|
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uid 253,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 254,0
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fg "0,65535,0"
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tg (CPTG
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uid 255,0
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stg "RightVerticalLayoutStrategy"
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uid 256,0
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va (VaSet
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font "courier,8,0"
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st "hClk"
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|
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|
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blo "41250,7000"
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tm "CptPortNameMgr"
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dt (MLText
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uid 257,0
|
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va (VaSet
|
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font "courier,8,0"
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)
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xt "44000,9000,61500,9900"
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st "hClk : OUT std_uLogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "hClk"
|
|
t "std_uLogic"
|
|
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|
|
suid 19,0
|
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)
|
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|
|
uid 258,0
|
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 259,0
|
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ro 180
|
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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xt "32625,5250,33375,6000"
|
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|
|
tg (CPTG
|
|
uid 260,0
|
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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f (Text
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st "hRData"
|
|
ju 2
|
|
blo "33250,7000"
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tm "CptPortNameMgr"
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)
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dt (MLText
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uid 262,0
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va (VaSet
|
|
font "courier,8,0"
|
|
)
|
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xt "44000,1800,77500,2700"
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st "hRData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0) ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "hRData"
|
|
t "std_ulogic_vector"
|
|
b "(ahbDataBitNb-1 DOWNTO 0)"
|
|
o 4
|
|
suid 20,0
|
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)
|
|
)
|
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)
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*88 (CptPort
|
|
uid 263,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 264,0
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va (VaSet
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fg "0,65535,0"
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tg (CPTG
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uid 265,0
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va (VaSet
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font "courier,8,0"
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tm "CptPortNameMgr"
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)
|
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thePort (LogicalPort
|
|
decl (Decl
|
|
n "hReady"
|
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t "std_uLogic"
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uid 268,0
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va (VaSet
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blo "43250,7000"
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tm "CptPortNameMgr"
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st "hReset_n : OUT std_uLogic ;
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|
|
m 1
|
|
decl (Decl
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)
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*90 (CptPort
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uid 273,0
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ps "OnEdgeStrategy"
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uid 274,0
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va (VaSet
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tg (CPTG
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uid 275,0
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uid 276,0
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st "hResp"
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|
ju 2
|
|
blo "37250,7000"
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tm "CptPortNameMgr"
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dt (MLText
|
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uid 277,0
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va (VaSet
|
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font "courier,8,0"
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|
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xt "44000,3600,61500,4500"
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st "hResp : IN std_uLogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "hResp"
|
|
t "std_uLogic"
|
|
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|
|
suid 23,0
|
|
)
|
|
)
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|
)
|
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*91 (CptPort
|
|
uid 278,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 279,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
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|
|
xt "30625,5250,31375,6000"
|
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tg (CPTG
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|
uid 280,0
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ps "CptPortTextPlaceStrategy"
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va (VaSet
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font "courier,8,0"
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xt "30550,7000,31450,9000"
|
|
st "hSel"
|
|
ju 2
|
|
blo "31250,7000"
|
|
tm "CptPortNameMgr"
|
|
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|
|
)
|
|
dt (MLText
|
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uid 282,0
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va (VaSet
|
|
font "courier,8,0"
|
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|
xt "44000,10800,61500,11700"
|
|
st "hSel : OUT std_uLogic ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "hSel"
|
|
t "std_uLogic"
|
|
o 8
|
|
suid 24,0
|
|
)
|
|
)
|
|
)
|
|
*92 (CptPort
|
|
uid 283,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 284,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "26625,5250,27375,6000"
|
|
)
|
|
tg (CPTG
|
|
uid 285,0
|
|
ps "CptPortTextPlaceStrategy"
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|
stg "RightVerticalLayoutStrategy"
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|
f (Text
|
|
uid 286,0
|
|
ro 270
|
|
va (VaSet
|
|
font "courier,8,0"
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)
|
|
xt "26550,7000,27450,10000"
|
|
st "hTrans"
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|
ju 2
|
|
blo "27250,7000"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 287,0
|
|
va (VaSet
|
|
font "courier,8,0"
|
|
)
|
|
xt "44000,11700,78000,12600"
|
|
st "hTrans : OUT std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0) ;
|
|
"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "hTrans"
|
|
t "std_ulogic_vector"
|
|
b "(ahbTransBitNb-1 DOWNTO 0)"
|
|
o 9
|
|
suid 25,0
|
|
)
|
|
)
|
|
)
|
|
*93 (CptPort
|
|
uid 288,0
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