38 lines
746 B
VHDL
38 lines
746 B
VHDL
architecture oneRegister of FIFO_oneRegister is
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signal dataRegister: std_ulogic_vector(dataIn'range);
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begin
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writeReg: process(reset, clock)
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begin
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if reset = '1' then
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dataRegister <= (others => '0');
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elsif rising_edge(clock) then
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if write = '1' then
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dataRegister <= dataIn;
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end if;
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end if;
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end process writeReg;
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dataOut <= dataRegister;
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manageFlags: process(reset, clock)
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begin
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if reset = '1' then
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empty <= '1';
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full <= '0';
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elsif rising_edge(clock) then
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if write = '1' then
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empty <= '0';
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full <= '1';
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elsif read = '1' then
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empty <= '1';
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full <= '0';
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end if;
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end if;
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end process manageFlags;
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end oneRegister;
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