25 lines
711 B
VHDL
25 lines
711 B
VHDL
ARCHITECTURE RTL OF sdramControllerTimingsShiftRegister IS
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--constant leadingZeroesNb: positive := 2;
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--constant leadingZeroes: std_ulogic_vector(1 to leadingZeroesNb) := (others => '0');
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--signal shiftReg: std_ulogic_vector(1 to timerDone'high-leadingZeroesNb);
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signal shiftReg: std_ulogic_vector(1 to timerDone'high);
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BEGIN
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shiftToken : process(reset, clock)
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begin
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if reset = '1' then
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shiftReg <= (others => '0');
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elsif rising_edge(clock) then
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shiftReg(1) <= timerStart;
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shiftReg(2 to shiftReg'right) <= shiftReg(1 to shiftReg'right-1);
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end if;
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end process shiftToken;
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--timerDone <= leadingZeroes & shiftReg;
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timerDone <= shiftReg;
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END ARCHITECTURE RTL;
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