54 lines
1.7 KiB
VHDL
54 lines
1.7 KiB
VHDL
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ARCHITECTURE rtl OF registerFile IS
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-- Bank of register
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type t_registersBank is array (31 downto 0) of
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std_ulogic_vector(31 downto 0);
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-- A bank of registers
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signal larr_registers: t_registersBank;
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signal lvec_btns : std_ulogic_vector(31 downto 0);
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BEGIN
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-- Special regs
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process(rst, clk)
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begin
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if rst = '1' then
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lvec_btns <= (others => '0');
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elsif rising_edge(clk) then
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lvec_btns <= (btns'length to g_datawidth-1 => '0') & btns;
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end if;
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end process;
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-- Clocked write
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process(rst, clk) begin
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if rst = '1' then
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larr_registers <= (others => (others => '0')) after g_tRfWr;
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elsif rising_edge(clk) then
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if writeEnable3 = '1' and en = '1' then
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larr_registers(to_integer(unsigned(addr3))) <= writeData after (g_tRfWr + g_tSetup);
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end if;
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end if;
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end process;
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-- Comb. read
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-- Addr 0 wired to 0s
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process(addr1, addr2) begin
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if (to_integer(unsigned(addr1)) = 0) then
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RD1 <= (others => '0') after g_tRfRd;
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elsif (to_integer(unsigned(addr1)) = 31) then -- buttons
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RD1 <= lvec_btns after g_tRfRd;
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else
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RD1 <= larr_registers(to_integer(unsigned(addr1))) after g_tRfRd;
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end if;
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if (to_integer(unsigned(addr2)) = 0) then
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RD2 <= (others => '0') after g_tRfRd;
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elsif (to_integer(unsigned(addr2)) = 31) then -- buttons
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RD2 <= lvec_btns after g_tRfRd;
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else
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RD2 <= larr_registers(to_integer(unsigned(addr2))) after g_tRfRd;
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end if;
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end process;
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leds <= larr_registers(30);
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END ARCHITECTURE rtl;
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