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Initial commit
2023-12-11 13:43:05 +00:00
<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html><head>
<title>Static Call Graph - [DMA\DMA.axf]</title></head>
<body><HR>
<H1>Static Call Graph for image DMA\DMA.axf</H1><HR>
Activate cache
2023-12-11 14:07:16 +00:00
<BR><P>#&#060CALLGRAPH&#062# ARM Linker, 5060960: Last Updated: Mon Dec 11 15:05:30 2023
Initial commit
2023-12-11 13:43:05 +00:00
<BR><P>
<H3>Maximum Stack Usage = 176 bytes + Unknown(Functions without stacksize, Cycles, Untraceable Function Pointers)</H3><H3>
Call chain for Maximum Stack Depth:</H3>
__rt_entry_main &rArr; main &rArr; SystemClock_Config &rArr; HAL_RCC_ClockConfig &rArr; HAL_RCC_GetSysClockFreq &rArr; __aeabi_uldivmod
<P>
<H3>
Functions with no stack information
</H3><UL>
Activate cache
2023-12-11 14:07:16 +00:00
<LI><a href="#[a4]">__user_initial_stackheap</a>
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
</UL>
<P>
<H3>
Mutually Recursive functions
</H3> <LI><a href="#[26]">ADC_IRQHandler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[26]">ADC_IRQHandler</a><BR>
<LI><a href="#[e]">BusFault_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[e]">BusFault_Handler</a><BR>
<LI><a href="#[c]">HardFault_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[c]">HardFault_Handler</a><BR>
<LI><a href="#[d]">MemManage_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[d]">MemManage_Handler</a><BR>
<LI><a href="#[b]">NMI_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[b]">NMI_Handler</a><BR>
<LI><a href="#[f]">UsageFault_Handler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[f]">UsageFault_Handler</a><BR>
</UL>
<P>
<H3>
Function Pointers
</H3><UL>
<LI><a href="#[26]">ADC_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[e]">BusFault_Handler</a> from stm32f7xx_it.o(i.BusFault_Handler) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[28]">CAN1_RX0_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[29]">CAN1_RX1_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[2a]">CAN1_SCE_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[27]">CAN1_TX_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[54]">CAN2_RX0_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[55]">CAN2_RX1_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[56]">CAN2_SCE_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[53]">CAN2_TX_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[71]">CEC_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[62]">DCMI_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[1f]">DMA1_Stream0_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[20]">DMA1_Stream1_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[21]">DMA1_Stream2_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[22]">DMA1_Stream3_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[23]">DMA1_Stream4_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[24]">DMA1_Stream5_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[25]">DMA1_Stream6_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[43]">DMA1_Stream7_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[6d]">DMA2D_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[4c]">DMA2_Stream0_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[4d]">DMA2_Stream1_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[4e]">DMA2_Stream2_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[4f]">DMA2_Stream3_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[50]">DMA2_Stream4_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[58]">DMA2_Stream5_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[59]">DMA2_Stream6_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[5a]">DMA2_Stream7_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[11]">DebugMon_Handler</a> from stm32f7xx_it.o(i.DebugMon_Handler) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[51]">ETH_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[52]">ETH_WKUP_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[1a]">EXTI0_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[3c]">EXTI15_10_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[1b]">EXTI1_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[1c]">EXTI2_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[1d]">EXTI3_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[1e]">EXTI4_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[2b]">EXTI9_5_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[18]">FLASH_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[44]">FMC_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[64]">FPU_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[c]">HardFault_Handler</a> from stm32f7xx_it.o(i.HardFault_Handler) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[34]">I2C1_ER_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[33]">I2C1_EV_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[36]">I2C2_ER_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[35]">I2C2_EV_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[5d]">I2C3_ER_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[5c]">I2C3_EV_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[73]">I2C4_ER_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[72]">I2C4_EV_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[70]">LPTIM1_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[6c]">LTDC_ER_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[6b]">LTDC_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[d]">MemManage_Handler</a> from stm32f7xx_it.o(i.MemManage_Handler) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[b]">NMI_Handler</a> from stm32f7xx_it.o(i.NMI_Handler) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[57]">OTG_FS_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[3e]">OTG_FS_WKUP_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[5f]">OTG_HS_EP1_IN_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[5e]">OTG_HS_EP1_OUT_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[61]">OTG_HS_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[60]">OTG_HS_WKUP_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[15]">PVD_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[12]">PendSV_Handler</a> from stm32f7xx_it.o(i.PendSV_Handler) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[6f]">QUADSPI_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[19]">RCC_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[63]">RNG_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[3d]">RTC_Alarm_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[17]">RTC_WKUP_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[a]">Reset_Handler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[6a]">SAI1_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[6e]">SAI2_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[45]">SDMMC1_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[74]">SPDIF_RX_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[37]">SPI1_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[38]">SPI2_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[47]">SPI3_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[67]">SPI4_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[68]">SPI5_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[69]">SPI6_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[10]">SVC_Handler</a> from stm32f7xx_it.o(i.SVC_Handler) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[13]">SysTick_Handler</a> from stm32f7xx_it.o(i.SysTick_Handler) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[75]">SystemInit</a> from system_stm32f7xx.o(i.SystemInit) referenced from startup_stm32f746xx.o(.text)
<LI><a href="#[16]">TAMP_STAMP_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[2c]">TIM1_BRK_TIM9_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[2f]">TIM1_CC_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[2e]">TIM1_TRG_COM_TIM11_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[2d]">TIM1_UP_TIM10_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[30]">TIM2_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[31]">TIM3_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[32]">TIM4_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[46]">TIM5_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[4a]">TIM6_DAC_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[4b]">TIM7_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[3f]">TIM8_BRK_TIM12_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[42]">TIM8_CC_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[41]">TIM8_TRG_COM_TIM14_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[40]">TIM8_UP_TIM13_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[48]">UART4_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[49]">UART5_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[65]">UART7_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[66]">UART8_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[39]">USART1_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[3a]">USART2_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[3b]">USART3_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[5b]">USART6_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[f]">UsageFault_Handler</a> from stm32f7xx_it.o(i.UsageFault_Handler) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[14]">WWDG_IRQHandler</a> from startup_stm32f746xx.o(.text) referenced from startup_stm32f746xx.o(RESET)
<LI><a href="#[79]">__main</a> from __main.o(!!!main) referenced from startup_stm32f746xx.o(.text)
<LI><a href="#[78]">_printf_input_char</a> from _printf_char_common.o(.text) referenced from _printf_char_common.o(.text)
<LI><a href="#[77]">fputc</a> from fputc.o(i.fputc) referenced from _printf_char_file.o(.text)
</UL>
<P>
<H3>
Global Symbols
</H3>
<P><STRONG><a name="[79]"></a>__main</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, __main.o(!!!main))
<BR><BR>[Calls]<UL><LI><a href="#[7b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_entry
<LI><a href="#[7a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__scatterload
</UL>
<P><STRONG><a name="[7a]"></a>__scatterload</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter))
<BR><BR>[Called By]<UL><LI><a href="#[79]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__main
</UL>
<P><STRONG><a name="[7c]"></a>__scatterload_rt2</STRONG> (Thumb, 44 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED)
<BR><BR>[Calls]<UL><LI><a href="#[7b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_entry
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[e9]"></a>__scatterload_rt2_thumb_only</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED)
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[ea]"></a>__scatterload_null</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED)
Initial commit
2023-12-11 13:43:05 +00:00
<P><STRONG><a name="[7d]"></a>__scatterload_copy</STRONG> (Thumb, 26 bytes, Stack size unknown bytes, __scatter_copy.o(!!handler_copy), UNUSED)
<BR><BR>[Calls]<UL><LI><a href="#[7d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__scatterload_copy
</UL>
<BR>[Called By]<UL><LI><a href="#[7d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__scatterload_copy
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[eb]"></a>__scatterload_zeroinit</STRONG> (Thumb, 28 bytes, Stack size unknown bytes, __scatter_zi.o(!!handler_zi), UNUSED)
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[7e]"></a>_printf_d</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, _printf_d.o(.ARM.Collect$$_printf_percent$$00000009))
<BR><BR>[Stack]<UL><LI>Max Depth = 56 + Unknown Stack Size
<LI>Call Chain = _printf_d &rArr; _printf_int_dec &rArr; _printf_int_common
</UL>
<BR>[Calls]<UL><LI><a href="#[7f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_printf_int_dec
</UL>
<P><STRONG><a name="[98]"></a>_printf_percent</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000))
<BR><BR>[Called By]<UL><LI><a href="#[97]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__printf
</UL>
<P><STRONG><a name="[ec]"></a>_printf_percent_end</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, _printf_percent_end.o(.ARM.Collect$$_printf_percent$$00000017))
<P><STRONG><a name="[8d]"></a>__rt_lib_init</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit.o(.ARM.Collect$$libinit$$00000000))
<BR><BR>[Called By]<UL><LI><a href="#[8c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_entry_li
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[80]"></a>__rt_lib_init_fp_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000001))
<BR><BR>[Calls]<UL><LI><a href="#[81]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_fp_init
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[82]"></a>__rt_lib_init_heap_2</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000005))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 64 + Unknown Stack Size
<LI>Call Chain = __rt_lib_init_heap_2 &rArr; _init_alloc &rArr; __rt_SIGRTMEM &rArr; __rt_SIGRTMEM_inner &rArr; __default_signal_display &rArr; _ttywrch
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[83]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_init_alloc
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[ed]"></a>__rt_lib_init_preinit_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000004))
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[ee]"></a>__rt_lib_init_heap_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000A))
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[84]"></a>__rt_lib_init_rand_2</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000D))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 8 + Unknown Stack Size
<LI>Call Chain = __rt_lib_init_rand_2 &rArr; _rand_init &rArr; srand
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[85]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_rand_init
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[ef]"></a>__rt_lib_init_user_alloc_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000C))
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[f0]"></a>__rt_lib_init_atexit_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001B))
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[f1]"></a>__rt_lib_init_clock_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000021))
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[f2]"></a>__rt_lib_init_fp_trap_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001F))
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[f3]"></a>__rt_lib_init_getenv_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000023))
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[f4]"></a>__rt_lib_init_lc_collate_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000011))
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[f5]"></a>__rt_lib_init_lc_ctype_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000013))
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[f6]"></a>__rt_lib_init_lc_monetary_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000015))
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[f7]"></a>__rt_lib_init_lc_numeric_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000017))
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[f8]"></a>__rt_lib_init_lc_time_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000019))
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[f9]"></a>__rt_lib_init_rand_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000E))
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[fa]"></a>__rt_lib_init_signal_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001D))
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[86]"></a>__rt_lib_init_stdio_2</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000024))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 120 + Unknown Stack Size
<LI>Call Chain = __rt_lib_init_stdio_2 &rArr; _initio &rArr; freopen &rArr; _fclose_internal &rArr; _fflush &rArr; _writebuf &rArr; _sys_write
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[87]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_initio
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[fb]"></a>__rt_lib_init_alloca_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000002E))
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[fc]"></a>__rt_lib_init_argv_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000002C))
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[fd]"></a>__rt_lib_init_cpp_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000032))
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[fe]"></a>__rt_lib_init_exceptions_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000030))
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[ff]"></a>__rt_lib_init_return</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000033))
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[100]"></a>__rt_lib_init_stdio_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000025))
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[92]"></a>__rt_lib_shutdown</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown.o(.ARM.Collect$$libshutdown$$00000000))
<BR><BR>[Called By]<UL><LI><a href="#[91]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_exit_ls
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[101]"></a>__rt_lib_shutdown_cpp_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000004))
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[102]"></a>__rt_lib_shutdown_fini_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000002))
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[88]"></a>__rt_lib_shutdown_stdio_2</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000005))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 104 + Unknown Stack Size
<LI>Call Chain = __rt_lib_shutdown_stdio_2 &rArr; _terminateio &rArr; _fclose_internal &rArr; _fflush &rArr; _writebuf &rArr; _sys_write
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[89]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_terminateio
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[103]"></a>__rt_lib_shutdown_fp_trap_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000009))
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[104]"></a>__rt_lib_shutdown_heap_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000011))
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[105]"></a>__rt_lib_shutdown_return</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000012))
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[106]"></a>__rt_lib_shutdown_signal_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C))
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[107]"></a>__rt_lib_shutdown_stdio_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000006))
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[108]"></a>__rt_lib_shutdown_user_alloc_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000E))
Initial commit
2023-12-11 13:43:05 +00:00
<P><STRONG><a name="[7b]"></a>__rt_entry</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __rtentry.o(.ARM.Collect$$rtentry$$00000000))
<BR><BR>[Called By]<UL><LI><a href="#[79]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__main
<LI><a href="#[7c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__scatterload_rt2
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[109]"></a>__rt_entry_presh_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$00000002))
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[8a]"></a>__rt_entry_sh</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __rtentry4.o(.ARM.Collect$$rtentry$$00000004))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 8 + Unknown Stack Size
<LI>Call Chain = __rt_entry_sh &rArr; __user_setup_stackheap
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[8b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__user_setup_stackheap
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[8c]"></a>__rt_entry_li</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$0000000A))
<BR><BR>[Calls]<UL><LI><a href="#[8d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_lib_init
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[10a]"></a>__rt_entry_postsh_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$00000009))
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[8e]"></a>__rt_entry_main</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$0000000D))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 176 + Unknown Stack Size
<LI>Call Chain = __rt_entry_main &rArr; main &rArr; SystemClock_Config &rArr; HAL_RCC_ClockConfig &rArr; HAL_RCC_GetSysClockFreq &rArr; __aeabi_uldivmod
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[8f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
<LI><a href="#[90]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;exit
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[10b]"></a>__rt_entry_postli_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$0000000C))
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[b2]"></a>__rt_exit</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, rtexit.o(.ARM.Collect$$rtexit$$00000000))
<BR><BR>[Called By]<UL><LI><a href="#[90]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;exit
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[91]"></a>__rt_exit_ls</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000003))
<BR><BR>[Calls]<UL><LI><a href="#[92]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_lib_shutdown
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[10c]"></a>__rt_exit_prels_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000002))
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[93]"></a>__rt_exit_exit</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000004))
<BR><BR>[Calls]<UL><LI><a href="#[94]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_sys_exit
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[c2]"></a>rand</STRONG> (Thumb, 48 bytes, Stack size 0 bytes, rand.o(.emb_text))
<BR><BR>[Called By]<UL><LI><a href="#[c3]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;CalcNewLineY
<LI><a href="#[c1]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;CalcNewLineX
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
<P><STRONG><a name="[a]"></a>Reset_Handler</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[10d]"></a>_maybe_terminate_alloc</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, maybetermalloc1.o(.emb_text), UNUSED)
Initial commit
2023-12-11 13:43:05 +00:00
<P><STRONG><a name="[26]"></a>ADC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[26]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;ADC_IRQHandler
</UL>
<BR>[Called By]<UL><LI><a href="#[26]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;ADC_IRQHandler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[28]"></a>CAN1_RX0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[29]"></a>CAN1_RX1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[2a]"></a>CAN1_SCE_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[27]"></a>CAN1_TX_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[54]"></a>CAN2_RX0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[55]"></a>CAN2_RX1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[56]"></a>CAN2_SCE_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[53]"></a>CAN2_TX_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[71]"></a>CEC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[62]"></a>DCMI_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[1f]"></a>DMA1_Stream0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[20]"></a>DMA1_Stream1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[21]"></a>DMA1_Stream2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[22]"></a>DMA1_Stream3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[23]"></a>DMA1_Stream4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[24]"></a>DMA1_Stream5_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[25]"></a>DMA1_Stream6_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[43]"></a>DMA1_Stream7_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[6d]"></a>DMA2D_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[4c]"></a>DMA2_Stream0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[4d]"></a>DMA2_Stream1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[4e]"></a>DMA2_Stream2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[4f]"></a>DMA2_Stream3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[50]"></a>DMA2_Stream4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[58]"></a>DMA2_Stream5_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[59]"></a>DMA2_Stream6_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[5a]"></a>DMA2_Stream7_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[51]"></a>ETH_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[52]"></a>ETH_WKUP_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[1a]"></a>EXTI0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[3c]"></a>EXTI15_10_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[1b]"></a>EXTI1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[1c]"></a>EXTI2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[1d]"></a>EXTI3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[1e]"></a>EXTI4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[2b]"></a>EXTI9_5_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[18]"></a>FLASH_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[44]"></a>FMC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[64]"></a>FPU_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[34]"></a>I2C1_ER_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[33]"></a>I2C1_EV_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[36]"></a>I2C2_ER_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[35]"></a>I2C2_EV_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[5d]"></a>I2C3_ER_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[5c]"></a>I2C3_EV_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[73]"></a>I2C4_ER_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[72]"></a>I2C4_EV_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[70]"></a>LPTIM1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[6c]"></a>LTDC_ER_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[6b]"></a>LTDC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[57]"></a>OTG_FS_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[3e]"></a>OTG_FS_WKUP_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[5f]"></a>OTG_HS_EP1_IN_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[5e]"></a>OTG_HS_EP1_OUT_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[61]"></a>OTG_HS_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[60]"></a>OTG_HS_WKUP_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[15]"></a>PVD_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[6f]"></a>QUADSPI_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[19]"></a>RCC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[63]"></a>RNG_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[3d]"></a>RTC_Alarm_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[17]"></a>RTC_WKUP_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[6a]"></a>SAI1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[6e]"></a>SAI2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[45]"></a>SDMMC1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[74]"></a>SPDIF_RX_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[37]"></a>SPI1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[38]"></a>SPI2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[47]"></a>SPI3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[67]"></a>SPI4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[68]"></a>SPI5_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[69]"></a>SPI6_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[16]"></a>TAMP_STAMP_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[2c]"></a>TIM1_BRK_TIM9_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[2f]"></a>TIM1_CC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[2e]"></a>TIM1_TRG_COM_TIM11_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[2d]"></a>TIM1_UP_TIM10_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[30]"></a>TIM2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[31]"></a>TIM3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[32]"></a>TIM4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[46]"></a>TIM5_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[4a]"></a>TIM6_DAC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[4b]"></a>TIM7_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[3f]"></a>TIM8_BRK_TIM12_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[42]"></a>TIM8_CC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[41]"></a>TIM8_TRG_COM_TIM14_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[40]"></a>TIM8_UP_TIM13_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[48]"></a>UART4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[49]"></a>UART5_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[65]"></a>UART7_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[66]"></a>UART8_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[39]"></a>USART1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[3a]"></a>USART2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[3b]"></a>USART3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[5b]"></a>USART6_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[14]"></a>WWDG_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f746xx.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[a4]"></a>__user_initial_stackheap</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, startup_stm32f746xx.o(.text))
<BR><BR>[Called By]<UL><LI><a href="#[8b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__user_setup_stackheap
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[cf]"></a>__aeabi_uldivmod</STRONG> (Thumb, 0 bytes, Stack size 48 bytes, lludivv7m.o(.text))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 48<LI>Call Chain = __aeabi_uldivmod
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[ce]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCC_GetSysClockFreq
</UL>
<P><STRONG><a name="[10e]"></a>_ll_udiv</STRONG> (Thumb, 238 bytes, Stack size 48 bytes, lludivv7m.o(.text), UNUSED)
<P><STRONG><a name="[95]"></a>__2printf</STRONG> (Thumb, 20 bytes, Stack size 24 bytes, noretval__2printf.o(.text))
<BR><BR>[Stack]<UL><LI>Max Depth = 128 + Unknown Stack Size
<LI>Call Chain = __2printf &rArr; _printf_char_file &rArr; _printf_char_common &rArr; __printf
</UL>
<BR>[Calls]<UL><LI><a href="#[96]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_printf_char_file
</UL>
<BR>[Called By]<UL><LI><a href="#[8f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[97]"></a>__printf</STRONG> (Thumb, 104 bytes, Stack size 24 bytes, __printf.o(.text))
<BR><BR>[Stack]<UL><LI>Max Depth = 24 + Unknown Stack Size
<LI>Call Chain = __printf
</UL>
<BR>[Calls]<UL><LI><a href="#[98]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_printf_percent
</UL>
<BR>[Called By]<UL><LI><a href="#[9b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_printf_char_common
</UL>
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[7f]"></a>_printf_int_dec</STRONG> (Thumb, 104 bytes, Stack size 24 bytes, _printf_dec.o(.text))
<BR><BR>[Stack]<UL><LI>Max Depth = 56<LI>Call Chain = _printf_int_dec &rArr; _printf_int_common
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[99]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_printf_int_common
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[7e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_printf_d
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[9a]"></a>srand</STRONG> (Thumb, 42 bytes, Stack size 8 bytes, rand.o(.text))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = srand
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[85]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_rand_init
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[85]"></a>_rand_init</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, rand.o(.text))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = _rand_init &rArr; srand
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[9a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;srand
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[84]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_lib_init_rand_2
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[9d]"></a>__aeabi_memclr4</STRONG> (Thumb, 0 bytes, Stack size 4 bytes, rt_memclr_w.o(.text))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = __aeabi_memclr4
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[d2]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_SPI_MspInit
<LI><a href="#[d6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_GPIO_Init
<LI><a href="#[e5]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SystemClock_Config
<LI><a href="#[a1]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_fclose_internal
<LI><a href="#[af]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;fopen
<LI><a href="#[87]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_initio
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[10f]"></a>__aeabi_memclr8</STRONG> (Thumb, 0 bytes, Stack size 4 bytes, rt_memclr_w.o(.text), UNUSED)
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[110]"></a>__rt_memclr_w</STRONG> (Thumb, 78 bytes, Stack size 4 bytes, rt_memclr_w.o(.text), UNUSED)
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[111]"></a>_memset_w</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, rt_memclr_w.o(.text), UNUSED)
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[e6]"></a>strcmp</STRONG> (Thumb, 104 bytes, Stack size 0 bytes, strcmpv7m_pel.o(.text))
<BR><BR>[Called By]<UL><LI><a href="#[ad]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_sys_open
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[112]"></a>__use_two_region_memory</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED)
Initial commit
2023-12-11 13:43:05 +00:00
<P><STRONG><a name="[7]"></a>__rt_heap_escrow</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED)
<P><STRONG><a name="[6]"></a>__rt_heap_expand</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED)
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[99]"></a>_printf_int_common</STRONG> (Thumb, 178 bytes, Stack size 32 bytes, _printf_intcommon.o(.text))
<BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = _printf_int_common
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[7f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_printf_int_dec
</UL>
<P><STRONG><a name="[96]"></a>_printf_char_file</STRONG> (Thumb, 32 bytes, Stack size 16 bytes, _printf_char_file.o(.text))
<BR><BR>[Stack]<UL><LI>Max Depth = 104 + Unknown Stack Size
<LI>Call Chain = _printf_char_file &rArr; _printf_char_common &rArr; __printf
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[9c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;ferror
<LI><a href="#[9b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_printf_char_common
</UL>
<BR>[Called By]<UL><LI><a href="#[95]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__2printf
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[9b]"></a>_printf_char_common</STRONG> (Thumb, 32 bytes, Stack size 64 bytes, _printf_char_common.o(.text))
<BR><BR>[Stack]<UL><LI>Max Depth = 88 + Unknown Stack Size
<LI>Call Chain = _printf_char_common &rArr; __printf
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[97]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__printf
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[96]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_printf_char_file
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[9c]"></a>ferror</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, ferror.o(.text))
<BR><BR>[Called By]<UL><LI><a href="#[96]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_printf_char_file
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[87]"></a>_initio</STRONG> (Thumb, 210 bytes, Stack size 8 bytes, initio.o(.text))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 120<LI>Call Chain = _initio &rArr; freopen &rArr; _fclose_internal &rArr; _fflush &rArr; _writebuf &rArr; _sys_write
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[9e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;freopen
<LI><a href="#[a0]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;setvbuf
<LI><a href="#[9d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_memclr4
<LI><a href="#[9f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_SIGRTRED
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[86]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_lib_init_stdio_2
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[89]"></a>_terminateio</STRONG> (Thumb, 56 bytes, Stack size 16 bytes, initio.o(.text))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 104<LI>Call Chain = _terminateio &rArr; _fclose_internal &rArr; _fflush &rArr; _writebuf &rArr; _sys_write
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[a1]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_fclose_internal
<LI><a href="#[a2]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;free
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[88]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_lib_shutdown_stdio_2
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[8b]"></a>__user_setup_stackheap</STRONG> (Thumb, 74 bytes, Stack size 8 bytes, sys_stackheap_outer.o(.text))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 8 + Unknown Stack Size
<LI>Call Chain = __user_setup_stackheap
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[a4]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__user_initial_stackheap
<LI><a href="#[a3]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__user_perproc_libspace
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[8a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_entry_sh
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[a2]"></a>free</STRONG> (Thumb, 78 bytes, Stack size 16 bytes, h1_free.o(.text))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = free
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[a5]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_heap_descriptor
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[a1]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_fclose_internal
<LI><a href="#[89]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_terminateio
<LI><a href="#[b6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__Heap_ProvideMemory
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[a6]"></a>__flsbuf</STRONG> (Thumb, 470 bytes, Stack size 32 bytes, flsbuf.o(.text), UNUSED)
<BR><BR>[Calls]<UL><LI><a href="#[aa]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_sys_istty
<LI><a href="#[a9]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_sys_flen
<LI><a href="#[a7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_deferredlazyseek
<LI><a href="#[ac]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_writebuf
<LI><a href="#[a8]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_seterr
<LI><a href="#[ab]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;malloc
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[e8]"></a>__flsbuf_byte</STRONG> (Thumb, 0 bytes, Stack size 32 bytes, flsbuf.o(.text))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = __flsbuf_byte
</UL>
<BR>[Called By]<UL><LI><a href="#[77]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;fputc
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[113]"></a>__flsbuf_wide</STRONG> (Thumb, 0 bytes, Stack size 32 bytes, flsbuf.o(.text), UNUSED)
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[a0]"></a>setvbuf</STRONG> (Thumb, 70 bytes, Stack size 16 bytes, setvbuf.o(.text))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = setvbuf
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[87]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_initio
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[9e]"></a>freopen</STRONG> (Thumb, 158 bytes, Stack size 24 bytes, fopen.o(.text))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 112<LI>Call Chain = freopen &rArr; _fclose_internal &rArr; _fflush &rArr; _writebuf &rArr; _sys_write
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[ad]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_sys_open
<LI><a href="#[a1]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_fclose_internal
<LI><a href="#[ae]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_fseek
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[af]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;fopen
<LI><a href="#[87]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_initio
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[af]"></a>fopen</STRONG> (Thumb, 74 bytes, Stack size 24 bytes, fopen.o(.text), UNUSED)
<BR><BR>[Calls]<UL><LI><a href="#[9e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;freopen
<LI><a href="#[9d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_memclr4
<LI><a href="#[ab]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;malloc
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[a1]"></a>_fclose_internal</STRONG> (Thumb, 76 bytes, Stack size 32 bytes, fclose.o(.text))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 88<LI>Call Chain = _fclose_internal &rArr; _fflush &rArr; _writebuf &rArr; _sys_write
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[b1]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_sys_close
<LI><a href="#[a2]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;free
<LI><a href="#[9d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_memclr4
<LI><a href="#[b0]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_fflush
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[9e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;freopen
<LI><a href="#[89]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_terminateio
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[114]"></a>fclose</STRONG> (Thumb, 0 bytes, Stack size 32 bytes, fclose.o(.text), UNUSED)
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[90]"></a>exit</STRONG> (Thumb, 18 bytes, Stack size 8 bytes, exit.o(.text))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 8 + Unknown Stack Size
<LI>Call Chain = exit
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[b2]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_exit
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[8e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_entry_main
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[9f]"></a>__rt_SIGRTRED</STRONG> (Thumb, 14 bytes, Stack size 8 bytes, defsig_rtred_outer.o(.text))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 40<LI>Call Chain = __rt_SIGRTRED &rArr; __rt_SIGRTRED_inner &rArr; __default_signal_display &rArr; _ttywrch
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[b3]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_SIGRTRED_inner
<LI><a href="#[b4]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__sig_exit
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[87]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_initio
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[115]"></a>__user_libspace</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, libspace.o(.text), UNUSED)
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[a3]"></a>__user_perproc_libspace</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, libspace.o(.text))
<BR><BR>[Called By]<UL><LI><a href="#[8b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__user_setup_stackheap
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[116]"></a>__user_perthread_libspace</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, libspace.o(.text), UNUSED)
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[a5]"></a>__rt_heap_descriptor</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, rt_heap_descriptor_intlibspace.o(.text))
<BR><BR>[Called By]<UL><LI><a href="#[a2]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;free
<LI><a href="#[ab]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;malloc
<LI><a href="#[83]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_init_alloc
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[117]"></a>__use_no_heap</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, hguard.o(.text), UNUSED)
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[118]"></a>__heap$guard</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, hguard.o(.text), UNUSED)
Initial commit
2023-12-11 13:43:05 +00:00
<P><STRONG><a name="[5]"></a>_terminate_user_alloc</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, init_alloc.o(.text), UNUSED)
<P><STRONG><a name="[1]"></a>_init_user_alloc</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, init_alloc.o(.text), UNUSED)
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[b5]"></a>__Heap_Full</STRONG> (Thumb, 34 bytes, Stack size 16 bytes, init_alloc.o(.text), UNUSED)
<BR><BR>[Calls]<UL><LI><a href="#[b6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__Heap_ProvideMemory
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[ab]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;malloc
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[b7]"></a>__Heap_Broken</STRONG> (Thumb, 6 bytes, Stack size 0 bytes, init_alloc.o(.text), UNUSED)
<BR><BR>[Calls]<UL><LI><a href="#[b8]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_SIGRTMEM
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[83]"></a>_init_alloc</STRONG> (Thumb, 94 bytes, Stack size 24 bytes, init_alloc.o(.text))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 64<LI>Call Chain = _init_alloc &rArr; __rt_SIGRTMEM &rArr; __rt_SIGRTMEM_inner &rArr; __default_signal_display &rArr; _ttywrch
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[b6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__Heap_ProvideMemory
<LI><a href="#[b9]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__Heap_Initialize
<LI><a href="#[b8]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_SIGRTMEM
<LI><a href="#[a5]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_heap_descriptor
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[82]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_lib_init_heap_2
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[ab]"></a>malloc</STRONG> (Thumb, 94 bytes, Stack size 16 bytes, h1_alloc.o(.text), UNUSED)
<BR><BR>[Calls]<UL><LI><a href="#[b5]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__Heap_Full
<LI><a href="#[a5]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_heap_descriptor
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[af]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;fopen
<LI><a href="#[a6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__flsbuf
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[ae]"></a>_fseek</STRONG> (Thumb, 242 bytes, Stack size 24 bytes, fseek.o(.text))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = _fseek &rArr; _ftell_internal
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[aa]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_sys_istty
<LI><a href="#[a9]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_sys_flen
<LI><a href="#[ba]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_ftell_internal
<LI><a href="#[a8]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_seterr
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[9e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;freopen
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[119]"></a>fseek</STRONG> (Thumb, 0 bytes, Stack size 24 bytes, fseek.o(.text), UNUSED)
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[a8]"></a>_seterr</STRONG> (Thumb, 20 bytes, Stack size 0 bytes, stdio.o(.text))
<BR><BR>[Called By]<UL><LI><a href="#[a6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__flsbuf
<LI><a href="#[ac]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_writebuf
<LI><a href="#[ae]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_fseek
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[ac]"></a>_writebuf</STRONG> (Thumb, 84 bytes, Stack size 32 bytes, stdio.o(.text))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 40<LI>Call Chain = _writebuf &rArr; _sys_write
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[bc]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_sys_write
<LI><a href="#[bb]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_sys_seek
<LI><a href="#[a8]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_seterr
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[a6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__flsbuf
<LI><a href="#[b0]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_fflush
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[b0]"></a>_fflush</STRONG> (Thumb, 70 bytes, Stack size 16 bytes, stdio.o(.text))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 56<LI>Call Chain = _fflush &rArr; _writebuf &rArr; _sys_write
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[ac]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_writebuf
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[a1]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_fclose_internal
<LI><a href="#[a7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_deferredlazyseek
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[a7]"></a>_deferredlazyseek</STRONG> (Thumb, 60 bytes, Stack size 8 bytes, stdio.o(.text), UNUSED)
<BR><BR>[Calls]<UL><LI><a href="#[b0]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_fflush
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[a6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__flsbuf
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[b4]"></a>__sig_exit</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, defsig_exit.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[94]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_sys_exit
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[b8]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_SIGRTMEM
<LI><a href="#[9f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_SIGRTRED
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[b3]"></a>__rt_SIGRTRED_inner</STRONG> (Thumb, 14 bytes, Stack size 8 bytes, defsig_rtred_inner.o(.text))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = __rt_SIGRTRED_inner &rArr; __default_signal_display &rArr; _ttywrch
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[bd]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__default_signal_display
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[9f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_SIGRTRED
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[b8]"></a>__rt_SIGRTMEM</STRONG> (Thumb, 14 bytes, Stack size 8 bytes, defsig_rtmem_outer.o(.text))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 40<LI>Call Chain = __rt_SIGRTMEM &rArr; __rt_SIGRTMEM_inner &rArr; __default_signal_display &rArr; _ttywrch
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[be]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_SIGRTMEM_inner
<LI><a href="#[b4]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__sig_exit
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[83]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_init_alloc
<LI><a href="#[b7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__Heap_Broken
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[94]"></a>_sys_exit</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, sys_exit.o(.text))
<BR><BR>[Called By]<UL><LI><a href="#[93]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_exit_exit
<LI><a href="#[b4]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__sig_exit
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[11a]"></a>__I$use$semihosting</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, use_no_semi.o(.text), UNUSED)
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[11b]"></a>__use_no_semihosting_swi</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, use_no_semi.o(.text), UNUSED)
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[b9]"></a>__Heap_Initialize</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, h1_init.o(.text))
<BR><BR>[Called By]<UL><LI><a href="#[83]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_init_alloc
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[11c]"></a>__semihosting_library_function</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, indicate_semi.o(.text), UNUSED)
Initial commit
2023-12-11 13:43:05 +00:00
<P><STRONG><a name="[8]"></a>__Heap_DescSize</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, h1_init.o(.text), UNUSED)
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[b6]"></a>__Heap_ProvideMemory</STRONG> (Thumb, 52 bytes, Stack size 0 bytes, h1_extend.o(.text))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = __Heap_ProvideMemory &rArr; free
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[a2]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;free
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[83]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_init_alloc
<LI><a href="#[b5]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__Heap_Full
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[ba]"></a>_ftell_internal</STRONG> (Thumb, 66 bytes, Stack size 8 bytes, ftell.o(.text))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = _ftell_internal
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[bf]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_errno_addr
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[ae]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_fseek
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[11d]"></a>ftell</STRONG> (Thumb, 0 bytes, Stack size 8 bytes, ftell.o(.text), UNUSED)
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[bd]"></a>__default_signal_display</STRONG> (Thumb, 50 bytes, Stack size 16 bytes, defsig_general.o(.text))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = __default_signal_display &rArr; _ttywrch
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[c0]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_ttywrch
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[be]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_SIGRTMEM_inner
<LI><a href="#[b3]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_SIGRTRED_inner
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[be]"></a>__rt_SIGRTMEM_inner</STRONG> (Thumb, 22 bytes, Stack size 8 bytes, defsig_rtmem_inner.o(.text))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = __rt_SIGRTMEM_inner &rArr; __default_signal_display &rArr; _ttywrch
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[bd]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__default_signal_display
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[b8]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_SIGRTMEM
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[c0]"></a>_ttywrch</STRONG> (Thumb, 14 bytes, Stack size 8 bytes, sys_wrch.o(.text))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = _ttywrch
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[bd]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__default_signal_display
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[bf]"></a>__aeabi_errno_addr</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, rt_errno_addr_intlibspace.o(.text))
<BR><BR>[Called By]<UL><LI><a href="#[ba]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_ftell_internal
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[11e]"></a>__errno$intlibspace</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, rt_errno_addr_intlibspace.o(.text), UNUSED)
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[11f]"></a>__rt_errno_addr$intlibspace</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, rt_errno_addr_intlibspace.o(.text), UNUSED)
Initial commit
2023-12-11 13:43:05 +00:00
<P><STRONG><a name="[e]"></a>BusFault_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, stm32f7xx_it.o(i.BusFault_Handler))
<BR><BR>[Calls]<UL><LI><a href="#[e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;BusFault_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;BusFault_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[11]"></a>DebugMon_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, stm32f7xx_it.o(i.DebugMon_Handler))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[d9]"></a>Error_Handler</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, main.o(i.Error_Handler))
<BR><BR>[Called By]<UL><LI><a href="#[d8]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_SPI2_Init
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[d3]"></a>HAL_GPIO_Init</STRONG> (Thumb, 530 bytes, Stack size 40 bytes, stm32f7xx_hal_gpio.o(i.HAL_GPIO_Init))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 40<LI>Call Chain = HAL_GPIO_Init
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[d2]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_SPI_MspInit
<LI><a href="#[d6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_GPIO_Init
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[d7]"></a>HAL_GPIO_WritePin</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, stm32f7xx_hal_gpio.o(i.HAL_GPIO_WritePin))
<BR><BR>[Called By]<UL><LI><a href="#[d6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_GPIO_Init
<LI><a href="#[e0]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Nokia_Init
<LI><a href="#[db]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NokiaData
<LI><a href="#[da]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NokiaControl
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[cc]"></a>HAL_GetTick</STRONG> (Thumb, 6 bytes, Stack size 0 bytes, stm32f7xx_hal.o(i.HAL_GetTick))
<BR><BR>[Called By]<UL><LI><a href="#[d0]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCC_OscConfig
<LI><a href="#[cd]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCC_ClockConfig
<LI><a href="#[cb]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_PWREx_EnableOverDrive
<LI><a href="#[8f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
<LI><a href="#[d4]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_SPI_Transmit
<LI><a href="#[e2]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SPI_WaitFlagStateUntilTimeout
<LI><a href="#[e1]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SPI_WaitFifoStateUntilTimeout
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[e4]"></a>HAL_IncTick</STRONG> (Thumb, 12 bytes, Stack size 0 bytes, stm32f7xx_hal.o(i.HAL_IncTick))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Called By]<UL><LI><a href="#[13]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SysTick_Handler
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[c4]"></a>HAL_Init</STRONG> (Thumb, 22 bytes, Stack size 8 bytes, stm32f7xx_hal.o(i.HAL_Init))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 40<LI>Call Chain = HAL_Init &rArr; HAL_InitTick &rArr; HAL_NVIC_SetPriority
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[c7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_MspInit
<LI><a href="#[c6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_InitTick
<LI><a href="#[c5]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_NVIC_SetPriorityGrouping
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[8f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[c6]"></a>HAL_InitTick</STRONG> (Thumb, 54 bytes, Stack size 16 bytes, stm32f7xx_hal.o(i.HAL_InitTick))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = HAL_InitTick &rArr; HAL_NVIC_SetPriority
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[c8]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_SYSTICK_Config
<LI><a href="#[c9]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_NVIC_SetPriority
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[cd]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCC_ClockConfig
<LI><a href="#[c4]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_Init
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[c7]"></a>HAL_MspInit</STRONG> (Thumb, 42 bytes, Stack size 8 bytes, stm32f7xx_hal_msp.o(i.HAL_MspInit))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = HAL_MspInit
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[c4]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_Init
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[c9]"></a>HAL_NVIC_SetPriority</STRONG> (Thumb, 60 bytes, Stack size 16 bytes, stm32f7xx_hal_cortex.o(i.HAL_NVIC_SetPriority))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = HAL_NVIC_SetPriority
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[ca]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__NVIC_SetPriority
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[c6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_InitTick
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[c5]"></a>HAL_NVIC_SetPriorityGrouping</STRONG> (Thumb, 28 bytes, Stack size 8 bytes, stm32f7xx_hal_cortex.o(i.HAL_NVIC_SetPriorityGrouping))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = HAL_NVIC_SetPriorityGrouping
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[c4]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_Init
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[cb]"></a>HAL_PWREx_EnableOverDrive</STRONG> (Thumb, 100 bytes, Stack size 24 bytes, stm32f7xx_hal_pwr_ex.o(i.HAL_PWREx_EnableOverDrive))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = HAL_PWREx_EnableOverDrive
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[cc]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_GetTick
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[e5]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SystemClock_Config
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[cd]"></a>HAL_RCC_ClockConfig</STRONG> (Thumb, 284 bytes, Stack size 32 bytes, stm32f7xx_hal_rcc.o(i.HAL_RCC_ClockConfig))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 88<LI>Call Chain = HAL_RCC_ClockConfig &rArr; HAL_RCC_GetSysClockFreq &rArr; __aeabi_uldivmod
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[cc]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_GetTick
<LI><a href="#[c6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_InitTick
<LI><a href="#[ce]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCC_GetSysClockFreq
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[e5]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SystemClock_Config
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[ce]"></a>HAL_RCC_GetSysClockFreq</STRONG> (Thumb, 88 bytes, Stack size 8 bytes, stm32f7xx_hal_rcc.o(i.HAL_RCC_GetSysClockFreq))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 56<LI>Call Chain = HAL_RCC_GetSysClockFreq &rArr; __aeabi_uldivmod
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[cf]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_uldivmod
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[cd]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCC_ClockConfig
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[d0]"></a>HAL_RCC_OscConfig</STRONG> (Thumb, 888 bytes, Stack size 40 bytes, stm32f7xx_hal_rcc.o(i.HAL_RCC_OscConfig))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 40<LI>Call Chain = HAL_RCC_OscConfig
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[cc]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_GetTick
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[e5]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SystemClock_Config
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[d1]"></a>HAL_SPI_Init</STRONG> (Thumb, 242 bytes, Stack size 24 bytes, stm32f7xx_hal_spi.o(i.HAL_SPI_Init))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 112<LI>Call Chain = HAL_SPI_Init &rArr; HAL_SPI_MspInit &rArr; HAL_GPIO_Init
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[d2]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_SPI_MspInit
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[d8]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_SPI2_Init
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[d2]"></a>HAL_SPI_MspInit</STRONG> (Thumb, 120 bytes, Stack size 48 bytes, spi.o(i.HAL_SPI_MspInit))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 88<LI>Call Chain = HAL_SPI_MspInit &rArr; HAL_GPIO_Init
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[d3]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_GPIO_Init
<LI><a href="#[9d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_memclr4
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[d1]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_SPI_Init
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[d4]"></a>HAL_SPI_Transmit</STRONG> (Thumb, 390 bytes, Stack size 40 bytes, stm32f7xx_hal_spi.o(i.HAL_SPI_Transmit))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 112<LI>Call Chain = HAL_SPI_Transmit &rArr; SPI_EndRxTxTransaction &rArr; SPI_WaitFifoStateUntilTimeout
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[cc]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_GetTick
<LI><a href="#[d5]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SPI_EndRxTxTransaction
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[db]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NokiaData
<LI><a href="#[da]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NokiaControl
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[c8]"></a>HAL_SYSTICK_Config</STRONG> (Thumb, 38 bytes, Stack size 8 bytes, stm32f7xx_hal_cortex.o(i.HAL_SYSTICK_Config))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = HAL_SYSTICK_Config
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[ca]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__NVIC_SetPriority
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[c6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_InitTick
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
<P><STRONG><a name="[c]"></a>HardFault_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, stm32f7xx_it.o(i.HardFault_Handler))
<BR><BR>[Calls]<UL><LI><a href="#[c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HardFault_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HardFault_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[e7]"></a>ITM_SendChar</STRONG> (Thumb, 32 bytes, Stack size 0 bytes, retarget_io.o(i.ITM_SendChar))
<BR><BR>[Called By]<UL><LI><a href="#[bc]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_sys_write
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[d6]"></a>MX_GPIO_Init</STRONG> (Thumb, 152 bytes, Stack size 48 bytes, gpio.o(i.MX_GPIO_Init))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 88<LI>Call Chain = MX_GPIO_Init &rArr; HAL_GPIO_Init
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[d3]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_GPIO_Init
<LI><a href="#[d7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_GPIO_WritePin
<LI><a href="#[9d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_memclr4
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[8f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[d8]"></a>MX_SPI2_Init</STRONG> (Thumb, 70 bytes, Stack size 16 bytes, spi.o(i.MX_SPI2_Init))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 128<LI>Call Chain = MX_SPI2_Init &rArr; HAL_SPI_Init &rArr; HAL_SPI_MspInit &rArr; HAL_GPIO_Init
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[d1]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_SPI_Init
<LI><a href="#[d9]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Error_Handler
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[8f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
<P><STRONG><a name="[d]"></a>MemManage_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, stm32f7xx_it.o(i.MemManage_Handler))
<BR><BR>[Calls]<UL><LI><a href="#[d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MemManage_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MemManage_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[b]"></a>NMI_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, stm32f7xx_it.o(i.NMI_Handler))
<BR><BR>[Calls]<UL><LI><a href="#[b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NMI_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NMI_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[dd]"></a>NokiaColorPixel</STRONG> (Thumb, 52 bytes, Stack size 12 bytes, nokia.o(i.NokiaColorPixel))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 12<LI>Call Chain = NokiaColorPixel
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[dc]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NokiaDrawLine
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[da]"></a>NokiaControl</STRONG> (Thumb, 64 bytes, Stack size 24 bytes, nokia.o(i.NokiaControl))
<BR><BR>[Stack]<UL><LI>Max Depth = 136<LI>Call Chain = NokiaControl &rArr; HAL_SPI_Transmit &rArr; SPI_EndRxTxTransaction &rArr; SPI_WaitFifoStateUntilTimeout
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[d4]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_SPI_Transmit
<LI><a href="#[d7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_GPIO_WritePin
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[e0]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Nokia_Init
<LI><a href="#[de]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NokiaGotoXY
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[db]"></a>NokiaData</STRONG> (Thumb, 38 bytes, Stack size 16 bytes, nokia.o(i.NokiaData))
<BR><BR>[Stack]<UL><LI>Max Depth = 128<LI>Call Chain = NokiaData &rArr; HAL_SPI_Transmit &rArr; SPI_EndRxTxTransaction &rArr; SPI_WaitFifoStateUntilTimeout
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[d4]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_SPI_Transmit
<LI><a href="#[d7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_GPIO_WritePin
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[df]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NokiaUpdate
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[dc]"></a>NokiaDrawLine</STRONG> (Thumb, 302 bytes, Stack size 32 bytes, nokia.o(i.NokiaDrawLine))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 44<LI>Call Chain = NokiaDrawLine &rArr; NokiaColorPixel
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[dd]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NokiaColorPixel
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[e3]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;ScreenSaver
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[de]"></a>NokiaGotoXY</STRONG> (Thumb, 28 bytes, Stack size 8 bytes, nokia.o(i.NokiaGotoXY))
<BR><BR>[Stack]<UL><LI>Max Depth = 144<LI>Call Chain = NokiaGotoXY &rArr; NokiaControl &rArr; HAL_SPI_Transmit &rArr; SPI_EndRxTxTransaction &rArr; SPI_WaitFifoStateUntilTimeout
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[da]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NokiaControl
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[df]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NokiaUpdate
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[df]"></a>NokiaUpdate</STRONG> (Thumb, 36 bytes, Stack size 16 bytes, nokia.o(i.NokiaUpdate))
<BR><BR>[Stack]<UL><LI>Max Depth = 160<LI>Call Chain = NokiaUpdate &rArr; NokiaGotoXY &rArr; NokiaControl &rArr; HAL_SPI_Transmit &rArr; SPI_EndRxTxTransaction &rArr; SPI_WaitFifoStateUntilTimeout
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[de]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NokiaGotoXY
<LI><a href="#[db]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NokiaData
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[8f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[e0]"></a>Nokia_Init</STRONG> (Thumb, 68 bytes, Stack size 8 bytes, nokia.o(i.Nokia_Init))
<BR><BR>[Stack]<UL><LI>Max Depth = 144<LI>Call Chain = Nokia_Init &rArr; NokiaControl &rArr; HAL_SPI_Transmit &rArr; SPI_EndRxTxTransaction &rArr; SPI_WaitFifoStateUntilTimeout
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[d7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_GPIO_WritePin
<LI><a href="#[da]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NokiaControl
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[8f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
<P><STRONG><a name="[12]"></a>PendSV_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, stm32f7xx_it.o(i.PendSV_Handler))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
<P><STRONG><a name="[10]"></a>SVC_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, stm32f7xx_it.o(i.SVC_Handler))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[e3]"></a>ScreenSaver</STRONG> (Thumb, 140 bytes, Stack size 24 bytes, lines_functions.o(i.ScreenSaver))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 68<LI>Call Chain = ScreenSaver &rArr; NokiaDrawLine &rArr; NokiaColorPixel
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[dc]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NokiaDrawLine
<LI><a href="#[c3]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;CalcNewLineY
<LI><a href="#[c1]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;CalcNewLineX
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[8f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
<P><STRONG><a name="[13]"></a>SysTick_Handler</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, stm32f7xx_it.o(i.SysTick_Handler))
Activate cache
2023-12-11 14:07:16 +00:00
<BR><BR>[Calls]<UL><LI><a href="#[e4]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_IncTick
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[e5]"></a>SystemClock_Config</STRONG> (Thumb, 150 bytes, Stack size 88 bytes, main.o(i.SystemClock_Config))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 176<LI>Call Chain = SystemClock_Config &rArr; HAL_RCC_ClockConfig &rArr; HAL_RCC_GetSysClockFreq &rArr; __aeabi_uldivmod
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[d0]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCC_OscConfig
<LI><a href="#[cd]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCC_ClockConfig
<LI><a href="#[cb]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_PWREx_EnableOverDrive
<LI><a href="#[9d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_memclr4
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[8f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
<P><STRONG><a name="[75]"></a>SystemInit</STRONG> (Thumb, 12 bytes, Stack size 0 bytes, system_stm32f7xx.o(i.SystemInit))
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(.text)
</UL>
<P><STRONG><a name="[f]"></a>UsageFault_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, stm32f7xx_it.o(i.UsageFault_Handler))
<BR><BR>[Calls]<UL><LI><a href="#[f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UsageFault_Handler
</UL>
<BR>[Called By]<UL><LI><a href="#[f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UsageFault_Handler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_stm32f746xx.o(RESET)
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[b1]"></a>_sys_close</STRONG> (Thumb, 24 bytes, Stack size 0 bytes, retarget_io.o(i._sys_close))
<BR><BR>[Called By]<UL><LI><a href="#[a1]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_fclose_internal
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[a9]"></a>_sys_flen</STRONG> (Thumb, 12 bytes, Stack size 0 bytes, retarget_io.o(i._sys_flen))
<BR><BR>[Called By]<UL><LI><a href="#[a6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__flsbuf
<LI><a href="#[ae]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_fseek
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[aa]"></a>_sys_istty</STRONG> (Thumb, 24 bytes, Stack size 0 bytes, retarget_io.o(i._sys_istty))
<BR><BR>[Called By]<UL><LI><a href="#[a6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__flsbuf
<LI><a href="#[ae]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_fseek
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[ad]"></a>_sys_open</STRONG> (Thumb, 68 bytes, Stack size 16 bytes, retarget_io.o(i._sys_open))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = _sys_open
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[e6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;strcmp
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[9e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;freopen
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[bb]"></a>_sys_seek</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, retarget_io.o(i._sys_seek))
<BR><BR>[Called By]<UL><LI><a href="#[ac]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_writebuf
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[bc]"></a>_sys_write</STRONG> (Thumb, 46 bytes, Stack size 8 bytes, retarget_io.o(i._sys_write))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = _sys_write
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[e7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;ITM_SendChar
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[ac]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_writebuf
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
<P><STRONG><a name="[77]"></a>fputc</STRONG> (Thumb, 26 bytes, Stack size 0 bytes, fputc.o(i.fputc))
<BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = fputc &rArr; __flsbuf_byte
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[e8]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__flsbuf_byte
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
<BR>[Address Reference Count : 1]<UL><LI> _printf_char_file.o(.text)
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[8f]"></a>main</STRONG> (Thumb, 178 bytes, Stack size 0 bytes, main.o(i.main))
<BR><BR>[Stack]<UL><LI>Max Depth = 176 + Unknown Stack Size
<LI>Call Chain = main &rArr; SystemClock_Config &rArr; HAL_RCC_ClockConfig &rArr; HAL_RCC_GetSysClockFreq &rArr; __aeabi_uldivmod
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[d8]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_SPI2_Init
<LI><a href="#[d6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_GPIO_Init
<LI><a href="#[c4]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_Init
<LI><a href="#[cc]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_GetTick
<LI><a href="#[e5]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SystemClock_Config
<LI><a href="#[e0]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Nokia_Init
<LI><a href="#[df]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;NokiaUpdate
<LI><a href="#[e3]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;ScreenSaver
<LI><a href="#[95]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__2printf
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[8e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_entry_main
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[81]"></a>_fp_init</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, fpinit.o(x$fpl$fpinit))
<BR><BR>[Called By]<UL><LI><a href="#[80]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_lib_init_fp_1
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[120]"></a>__fplib_config_fpu_vfp</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, fpinit.o(x$fpl$fpinit), UNUSED)
Initial commit
2023-12-11 13:43:05 +00:00
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[121]"></a>__fplib_config_pureend_doubles</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, fpinit.o(x$fpl$fpinit), UNUSED)
Initial commit
2023-12-11 13:43:05 +00:00
<P>
<H3>
Local Symbols
</H3>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[c1]"></a>CalcNewLineX</STRONG> (Thumb, 72 bytes, Stack size 16 bytes, lines_functions.o(i.CalcNewLineX))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = CalcNewLineX
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[c2]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;rand
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[e3]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;ScreenSaver
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[c3]"></a>CalcNewLineY</STRONG> (Thumb, 64 bytes, Stack size 16 bytes, lines_functions.o(i.CalcNewLineY))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = CalcNewLineY
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[c2]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;rand
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[e3]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;ScreenSaver
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[ca]"></a>__NVIC_SetPriority</STRONG> (Thumb, 34 bytes, Stack size 0 bytes, stm32f7xx_hal_cortex.o(i.__NVIC_SetPriority))
<BR><BR>[Called By]<UL><LI><a href="#[c8]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_SYSTICK_Config
<LI><a href="#[c9]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_NVIC_SetPriority
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[d5]"></a>SPI_EndRxTxTransaction</STRONG> (Thumb, 118 bytes, Stack size 24 bytes, stm32f7xx_hal_spi.o(i.SPI_EndRxTxTransaction))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 72<LI>Call Chain = SPI_EndRxTxTransaction &rArr; SPI_WaitFifoStateUntilTimeout
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[e2]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SPI_WaitFlagStateUntilTimeout
<LI><a href="#[e1]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SPI_WaitFifoStateUntilTimeout
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[d4]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_SPI_Transmit
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[e1]"></a>SPI_WaitFifoStateUntilTimeout</STRONG> (Thumb, 216 bytes, Stack size 48 bytes, stm32f7xx_hal_spi.o(i.SPI_WaitFifoStateUntilTimeout))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 48<LI>Call Chain = SPI_WaitFifoStateUntilTimeout
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[cc]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_GetTick
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[d5]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SPI_EndRxTxTransaction
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<P><STRONG><a name="[e2]"></a>SPI_WaitFlagStateUntilTimeout</STRONG> (Thumb, 180 bytes, Stack size 32 bytes, stm32f7xx_hal_spi.o(i.SPI_WaitFlagStateUntilTimeout))
Initial commit
2023-12-11 13:43:05 +00:00
<BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = SPI_WaitFlagStateUntilTimeout
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Calls]<UL><LI><a href="#[cc]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_GetTick
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
Activate cache
2023-12-11 14:07:16 +00:00
<BR>[Called By]<UL><LI><a href="#[d5]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SPI_EndRxTxTransaction
Initial commit
2023-12-11 13:43:05 +00:00
</UL>
<P><STRONG><a name="[78]"></a>_printf_input_char</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, _printf_char_common.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> _printf_char_common.o(.text)
</UL><P>
<H3>
Undefined Global Symbols
</H3><HR></body></html>
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