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Julien Chevalley
410
Drivers/CMSIS/Core_A/Source/irq_ctrl_gic.c
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410
Drivers/CMSIS/Core_A/Source/irq_ctrl_gic.c
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/**************************************************************************//**
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* @file irq_ctrl_gic.c
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* @brief Interrupt controller handling implementation for GIC
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* @version V1.0.1
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* @date 9. April 2018
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******************************************************************************/
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/*
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* Copyright (c) 2017 ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <stddef.h>
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#include "RTE_Components.h"
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#include CMSIS_device_header
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#include "irq_ctrl.h"
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#if defined(__GIC_PRESENT) && (__GIC_PRESENT == 1U)
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/// Number of implemented interrupt lines
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#ifndef IRQ_GIC_LINE_COUNT
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#define IRQ_GIC_LINE_COUNT (1020U)
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#endif
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static IRQHandler_t IRQTable[IRQ_GIC_LINE_COUNT] = { 0U };
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static uint32_t IRQ_ID0;
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/// Initialize interrupt controller.
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__WEAK int32_t IRQ_Initialize (void) {
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uint32_t i;
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for (i = 0U; i < IRQ_GIC_LINE_COUNT; i++) {
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IRQTable[i] = (IRQHandler_t)NULL;
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}
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GIC_Enable();
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return (0);
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}
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/// Register interrupt handler.
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__WEAK int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler) {
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int32_t status;
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if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
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IRQTable[irqn] = handler;
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status = 0;
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} else {
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status = -1;
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}
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return (status);
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}
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/// Get the registered interrupt handler.
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__WEAK IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn) {
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IRQHandler_t h;
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// Ignore CPUID field (software generated interrupts)
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irqn &= 0x3FFU;
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if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
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h = IRQTable[irqn];
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} else {
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h = (IRQHandler_t)0;
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}
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return (h);
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}
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/// Enable interrupt.
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__WEAK int32_t IRQ_Enable (IRQn_ID_t irqn) {
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int32_t status;
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if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
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GIC_EnableIRQ ((IRQn_Type)irqn);
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status = 0;
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} else {
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status = -1;
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}
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return (status);
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}
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/// Disable interrupt.
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__WEAK int32_t IRQ_Disable (IRQn_ID_t irqn) {
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int32_t status;
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if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
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GIC_DisableIRQ ((IRQn_Type)irqn);
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status = 0;
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} else {
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status = -1;
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}
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return (status);
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}
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/// Get interrupt enable state.
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__WEAK uint32_t IRQ_GetEnableState (IRQn_ID_t irqn) {
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uint32_t enable;
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if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
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enable = GIC_GetEnableIRQ((IRQn_Type)irqn);
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} else {
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enable = 0U;
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}
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return (enable);
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}
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/// Configure interrupt request mode.
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__WEAK int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) {
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uint32_t val;
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uint8_t cfg;
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uint8_t secure;
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uint8_t cpu;
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int32_t status = 0;
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if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
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// Check triggering mode
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val = (mode & IRQ_MODE_TRIG_Msk);
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if (val == IRQ_MODE_TRIG_LEVEL) {
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cfg = 0x00U;
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} else if (val == IRQ_MODE_TRIG_EDGE) {
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cfg = 0x02U;
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} else {
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cfg = 0x00U;
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status = -1;
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}
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// Check interrupt type
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val = mode & IRQ_MODE_TYPE_Msk;
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if (val != IRQ_MODE_TYPE_IRQ) {
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status = -1;
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}
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// Check interrupt domain
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val = mode & IRQ_MODE_DOMAIN_Msk;
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if (val == IRQ_MODE_DOMAIN_NONSECURE) {
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secure = 0U;
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} else {
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// Check security extensions support
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val = GIC_DistributorInfo() & (1UL << 10U);
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if (val != 0U) {
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// Security extensions are supported
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secure = 1U;
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} else {
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secure = 0U;
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status = -1;
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}
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}
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// Check interrupt CPU targets
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val = mode & IRQ_MODE_CPU_Msk;
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if (val == IRQ_MODE_CPU_ALL) {
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cpu = 0xFFU;
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} else {
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cpu = val >> IRQ_MODE_CPU_Pos;
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}
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// Apply configuration if no mode error
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if (status == 0) {
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GIC_SetConfiguration((IRQn_Type)irqn, cfg);
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GIC_SetTarget ((IRQn_Type)irqn, cpu);
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if (secure != 0U) {
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GIC_SetGroup ((IRQn_Type)irqn, secure);
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}
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}
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}
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return (status);
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}
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/// Get interrupt mode configuration.
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__WEAK uint32_t IRQ_GetMode (IRQn_ID_t irqn) {
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uint32_t mode;
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uint32_t val;
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if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
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mode = IRQ_MODE_TYPE_IRQ;
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// Get trigger mode
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val = GIC_GetConfiguration((IRQn_Type)irqn);
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if ((val & 2U) != 0U) {
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// Corresponding interrupt is edge triggered
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mode |= IRQ_MODE_TRIG_EDGE;
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} else {
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// Corresponding interrupt is level triggered
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mode |= IRQ_MODE_TRIG_LEVEL;
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}
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// Get interrupt CPU targets
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mode |= GIC_GetTarget ((IRQn_Type)irqn) << IRQ_MODE_CPU_Pos;
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} else {
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mode = IRQ_MODE_ERROR;
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}
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return (mode);
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}
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/// Get ID number of current interrupt request (IRQ).
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__WEAK IRQn_ID_t IRQ_GetActiveIRQ (void) {
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IRQn_ID_t irqn;
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uint32_t prio;
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/* Dummy read to avoid GIC 390 errata 801120 */
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GIC_GetHighPendingIRQ();
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irqn = GIC_AcknowledgePending();
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__DSB();
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/* Workaround GIC 390 errata 733075 (GIC-390_Errata_Notice_v6.pdf, 09-Jul-2014) */
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/* The following workaround code is for a single-core system. It would be */
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/* different in a multi-core system. */
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/* If the ID is 0 or 0x3FE or 0x3FF, then the GIC CPU interface may be locked-up */
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/* so unlock it, otherwise service the interrupt as normal. */
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/* Special IDs 1020=0x3FC and 1021=0x3FD are reserved values in GICv1 and GICv2 */
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/* so will not occur here. */
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if ((irqn == 0) || (irqn >= 0x3FE)) {
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/* Unlock the CPU interface with a dummy write to Interrupt Priority Register */
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prio = GIC_GetPriority((IRQn_Type)0);
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GIC_SetPriority ((IRQn_Type)0, prio);
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__DSB();
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if ((irqn == 0U) && ((GIC_GetIRQStatus ((IRQn_Type)irqn) & 1U) != 0U) && (IRQ_ID0 == 0U)) {
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/* If the ID is 0, is active and has not been seen before */
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IRQ_ID0 = 1U;
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}
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/* End of Workaround GIC 390 errata 733075 */
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}
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return (irqn);
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}
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/// Get ID number of current fast interrupt request (FIQ).
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__WEAK IRQn_ID_t IRQ_GetActiveFIQ (void) {
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return ((IRQn_ID_t)-1);
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}
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/// Signal end of interrupt processing.
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__WEAK int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn) {
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int32_t status;
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IRQn_Type irq = (IRQn_Type)irqn;
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irqn &= 0x3FFU;
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if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
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GIC_EndInterrupt (irq);
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if (irqn == 0) {
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IRQ_ID0 = 0U;
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}
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status = 0;
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} else {
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status = -1;
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}
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return (status);
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}
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/// Set interrupt pending flag.
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__WEAK int32_t IRQ_SetPending (IRQn_ID_t irqn) {
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int32_t status;
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if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
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GIC_SetPendingIRQ ((IRQn_Type)irqn);
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status = 0;
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} else {
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status = -1;
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}
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return (status);
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}
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/// Get interrupt pending flag.
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__WEAK uint32_t IRQ_GetPending (IRQn_ID_t irqn) {
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uint32_t pending;
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if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
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pending = GIC_GetPendingIRQ ((IRQn_Type)irqn);
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} else {
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pending = 0U;
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}
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return (pending & 1U);
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}
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/// Clear interrupt pending flag.
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__WEAK int32_t IRQ_ClearPending (IRQn_ID_t irqn) {
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int32_t status;
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if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
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GIC_ClearPendingIRQ ((IRQn_Type)irqn);
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status = 0;
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} else {
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status = -1;
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}
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return (status);
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}
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/// Set interrupt priority value.
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__WEAK int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority) {
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int32_t status;
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if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
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GIC_SetPriority ((IRQn_Type)irqn, priority);
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status = 0;
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} else {
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status = -1;
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}
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return (status);
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}
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/// Get interrupt priority.
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__WEAK uint32_t IRQ_GetPriority (IRQn_ID_t irqn) {
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uint32_t priority;
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if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
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priority = GIC_GetPriority ((IRQn_Type)irqn);
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} else {
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priority = IRQ_PRIORITY_ERROR;
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}
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return (priority);
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}
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/// Set priority masking threshold.
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__WEAK int32_t IRQ_SetPriorityMask (uint32_t priority) {
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GIC_SetInterfacePriorityMask (priority);
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return (0);
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}
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/// Get priority masking threshold
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__WEAK uint32_t IRQ_GetPriorityMask (void) {
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return GIC_GetInterfacePriorityMask();
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}
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/// Set priority grouping field split point
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__WEAK int32_t IRQ_SetPriorityGroupBits (uint32_t bits) {
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int32_t status;
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if (bits == IRQ_PRIORITY_Msk) {
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bits = 7U;
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}
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if (bits < 8U) {
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GIC_SetBinaryPoint (7U - bits);
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status = 0;
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} else {
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status = -1;
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}
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return (status);
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}
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/// Get priority grouping field split point
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__WEAK uint32_t IRQ_GetPriorityGroupBits (void) {
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uint32_t bp;
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bp = GIC_GetBinaryPoint() & 0x07U;
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return (7U - bp);
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}
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#endif
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