1313 lines
39 KiB
C
1313 lines
39 KiB
C
/**
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******************************************************************************
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* @file stm32f7xx_hal_dma.c
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* @author MCD Application Team
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* @brief DMA HAL module driver.
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*
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* This file provides firmware functions to manage the following
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* functionalities of the Direct Memory Access (DMA) peripheral:
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* + Initialization and de-initialization functions
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* + IO operation functions
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* + Peripheral State and errors functions
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@verbatim
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==============================================================================
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##### How to use this driver #####
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==============================================================================
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[..]
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(#) Enable and configure the peripheral to be connected to the DMA Stream
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(except for internal SRAM/FLASH memories: no initialization is
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necessary) please refer to Reference manual for connection between peripherals
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and DMA requests.
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(#) For a given Stream, program the required configuration through the following parameters:
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Transfer Direction, Source and Destination data formats,
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Circular, Normal or peripheral flow control mode, Stream Priority level,
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Source and Destination Increment mode, FIFO mode and its Threshold (if needed),
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Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.
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-@- Prior to HAL_DMA_Init() the clock must be enabled for DMA through the following macros:
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__HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE().
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*** Polling mode IO operation ***
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=================================
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[..]
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(+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
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address and destination address and the Length of data to be transferred.
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(+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
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case a fixed Timeout can be configured by User depending from his application.
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(+) Use HAL_DMA_Abort() function to abort the current transfer.
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*** Interrupt mode IO operation ***
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===================================
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[..]
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(+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
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(+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
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(+) Select Callbacks functions using HAL_DMA_RegisterCallback()
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(+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
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Source address and destination address and the Length of data to be transferred. In this
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case the DMA interrupt is configured
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(+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
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(+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
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add his own function by customization of function pointer XferCpltCallback and
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XferErrorCallback (i.e a member of DMA handle structure).
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[..]
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(#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
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detection.
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(#) Use HAL_DMA_Abort_IT() function to abort the current transfer
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-@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
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-@- The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is
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possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
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Half-Word data size for the peripheral to access its data register and set Word data size
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for the Memory to gain in access time. Each two half words will be packed and written in
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a single access to a Word in the Memory).
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-@- When FIFO is disabled, it is not allowed to configure different Data Sizes for Source
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and Destination. In this case the Peripheral Data Size will be applied to both Source
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and Destination.
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*** DMA HAL driver macros list ***
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=============================================
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[..]
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Below the list of most used macros in DMA HAL driver.
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(+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
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(+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
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(+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not.
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[..]
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(@) You can refer to the DMA HAL driver header file for more useful macros
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@endverbatim
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file in
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* the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f7xx_hal.h"
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/** @addtogroup STM32F7xx_HAL_Driver
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* @{
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*/
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/** @defgroup DMA DMA
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* @brief DMA HAL module driver
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* @{
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*/
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#ifdef HAL_DMA_MODULE_ENABLED
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/* Private types -------------------------------------------------------------*/
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typedef struct
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{
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__IO uint32_t ISR; /*!< DMA interrupt status register */
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__IO uint32_t Reserved0;
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__IO uint32_t IFCR; /*!< DMA interrupt flag clear register */
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} DMA_Base_Registers;
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/* Private variables ---------------------------------------------------------*/
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/* Private constants ---------------------------------------------------------*/
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/** @addtogroup DMA_Private_Constants
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* @{
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*/
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#define HAL_TIMEOUT_DMA_ABORT ((uint32_t)5) /* 5 ms */
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/**
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* @}
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*/
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/* Private macros ------------------------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/** @addtogroup DMA_Private_Functions
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* @{
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*/
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static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
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static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
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static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma);
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/**
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* @}
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*/
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/* Exported functions ---------------------------------------------------------*/
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/** @addtogroup DMA_Exported_Functions
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* @{
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*/
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/** @addtogroup DMA_Exported_Functions_Group1
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*
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@verbatim
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===============================================================================
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##### Initialization and de-initialization functions #####
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===============================================================================
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[..]
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This section provides functions allowing to initialize the DMA Stream source
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and destination addresses, incrementation and data sizes, transfer direction,
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circular/normal mode selection, memory-to-memory mode selection and Stream priority value.
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[..]
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The HAL_DMA_Init() function follows the DMA configuration procedures as described in
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reference manual.
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@endverbatim
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* @{
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*/
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/**
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* @brief Initialize the DMA according to the specified
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* parameters in the DMA_InitTypeDef and create the associated handle.
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* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
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* the configuration information for the specified DMA Stream.
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
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{
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uint32_t tmp = 0U;
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uint32_t tickstart = HAL_GetTick();
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DMA_Base_Registers *regs;
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/* Check the DMA peripheral state */
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if(hdma == NULL)
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{
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return HAL_ERROR;
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}
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/* Check the parameters */
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assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
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assert_param(IS_DMA_CHANNEL(hdma->Init.Channel));
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assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
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assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
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assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
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assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
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assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
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assert_param(IS_DMA_MODE(hdma->Init.Mode));
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assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
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assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode));
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/* Check the memory burst, peripheral burst and FIFO threshold parameters only
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when FIFO mode is enabled */
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if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE)
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{
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assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold));
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assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
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assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
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}
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/* Change DMA peripheral state */
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hdma->State = HAL_DMA_STATE_BUSY;
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/* Allocate lock resource */
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__HAL_UNLOCK(hdma);
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/* Disable the peripheral */
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__HAL_DMA_DISABLE(hdma);
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/* Check if the DMA Stream is effectively disabled */
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while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
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{
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/* Check for the Timeout */
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if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
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{
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/* Update error code */
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hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
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/* Change the DMA state */
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hdma->State = HAL_DMA_STATE_TIMEOUT;
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return HAL_TIMEOUT;
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}
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}
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/* Get the CR register value */
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tmp = hdma->Instance->CR;
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/* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
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tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
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DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \
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DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \
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DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM));
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/* Prepare the DMA Stream configuration */
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tmp |= hdma->Init.Channel | hdma->Init.Direction |
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hdma->Init.PeriphInc | hdma->Init.MemInc |
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hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
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hdma->Init.Mode | hdma->Init.Priority;
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/* the Memory burst and peripheral burst are not used when the FIFO is disabled */
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if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
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{
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/* Get memory burst and peripheral burst */
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tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst;
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}
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/* Write to DMA Stream CR register */
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hdma->Instance->CR = tmp;
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/* Get the FCR register value */
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tmp = hdma->Instance->FCR;
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/* Clear Direct mode and FIFO threshold bits */
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tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
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/* Prepare the DMA Stream FIFO configuration */
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tmp |= hdma->Init.FIFOMode;
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/* The FIFO threshold is not used when the FIFO mode is disabled */
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if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
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{
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/* Get the FIFO threshold */
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tmp |= hdma->Init.FIFOThreshold;
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/* Check compatibility between FIFO threshold level and size of the memory burst */
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/* for INCR4, INCR8, INCR16 bursts */
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if (hdma->Init.MemBurst != DMA_MBURST_SINGLE)
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{
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if (DMA_CheckFifoParam(hdma) != HAL_OK)
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{
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/* Update error code */
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hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
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/* Change the DMA state */
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hdma->State = HAL_DMA_STATE_READY;
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return HAL_ERROR;
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}
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}
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}
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/* Write to DMA Stream FCR */
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hdma->Instance->FCR = tmp;
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/* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
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DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
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regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
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/* Clear all interrupt flags */
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regs->IFCR = 0x3FU << hdma->StreamIndex;
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/* Initialize the error code */
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hdma->ErrorCode = HAL_DMA_ERROR_NONE;
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/* Initialize the DMA state */
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hdma->State = HAL_DMA_STATE_READY;
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return HAL_OK;
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}
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/**
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* @brief DeInitializes the DMA peripheral
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* @param hdma pointer to a DMA_HandleTypeDef structure that contains
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* the configuration information for the specified DMA Stream.
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
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{
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DMA_Base_Registers *regs;
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/* Check the DMA peripheral state */
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if(hdma == NULL)
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{
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return HAL_ERROR;
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}
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/* Check the DMA peripheral state */
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if(hdma->State == HAL_DMA_STATE_BUSY)
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{
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/* Return error status */
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return HAL_BUSY;
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}
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/* Check the parameters */
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assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
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/* Disable the selected DMA Streamx */
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__HAL_DMA_DISABLE(hdma);
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/* Reset DMA Streamx control register */
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hdma->Instance->CR = 0U;
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/* Reset DMA Streamx number of data to transfer register */
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hdma->Instance->NDTR = 0U;
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/* Reset DMA Streamx peripheral address register */
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hdma->Instance->PAR = 0U;
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/* Reset DMA Streamx memory 0 address register */
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hdma->Instance->M0AR = 0U;
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/* Reset DMA Streamx memory 1 address register */
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hdma->Instance->M1AR = 0U;
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/* Reset DMA Streamx FIFO control register */
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hdma->Instance->FCR = (uint32_t)0x00000021U;
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/* Get DMA steam Base Address */
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regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
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/* Clear all interrupt flags at correct offset within the register */
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regs->IFCR = 0x3FU << hdma->StreamIndex;
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/* Clean all callbacks */
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hdma->XferCpltCallback = NULL;
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hdma->XferHalfCpltCallback = NULL;
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hdma->XferM1CpltCallback = NULL;
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hdma->XferM1HalfCpltCallback = NULL;
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hdma->XferErrorCallback = NULL;
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hdma->XferAbortCallback = NULL;
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/* Reset the error code */
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hdma->ErrorCode = HAL_DMA_ERROR_NONE;
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/* Reset the DMA state */
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hdma->State = HAL_DMA_STATE_RESET;
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/* Release Lock */
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__HAL_UNLOCK(hdma);
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return HAL_OK;
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}
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/**
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* @}
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*/
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/** @addtogroup DMA_Exported_Functions_Group2
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*
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@verbatim
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===============================================================================
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##### IO operation functions #####
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===============================================================================
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[..] This section provides functions allowing to:
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(+) Configure the source, destination address and data length and Start DMA transfer
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(+) Configure the source, destination address and data length and
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Start DMA transfer with interrupt
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(+) Abort DMA transfer
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(+) Poll for transfer complete
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(+) Handle DMA interrupt request
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@endverbatim
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* @{
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*/
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/**
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* @brief Starts the DMA Transfer.
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* @param hdma pointer to a DMA_HandleTypeDef structure that contains
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* the configuration information for the specified DMA Stream.
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* @param SrcAddress The source memory Buffer address
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* @param DstAddress The destination memory Buffer address
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* @param DataLength The length of data to be transferred from source to destination
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
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{
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HAL_StatusTypeDef status = HAL_OK;
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/* Check the parameters */
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assert_param(IS_DMA_BUFFER_SIZE(DataLength));
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/* Process locked */
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__HAL_LOCK(hdma);
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if(HAL_DMA_STATE_READY == hdma->State)
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{
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/* Change DMA peripheral state */
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hdma->State = HAL_DMA_STATE_BUSY;
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/* Initialize the error code */
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hdma->ErrorCode = HAL_DMA_ERROR_NONE;
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/* Configure the source, destination address and the data length */
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DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
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/* Enable the Peripheral */
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__HAL_DMA_ENABLE(hdma);
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}
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else
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{
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/* Process unlocked */
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__HAL_UNLOCK(hdma);
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/* Return error status */
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status = HAL_BUSY;
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}
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return status;
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}
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/**
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* @brief Start the DMA Transfer with interrupt enabled.
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* @param hdma pointer to a DMA_HandleTypeDef structure that contains
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* the configuration information for the specified DMA Stream.
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* @param SrcAddress The source memory Buffer address
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* @param DstAddress The destination memory Buffer address
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* @param DataLength The length of data to be transferred from source to destination
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
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{
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HAL_StatusTypeDef status = HAL_OK;
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/* calculate DMA base and stream number */
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DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
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/* Check the parameters */
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assert_param(IS_DMA_BUFFER_SIZE(DataLength));
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/* Process locked */
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__HAL_LOCK(hdma);
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if(HAL_DMA_STATE_READY == hdma->State)
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{
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/* Change DMA peripheral state */
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hdma->State = HAL_DMA_STATE_BUSY;
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/* Initialize the error code */
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hdma->ErrorCode = HAL_DMA_ERROR_NONE;
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/* Configure the source, destination address and the data length */
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DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
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/* Clear all interrupt flags at correct offset within the register */
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regs->IFCR = 0x3FU << hdma->StreamIndex;
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/* Enable Common interrupts*/
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hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
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hdma->Instance->FCR |= DMA_IT_FE;
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if(hdma->XferHalfCpltCallback != NULL)
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{
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hdma->Instance->CR |= DMA_IT_HT;
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}
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/* Enable the Peripheral */
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__HAL_DMA_ENABLE(hdma);
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}
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else
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{
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/* Process unlocked */
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__HAL_UNLOCK(hdma);
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/* Return error status */
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status = HAL_BUSY;
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}
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return status;
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}
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|
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/**
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* @brief Aborts the DMA Transfer.
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* @param hdma pointer to a DMA_HandleTypeDef structure that contains
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* the configuration information for the specified DMA Stream.
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*
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* @note After disabling a DMA Stream, a check for wait until the DMA Stream is
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* effectively disabled is added. If a Stream is disabled
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* while a data transfer is ongoing, the current data will be transferred
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* and the Stream will be effectively disabled only after the transfer of
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* this single data is finished.
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* @retval HAL status
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*/
|
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HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
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{
|
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/* calculate DMA base and stream number */
|
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DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
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|
|
uint32_t tickstart = HAL_GetTick();
|
|
|
|
if(hdma->State != HAL_DMA_STATE_BUSY)
|
|
{
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
|
|
return HAL_ERROR;
|
|
}
|
|
else
|
|
{
|
|
/* Disable all the transfer interrupts */
|
|
hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
|
|
hdma->Instance->FCR &= ~(DMA_IT_FE);
|
|
|
|
if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
|
|
{
|
|
hdma->Instance->CR &= ~(DMA_IT_HT);
|
|
}
|
|
|
|
/* Disable the stream */
|
|
__HAL_DMA_DISABLE(hdma);
|
|
|
|
/* Check if the DMA Stream is effectively disabled */
|
|
while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
|
|
{
|
|
/* Check for the Timeout */
|
|
if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
|
|
{
|
|
/* Update error code */
|
|
hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
|
|
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_TIMEOUT;
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
|
|
/* Clear all interrupt flags at correct offset within the register */
|
|
regs->IFCR = 0x3FU << hdma->StreamIndex;
|
|
|
|
/* Change the DMA state*/
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
|
|
}
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Aborts the DMA Transfer in Interrupt mode.
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Stream.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
|
|
{
|
|
if(hdma->State != HAL_DMA_STATE_BUSY)
|
|
{
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
|
return HAL_ERROR;
|
|
}
|
|
else
|
|
{
|
|
/* Set Abort State */
|
|
hdma->State = HAL_DMA_STATE_ABORT;
|
|
|
|
/* Disable the stream */
|
|
__HAL_DMA_DISABLE(hdma);
|
|
}
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Polling for transfer complete.
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Stream.
|
|
* @param CompleteLevel Specifies the DMA level complete.
|
|
* @note The polling mode is kept in this version for legacy. it is recommended to use the IT model instead.
|
|
* This model could be used for debug purpose.
|
|
* @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode).
|
|
* @param Timeout Timeout duration.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
|
|
{
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
uint32_t mask_cpltlevel;
|
|
uint32_t tickstart = HAL_GetTick();
|
|
uint32_t tmpisr;
|
|
|
|
/* calculate DMA base and stream number */
|
|
DMA_Base_Registers *regs;
|
|
|
|
if(HAL_DMA_STATE_BUSY != hdma->State)
|
|
{
|
|
/* No transfer ongoing */
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
|
__HAL_UNLOCK(hdma);
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
/* Polling mode not supported in circular mode and double buffering mode */
|
|
if ((hdma->Instance->CR & DMA_SxCR_CIRC) != RESET)
|
|
{
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
/* Get the level transfer complete flag */
|
|
if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
|
|
{
|
|
/* Transfer Complete flag */
|
|
mask_cpltlevel = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
|
|
}
|
|
else
|
|
{
|
|
/* Half Transfer Complete flag */
|
|
mask_cpltlevel = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
|
|
}
|
|
|
|
regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
|
|
tmpisr = regs->ISR;
|
|
|
|
while(((tmpisr & mask_cpltlevel) == RESET) && ((hdma->ErrorCode & HAL_DMA_ERROR_TE) == RESET))
|
|
{
|
|
/* Check for the Timeout (Not applicable in circular mode)*/
|
|
if(Timeout != HAL_MAX_DELAY)
|
|
{
|
|
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
|
|
{
|
|
/* Update error code */
|
|
hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
|
|
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
|
|
/* Get the ISR register value */
|
|
tmpisr = regs->ISR;
|
|
|
|
if((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
|
|
{
|
|
/* Update error code */
|
|
hdma->ErrorCode |= HAL_DMA_ERROR_TE;
|
|
|
|
/* Clear the transfer error flag */
|
|
regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
|
|
}
|
|
|
|
if((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
|
|
{
|
|
/* Update error code */
|
|
hdma->ErrorCode |= HAL_DMA_ERROR_FE;
|
|
|
|
/* Clear the FIFO error flag */
|
|
regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
|
|
}
|
|
|
|
if((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
|
|
{
|
|
/* Update error code */
|
|
hdma->ErrorCode |= HAL_DMA_ERROR_DME;
|
|
|
|
/* Clear the Direct Mode error flag */
|
|
regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
|
|
}
|
|
}
|
|
|
|
if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
|
|
{
|
|
if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
|
|
{
|
|
HAL_DMA_Abort(hdma);
|
|
|
|
/* Clear the half transfer and transfer complete flags */
|
|
regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
|
|
|
|
/* Change the DMA state */
|
|
hdma->State= HAL_DMA_STATE_READY;
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
|
|
return HAL_ERROR;
|
|
}
|
|
}
|
|
|
|
/* Get the level transfer complete flag */
|
|
if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
|
|
{
|
|
/* Clear the half transfer and transfer complete flags */
|
|
regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
|
|
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
|
|
}
|
|
else
|
|
{
|
|
/* Clear the half transfer flag */
|
|
regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex;
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* @brief Handles DMA interrupt request.
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Stream.
|
|
* @retval None
|
|
*/
|
|
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
|
|
{
|
|
uint32_t tmpisr;
|
|
__IO uint32_t count = 0;
|
|
uint32_t timeout = SystemCoreClock / 9600;
|
|
|
|
/* calculate DMA base and stream number */
|
|
DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
|
|
|
|
tmpisr = regs->ISR;
|
|
|
|
/* Transfer Error Interrupt management ***************************************/
|
|
if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
|
|
{
|
|
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
|
|
{
|
|
/* Disable the transfer error interrupt */
|
|
hdma->Instance->CR &= ~(DMA_IT_TE);
|
|
|
|
/* Clear the transfer error flag */
|
|
regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
|
|
|
|
/* Update error code */
|
|
hdma->ErrorCode |= HAL_DMA_ERROR_TE;
|
|
}
|
|
}
|
|
/* FIFO Error Interrupt management ******************************************/
|
|
if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
|
|
{
|
|
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)
|
|
{
|
|
/* Clear the FIFO error flag */
|
|
regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
|
|
|
|
/* Update error code */
|
|
hdma->ErrorCode |= HAL_DMA_ERROR_FE;
|
|
}
|
|
}
|
|
/* Direct Mode Error Interrupt management ***********************************/
|
|
if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
|
|
{
|
|
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)
|
|
{
|
|
/* Clear the direct mode error flag */
|
|
regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
|
|
|
|
/* Update error code */
|
|
hdma->ErrorCode |= HAL_DMA_ERROR_DME;
|
|
}
|
|
}
|
|
/* Half Transfer Complete Interrupt management ******************************/
|
|
if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET)
|
|
{
|
|
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
|
|
{
|
|
/* Clear the half transfer complete flag */
|
|
regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
|
|
|
|
/* Multi_Buffering mode enabled */
|
|
if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
|
|
{
|
|
/* Current memory buffer used is Memory 0 */
|
|
if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
|
|
{
|
|
if(hdma->XferHalfCpltCallback != NULL)
|
|
{
|
|
/* Half transfer callback */
|
|
hdma->XferHalfCpltCallback(hdma);
|
|
}
|
|
}
|
|
/* Current memory buffer used is Memory 1 */
|
|
else
|
|
{
|
|
if(hdma->XferM1HalfCpltCallback != NULL)
|
|
{
|
|
/* Half transfer callback */
|
|
hdma->XferM1HalfCpltCallback(hdma);
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
|
|
if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
|
|
{
|
|
/* Disable the half transfer interrupt */
|
|
hdma->Instance->CR &= ~(DMA_IT_HT);
|
|
}
|
|
|
|
if(hdma->XferHalfCpltCallback != NULL)
|
|
{
|
|
/* Half transfer callback */
|
|
hdma->XferHalfCpltCallback(hdma);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/* Transfer Complete Interrupt management ***********************************/
|
|
if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET)
|
|
{
|
|
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
|
|
{
|
|
/* Clear the transfer complete flag */
|
|
regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
|
|
|
|
if(HAL_DMA_STATE_ABORT == hdma->State)
|
|
{
|
|
/* Disable all the transfer interrupts */
|
|
hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
|
|
hdma->Instance->FCR &= ~(DMA_IT_FE);
|
|
|
|
if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
|
|
{
|
|
hdma->Instance->CR &= ~(DMA_IT_HT);
|
|
}
|
|
|
|
/* Clear all interrupt flags at correct offset within the register */
|
|
regs->IFCR = 0x3FU << hdma->StreamIndex;
|
|
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
|
|
if(hdma->XferAbortCallback != NULL)
|
|
{
|
|
hdma->XferAbortCallback(hdma);
|
|
}
|
|
return;
|
|
}
|
|
|
|
if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
|
|
{
|
|
/* Current memory buffer used is Memory 0 */
|
|
if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
|
|
{
|
|
if(hdma->XferM1CpltCallback != NULL)
|
|
{
|
|
/* Transfer complete Callback for memory1 */
|
|
hdma->XferM1CpltCallback(hdma);
|
|
}
|
|
}
|
|
/* Current memory buffer used is Memory 1 */
|
|
else
|
|
{
|
|
if(hdma->XferCpltCallback != NULL)
|
|
{
|
|
/* Transfer complete Callback for memory0 */
|
|
hdma->XferCpltCallback(hdma);
|
|
}
|
|
}
|
|
}
|
|
/* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
|
|
else
|
|
{
|
|
if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
|
|
{
|
|
/* Disable the transfer complete interrupt */
|
|
hdma->Instance->CR &= ~(DMA_IT_TC);
|
|
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
|
|
}
|
|
|
|
if(hdma->XferCpltCallback != NULL)
|
|
{
|
|
/* Transfer complete callback */
|
|
hdma->XferCpltCallback(hdma);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/* manage error case */
|
|
if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
|
|
{
|
|
if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
|
|
{
|
|
hdma->State = HAL_DMA_STATE_ABORT;
|
|
|
|
/* Disable the stream */
|
|
__HAL_DMA_DISABLE(hdma);
|
|
|
|
do
|
|
{
|
|
if (++count > timeout)
|
|
{
|
|
break;
|
|
}
|
|
}
|
|
while((hdma->Instance->CR & DMA_SxCR_EN) != RESET);
|
|
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
|
|
}
|
|
|
|
if(hdma->XferErrorCallback != NULL)
|
|
{
|
|
/* Transfer error callback */
|
|
hdma->XferErrorCallback(hdma);
|
|
}
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Register callbacks
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Stream.
|
|
* @param CallbackID User Callback identifier
|
|
* a DMA_HandleTypeDef structure as parameter.
|
|
* @param pCallback pointer to private callbacsk function which has pointer to
|
|
* a DMA_HandleTypeDef structure as parameter.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))
|
|
{
|
|
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hdma);
|
|
|
|
if(HAL_DMA_STATE_READY == hdma->State)
|
|
{
|
|
switch (CallbackID)
|
|
{
|
|
case HAL_DMA_XFER_CPLT_CB_ID:
|
|
hdma->XferCpltCallback = pCallback;
|
|
break;
|
|
|
|
case HAL_DMA_XFER_HALFCPLT_CB_ID:
|
|
hdma->XferHalfCpltCallback = pCallback;
|
|
break;
|
|
|
|
case HAL_DMA_XFER_M1CPLT_CB_ID:
|
|
hdma->XferM1CpltCallback = pCallback;
|
|
break;
|
|
|
|
case HAL_DMA_XFER_M1HALFCPLT_CB_ID:
|
|
hdma->XferM1HalfCpltCallback = pCallback;
|
|
break;
|
|
|
|
case HAL_DMA_XFER_ERROR_CB_ID:
|
|
hdma->XferErrorCallback = pCallback;
|
|
break;
|
|
|
|
case HAL_DMA_XFER_ABORT_CB_ID:
|
|
hdma->XferAbortCallback = pCallback;
|
|
break;
|
|
|
|
default:
|
|
/* Return error status */
|
|
status = HAL_ERROR;
|
|
break;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Return error status */
|
|
status = HAL_ERROR;
|
|
}
|
|
|
|
/* Release Lock */
|
|
__HAL_UNLOCK(hdma);
|
|
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* @brief UnRegister callbacks
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Stream.
|
|
* @param CallbackID User Callback identifier
|
|
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
|
|
{
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hdma);
|
|
|
|
if(HAL_DMA_STATE_READY == hdma->State)
|
|
{
|
|
switch (CallbackID)
|
|
{
|
|
case HAL_DMA_XFER_CPLT_CB_ID:
|
|
hdma->XferCpltCallback = NULL;
|
|
break;
|
|
|
|
case HAL_DMA_XFER_HALFCPLT_CB_ID:
|
|
hdma->XferHalfCpltCallback = NULL;
|
|
break;
|
|
|
|
case HAL_DMA_XFER_M1CPLT_CB_ID:
|
|
hdma->XferM1CpltCallback = NULL;
|
|
break;
|
|
|
|
case HAL_DMA_XFER_M1HALFCPLT_CB_ID:
|
|
hdma->XferM1HalfCpltCallback = NULL;
|
|
break;
|
|
|
|
case HAL_DMA_XFER_ERROR_CB_ID:
|
|
hdma->XferErrorCallback = NULL;
|
|
break;
|
|
|
|
case HAL_DMA_XFER_ABORT_CB_ID:
|
|
hdma->XferAbortCallback = NULL;
|
|
break;
|
|
|
|
case HAL_DMA_XFER_ALL_CB_ID:
|
|
hdma->XferCpltCallback = NULL;
|
|
hdma->XferHalfCpltCallback = NULL;
|
|
hdma->XferM1CpltCallback = NULL;
|
|
hdma->XferM1HalfCpltCallback = NULL;
|
|
hdma->XferErrorCallback = NULL;
|
|
hdma->XferAbortCallback = NULL;
|
|
break;
|
|
|
|
default:
|
|
status = HAL_ERROR;
|
|
break;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
status = HAL_ERROR;
|
|
}
|
|
|
|
/* Release Lock */
|
|
__HAL_UNLOCK(hdma);
|
|
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @addtogroup DMA_Exported_Functions_Group3
|
|
*
|
|
@verbatim
|
|
===============================================================================
|
|
##### State and Errors functions #####
|
|
===============================================================================
|
|
[..]
|
|
This subsection provides functions allowing to
|
|
(+) Check the DMA state
|
|
(+) Get error code
|
|
|
|
@endverbatim
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Returns the DMA state.
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Stream.
|
|
* @retval HAL state
|
|
*/
|
|
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
|
|
{
|
|
return hdma->State;
|
|
}
|
|
|
|
/**
|
|
* @brief Return the DMA error code
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Stream.
|
|
* @retval DMA Error Code
|
|
*/
|
|
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
|
|
{
|
|
return hdma->ErrorCode;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @addtogroup DMA_Private_Functions
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Sets the DMA Transfer parameter.
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Stream.
|
|
* @param SrcAddress The source memory Buffer address
|
|
* @param DstAddress The destination memory Buffer address
|
|
* @param DataLength The length of data to be transferred from source to destination
|
|
* @retval HAL status
|
|
*/
|
|
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
|
{
|
|
/* Clear DBM bit */
|
|
hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM);
|
|
|
|
/* Configure DMA Stream data length */
|
|
hdma->Instance->NDTR = DataLength;
|
|
|
|
/* Memory to Peripheral */
|
|
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
|
|
{
|
|
/* Configure DMA Stream destination address */
|
|
hdma->Instance->PAR = DstAddress;
|
|
|
|
/* Configure DMA Stream source address */
|
|
hdma->Instance->M0AR = SrcAddress;
|
|
}
|
|
/* Peripheral to Memory */
|
|
else
|
|
{
|
|
/* Configure DMA Stream source address */
|
|
hdma->Instance->PAR = SrcAddress;
|
|
|
|
/* Configure DMA Stream destination address */
|
|
hdma->Instance->M0AR = DstAddress;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Returns the DMA Stream base address depending on stream number
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Stream.
|
|
* @retval Stream base address
|
|
*/
|
|
static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
|
|
{
|
|
uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U;
|
|
|
|
/* lookup table for necessary bitshift of flags within status registers */
|
|
static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};
|
|
hdma->StreamIndex = flagBitshiftOffset[stream_number];
|
|
|
|
if (stream_number > 3U)
|
|
{
|
|
/* return pointer to HISR and HIFCR */
|
|
hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U);
|
|
}
|
|
else
|
|
{
|
|
/* return pointer to LISR and LIFCR */
|
|
hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU));
|
|
}
|
|
|
|
return hdma->StreamBaseAddress;
|
|
}
|
|
|
|
/**
|
|
* @brief Check compatibility between FIFO threshold level and size of the memory burst
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Stream.
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
|
|
{
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
uint32_t tmp = hdma->Init.FIFOThreshold;
|
|
|
|
/* Memory Data size equal to Byte */
|
|
if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)
|
|
{
|
|
switch (tmp)
|
|
{
|
|
case DMA_FIFO_THRESHOLD_1QUARTERFULL:
|
|
case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
|
|
if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
|
|
{
|
|
status = HAL_ERROR;
|
|
}
|
|
break;
|
|
case DMA_FIFO_THRESHOLD_HALFFULL:
|
|
if (hdma->Init.MemBurst == DMA_MBURST_INC16)
|
|
{
|
|
status = HAL_ERROR;
|
|
}
|
|
break;
|
|
case DMA_FIFO_THRESHOLD_FULL:
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* Memory Data size equal to Half-Word */
|
|
else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
|
|
{
|
|
switch (tmp)
|
|
{
|
|
case DMA_FIFO_THRESHOLD_1QUARTERFULL:
|
|
case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
|
|
status = HAL_ERROR;
|
|
break;
|
|
case DMA_FIFO_THRESHOLD_HALFFULL:
|
|
if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
|
|
{
|
|
status = HAL_ERROR;
|
|
}
|
|
break;
|
|
case DMA_FIFO_THRESHOLD_FULL:
|
|
if (hdma->Init.MemBurst == DMA_MBURST_INC16)
|
|
{
|
|
status = HAL_ERROR;
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* Memory Data size equal to Word */
|
|
else
|
|
{
|
|
switch (tmp)
|
|
{
|
|
case DMA_FIFO_THRESHOLD_1QUARTERFULL:
|
|
case DMA_FIFO_THRESHOLD_HALFFULL:
|
|
case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
|
|
status = HAL_ERROR;
|
|
break;
|
|
case DMA_FIFO_THRESHOLD_FULL:
|
|
if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
|
|
{
|
|
status = HAL_ERROR;
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif /* HAL_DMA_MODULE_ENABLED */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|