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/**
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******************************************************************************
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* @file stm32f7xx_hal.h
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* @author MCD Application Team
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* @brief This file contains all the functions prototypes for the HAL
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* module driver.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F7xx_HAL_H
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#define __STM32F7xx_HAL_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f7xx_hal_conf.h"
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/** @addtogroup STM32F7xx_HAL_Driver
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* @{
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*/
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/** @addtogroup HAL
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup HAL_Exported_Constants HAL Exported Constants
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* @{
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*/
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/** @defgroup HAL_TICK_FREQ Tick Frequency
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* @{
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*/
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typedef enum
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{
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HAL_TICK_FREQ_10HZ = 100U,
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HAL_TICK_FREQ_100HZ = 10U,
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HAL_TICK_FREQ_1KHZ = 1U,
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HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
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} HAL_TickFreqTypeDef;
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/**
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* @}
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*/
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/** @defgroup SYSCFG_BootMode Boot Mode
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* @{
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*/
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#define SYSCFG_MEM_BOOT_ADD0 ((uint32_t)0x00000000U)
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#define SYSCFG_MEM_BOOT_ADD1 SYSCFG_MEMRMP_MEM_BOOT
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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/** @defgroup HAL_Exported_Macros HAL Exported Macros
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* @{
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*/
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/** @brief Freeze/Unfreeze Peripherals in Debug mode
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*/
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#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
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#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
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#define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
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#define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
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#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
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#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
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#define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
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#define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
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#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
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#define __HAL_DBGMCU_FREEZE_LPTIM1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_LPTIM1_STOP))
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#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
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#define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
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#define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
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#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
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#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
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#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
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#define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT))
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#define __HAL_DBGMCU_FREEZE_CAN1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP))
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#define __HAL_DBGMCU_FREEZE_CAN2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP))
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#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
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#define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
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#define __HAL_DBGMCU_FREEZE_TIM9() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP))
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#define __HAL_DBGMCU_FREEZE_TIM10() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP))
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#define __HAL_DBGMCU_FREEZE_TIM11() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP))
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#define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
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#define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
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#define __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
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#define __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
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#define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
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#define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
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#define __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
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#define __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
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#define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
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#define __HAL_DBGMCU_UNFREEZE_LPTIM1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_LPTIM1_STOP))
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#define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
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#define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
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#define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
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#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
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#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
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#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
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#define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT))
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#define __HAL_DBGMCU_UNFREEZE_CAN1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP))
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#define __HAL_DBGMCU_UNFREEZE_CAN2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP))
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#define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
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#define __HAL_DBGMCU_UNFREEZE_TIM8() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
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#define __HAL_DBGMCU_UNFREEZE_TIM9() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP))
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#define __HAL_DBGMCU_UNFREEZE_TIM10() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP))
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#define __HAL_DBGMCU_UNFREEZE_TIM11() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP))
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/** @brief FMC (NOR/RAM) mapped at 0x60000000 and SDRAM mapped at 0xC0000000
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*/
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#define __HAL_SYSCFG_REMAPMEMORY_FMC() (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_SWP_FMC))
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/** @brief FMC/SDRAM mapped at 0x60000000 (NOR/RAM) mapped at 0xC0000000
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*/
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#define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_SWP_FMC);\
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SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_SWP_FMC_0);\
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}while(0);
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/**
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* @brief Return the memory boot mapping as configured by user.
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* @retval The boot mode as configured by user. The returned value can be one
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* of the following values:
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* @arg @ref SYSCFG_MEM_BOOT_ADD0
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* @arg @ref SYSCFG_MEM_BOOT_ADD1
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*/
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#define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_BOOT)
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#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
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/** @brief SYSCFG Break Cortex-M7 Lockup lock.
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* Enable and lock the connection of Cortex-M7 LOCKUP (Hardfault) output to TIM1/8 Break input.
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* @note The selected configuration is locked and can be unlocked only by system reset.
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*/
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#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CBR, SYSCFG_CBR_CLL)
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/** @brief SYSCFG Break PVD lock.
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* Enable and lock the PVD connection to Timer1/8 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR1 register.
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* @note The selected configuration is locked and can be unlocked only by system reset.
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*/
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#define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CBR, SYSCFG_CBR_PVDL)
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#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
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/**
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* @}
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*/
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/** @defgroup HAL_Private_Macros HAL Private Macros
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* @{
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*/
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#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
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((FREQ) == HAL_TICK_FREQ_100HZ) || \
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((FREQ) == HAL_TICK_FREQ_1KHZ))
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/**
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* @}
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*/
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/* Exported functions --------------------------------------------------------*/
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/** @addtogroup HAL_Exported_Functions
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* @{
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*/
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/** @addtogroup HAL_Exported_Functions_Group1
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* @{
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*/
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/* Initialization and Configuration functions ******************************/
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HAL_StatusTypeDef HAL_Init(void);
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HAL_StatusTypeDef HAL_DeInit(void);
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void HAL_MspInit(void);
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void HAL_MspDeInit(void);
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HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
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/**
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* @}
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*/
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/* Exported variables ---------------------------------------------------------*/
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/** @addtogroup HAL_Exported_Variables
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* @{
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*/
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extern __IO uint32_t uwTick;
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extern uint32_t uwTickPrio;
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extern HAL_TickFreqTypeDef uwTickFreq;
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/**
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* @}
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*/
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/** @addtogroup HAL_Exported_Functions_Group2
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* @{
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*/
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/* Peripheral Control functions ************************************************/
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void HAL_IncTick(void);
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void HAL_Delay(uint32_t Delay);
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uint32_t HAL_GetTick(void);
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uint32_t HAL_GetTickPrio(void);
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HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
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HAL_TickFreqTypeDef HAL_GetTickFreq(void);
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void HAL_SuspendTick(void);
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void HAL_ResumeTick(void);
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uint32_t HAL_GetHalVersion(void);
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uint32_t HAL_GetREVID(void);
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uint32_t HAL_GetDEVID(void);
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uint32_t HAL_GetUIDw0(void);
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uint32_t HAL_GetUIDw1(void);
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uint32_t HAL_GetUIDw2(void);
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void HAL_DBGMCU_EnableDBGSleepMode(void);
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void HAL_DBGMCU_DisableDBGSleepMode(void);
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void HAL_DBGMCU_EnableDBGStopMode(void);
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void HAL_DBGMCU_DisableDBGStopMode(void);
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void HAL_DBGMCU_EnableDBGStandbyMode(void);
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void HAL_DBGMCU_DisableDBGStandbyMode(void);
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void HAL_EnableCompensationCell(void);
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void HAL_DisableCompensationCell(void);
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void HAL_EnableFMCMemorySwapping(void);
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void HAL_DisableFMCMemorySwapping(void);
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#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
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void HAL_EnableMemorySwappingBank(void);
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void HAL_DisableMemorySwappingBank(void);
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#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
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/**
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* @}
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*/
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||||
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||||
/**
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* @}
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*/
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/* Private types -------------------------------------------------------------*/
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||||
/* Private variables ---------------------------------------------------------*/
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/** @defgroup HAL_Private_Variables HAL Private Variables
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* @{
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||||
*/
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/**
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* @}
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||||
*/
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/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup HAL_Private_Constants HAL Private Constants
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
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||||
*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/**
|
||||
* @}
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||||
*/
|
||||
|
||||
/**
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||||
* @}
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||||
*/
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||||
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#ifdef __cplusplus
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}
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#endif
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#endif /* __STM32F7xx_HAL_H */
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@ -0,0 +1,404 @@
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/**
|
||||
******************************************************************************
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||||
* @file stm32f7xx_hal_cortex.h
|
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* @author MCD Application Team
|
||||
* @brief Header file of CORTEX HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file in
|
||||
* the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_CORTEX_H
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#define __STM32F7xx_HAL_CORTEX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
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||||
|
||||
/* Includes ------------------------------------------------------------------*/
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||||
#include "stm32f7xx_hal_def.h"
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||||
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||||
/** @addtogroup STM32F7xx_HAL_Driver
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||||
* @{
|
||||
*/
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||||
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||||
/** @addtogroup CORTEX
|
||||
* @{
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||||
*/
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/* Exported types ------------------------------------------------------------*/
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||||
/** @defgroup CORTEX_Exported_Types Cortex Exported Types
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||||
* @{
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||||
*/
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#if (__MPU_PRESENT == 1)
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/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
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* @brief MPU Region initialization structure
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* @{
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*/
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typedef struct
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||||
{
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uint8_t Enable; /*!< Specifies the status of the region.
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This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
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uint8_t Number; /*!< Specifies the number of the region to protect.
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||||
This parameter can be a value of @ref CORTEX_MPU_Region_Number */
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||||
uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
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||||
uint8_t Size; /*!< Specifies the size of the region to protect.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Size */
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||||
uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
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This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
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uint8_t TypeExtField; /*!< Specifies the TEX field level.
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||||
This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
|
||||
uint8_t AccessPermission; /*!< Specifies the region access permission type.
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||||
This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
|
||||
uint8_t DisableExec; /*!< Specifies the instruction access status.
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||||
This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
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||||
uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
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This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
|
||||
uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
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||||
This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
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||||
uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
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||||
This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
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||||
}MPU_Region_InitTypeDef;
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||||
/**
|
||||
* @}
|
||||
*/
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||||
#endif /* __MPU_PRESENT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
|
||||
* @{
|
||||
*/
|
||||
#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007U) /*!< 0 bits for pre-emption priority
|
||||
4 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006U) /*!< 1 bits for pre-emption priority
|
||||
3 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005U) /*!< 2 bits for pre-emption priority
|
||||
2 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004U) /*!< 3 bits for pre-emption priority
|
||||
1 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003U) /*!< 4 bits for pre-emption priority
|
||||
0 bits for subpriority */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
|
||||
* @{
|
||||
*/
|
||||
#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U)
|
||||
#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if (__MPU_PRESENT == 1)
|
||||
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
|
||||
* @{
|
||||
*/
|
||||
#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U)
|
||||
#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002U)
|
||||
#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004U)
|
||||
#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_ENABLE ((uint8_t)0x01U)
|
||||
#define MPU_REGION_DISABLE ((uint8_t)0x00U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
|
||||
* @{
|
||||
*/
|
||||
#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U)
|
||||
#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
|
||||
* @{
|
||||
*/
|
||||
#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U)
|
||||
#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
|
||||
* @{
|
||||
*/
|
||||
#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U)
|
||||
#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
|
||||
* @{
|
||||
*/
|
||||
#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U)
|
||||
#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
|
||||
* @{
|
||||
*/
|
||||
#define MPU_TEX_LEVEL0 ((uint8_t)0x00U)
|
||||
#define MPU_TEX_LEVEL1 ((uint8_t)0x01U)
|
||||
#define MPU_TEX_LEVEL2 ((uint8_t)0x02U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_SIZE_32B ((uint8_t)0x04U)
|
||||
#define MPU_REGION_SIZE_64B ((uint8_t)0x05U)
|
||||
#define MPU_REGION_SIZE_128B ((uint8_t)0x06U)
|
||||
#define MPU_REGION_SIZE_256B ((uint8_t)0x07U)
|
||||
#define MPU_REGION_SIZE_512B ((uint8_t)0x08U)
|
||||
#define MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
|
||||
#define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
|
||||
#define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
|
||||
#define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
|
||||
#define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
|
||||
#define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
|
||||
#define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
|
||||
#define MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
|
||||
#define MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
|
||||
#define MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
|
||||
#define MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
|
||||
#define MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
|
||||
#define MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
|
||||
#define MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
|
||||
#define MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
|
||||
#define MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
|
||||
#define MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
|
||||
#define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
|
||||
#define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
|
||||
#define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
|
||||
#define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
|
||||
#define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
|
||||
#define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_NO_ACCESS ((uint8_t)0x00U)
|
||||
#define MPU_REGION_PRIV_RW ((uint8_t)0x01U)
|
||||
#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U)
|
||||
#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U)
|
||||
#define MPU_REGION_PRIV_RO ((uint8_t)0x05U)
|
||||
#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_NUMBER0 ((uint8_t)0x00U)
|
||||
#define MPU_REGION_NUMBER1 ((uint8_t)0x01U)
|
||||
#define MPU_REGION_NUMBER2 ((uint8_t)0x02U)
|
||||
#define MPU_REGION_NUMBER3 ((uint8_t)0x03U)
|
||||
#define MPU_REGION_NUMBER4 ((uint8_t)0x04U)
|
||||
#define MPU_REGION_NUMBER5 ((uint8_t)0x05U)
|
||||
#define MPU_REGION_NUMBER6 ((uint8_t)0x06U)
|
||||
#define MPU_REGION_NUMBER7 ((uint8_t)0x07U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* __MPU_PRESENT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported Macros -----------------------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup CORTEX_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CORTEX_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
|
||||
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
|
||||
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_SystemReset(void);
|
||||
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CORTEX_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
#if (__MPU_PRESENT == 1)
|
||||
void HAL_MPU_Enable(uint32_t MPU_Control);
|
||||
void HAL_MPU_Disable(void);
|
||||
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
|
||||
#endif /* __MPU_PRESENT */
|
||||
uint32_t HAL_NVIC_GetPriorityGrouping(void);
|
||||
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
|
||||
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
|
||||
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
|
||||
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
|
||||
void HAL_SYSTICK_IRQHandler(void);
|
||||
void HAL_SYSTICK_Callback(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_1) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_2) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_3) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_4))
|
||||
|
||||
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
|
||||
|
||||
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
|
||||
|
||||
#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
|
||||
|
||||
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
|
||||
((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
|
||||
|
||||
#if (__MPU_PRESENT == 1)
|
||||
#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
|
||||
((STATE) == MPU_REGION_DISABLE))
|
||||
|
||||
#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
|
||||
((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
|
||||
|
||||
#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
|
||||
((STATE) == MPU_ACCESS_NOT_SHAREABLE))
|
||||
|
||||
#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
|
||||
((STATE) == MPU_ACCESS_NOT_CACHEABLE))
|
||||
|
||||
#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
|
||||
((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
|
||||
|
||||
#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
|
||||
((TYPE) == MPU_TEX_LEVEL1) || \
|
||||
((TYPE) == MPU_TEX_LEVEL2))
|
||||
|
||||
#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RW) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RW_URO) || \
|
||||
((TYPE) == MPU_REGION_FULL_ACCESS) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RO) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RO_URO))
|
||||
|
||||
#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER1) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER2) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER3) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER4) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER5) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER6) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER7))
|
||||
|
||||
#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_64B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_128B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_256B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_512B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_1KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_2KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_4KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_8KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_16KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_32KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_64KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_128KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_256KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_512KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_1MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_2MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_4MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_8MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_16MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_32MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_64MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_128MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_256MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_512MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_1GB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_2GB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_4GB))
|
||||
|
||||
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU)
|
||||
#endif /* __MPU_PRESENT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_CORTEX_H */
|
||||
|
||||
|
||||
@ -0,0 +1,218 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_def.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains HAL common defines, enumeration, macros and
|
||||
* structures definitions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_DEF
|
||||
#define __STM32F7xx_HAL_DEF
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx.h"
|
||||
#include "Legacy/stm32_hal_legacy.h"
|
||||
#include <stddef.h>
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief HAL Status structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_OK = 0x00U,
|
||||
HAL_ERROR = 0x01U,
|
||||
HAL_BUSY = 0x02U,
|
||||
HAL_TIMEOUT = 0x03U
|
||||
} HAL_StatusTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL Lock structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_UNLOCKED = 0x00U,
|
||||
HAL_LOCKED = 0x01U
|
||||
} HAL_LockTypeDef;
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
|
||||
|
||||
#define HAL_MAX_DELAY 0xFFFFFFFFU
|
||||
|
||||
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT))
|
||||
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
|
||||
|
||||
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
|
||||
(__DMA_HANDLE__).Parent = (__HANDLE__); \
|
||||
} while(0)
|
||||
|
||||
/** @brief Reset the Handle's State field.
|
||||
* @param __HANDLE__ specifies the Peripheral Handle.
|
||||
* @note This macro can be used for the following purpose:
|
||||
* - When the Handle is declared as local variable; before passing it as parameter
|
||||
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
|
||||
* to set to 0 the Handle's "State" field.
|
||||
* Otherwise, "State" field may have any random value and the first time the function
|
||||
* HAL_PPP_Init() is called, the low level hardware initialization will be missed
|
||||
* (i.e. HAL_PPP_MspInit() will not be executed).
|
||||
* - When there is a need to reconfigure the low level hardware: instead of calling
|
||||
* HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
|
||||
* In this later function, when the Handle's "State" field is set to 0, it will execute the function
|
||||
* HAL_PPP_MspInit() which will reconfigure the low level hardware.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
|
||||
|
||||
#if (USE_RTOS == 1U)
|
||||
/* Reserved for future use */
|
||||
#error "USE_RTOS should be 0 in the current HAL release"
|
||||
#else
|
||||
#define __HAL_LOCK(__HANDLE__) \
|
||||
do{ \
|
||||
if((__HANDLE__)->Lock == HAL_LOCKED) \
|
||||
{ \
|
||||
return HAL_BUSY; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Lock = HAL_LOCKED; \
|
||||
} \
|
||||
}while (0U)
|
||||
|
||||
#define __HAL_UNLOCK(__HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->Lock = HAL_UNLOCKED; \
|
||||
}while (0U)
|
||||
#endif /* USE_RTOS */
|
||||
|
||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
|
||||
#ifndef __weak
|
||||
#define __weak __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __packed
|
||||
#define __packed __attribute__((packed))
|
||||
#endif
|
||||
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
|
||||
#ifndef __weak
|
||||
#define __weak __attribute__((weak))
|
||||
#endif /* __weak */
|
||||
#ifndef __packed
|
||||
#define __packed __attribute__((__packed__))
|
||||
#endif /* __packed */
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
|
||||
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
|
||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#define __ALIGN_BEGIN
|
||||
#endif
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END __attribute__ ((aligned (4)))
|
||||
#endif
|
||||
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END __attribute__ ((aligned (4)))
|
||||
#endif /* __ALIGN_END */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#define __ALIGN_BEGIN
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#else
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END
|
||||
#endif /* __ALIGN_END */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#if defined (__CC_ARM) /* ARM Compiler V5*/
|
||||
#define __ALIGN_BEGIN __align(4)
|
||||
#elif defined (__ICCARM__) /* IAR Compiler */
|
||||
#define __ALIGN_BEGIN
|
||||
#endif /* __CC_ARM */
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
/* Macro to get variable aligned on 32-bytes,needed for cache maintenance purpose */
|
||||
#if defined (__GNUC__) /* GNU Compiler */
|
||||
#define ALIGN_32BYTES(buf) buf __attribute__ ((aligned (32)))
|
||||
#elif defined (__ICCARM__) /* IAR Compiler */
|
||||
#define ALIGN_32BYTES(buf) _Pragma("data_alignment=32") buf
|
||||
#elif defined (__CC_ARM) /* ARM Compiler */
|
||||
#define ALIGN_32BYTES(buf) __align(32) buf
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief __RAM_FUNC definition
|
||||
*/
|
||||
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
|
||||
/* ARM Compiler V4/V5 and V6
|
||||
--------------------------
|
||||
RAM functions are defined using the toolchain options.
|
||||
Functions that are executed in RAM should reside in a separate source module.
|
||||
Using the 'Options for File' dialog you can simply change the 'Code / Const'
|
||||
area of a module to a memory space in physical RAM.
|
||||
Available memory areas are declared in the 'Target' tab of the 'Options for Target'
|
||||
dialog.
|
||||
*/
|
||||
#define __RAM_FUNC
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
/* ICCARM Compiler
|
||||
---------------
|
||||
RAM functions are defined using a specific toolchain keyword "__ramfunc".
|
||||
*/
|
||||
#define __RAM_FUNC __ramfunc
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
/* GNU Compiler
|
||||
------------
|
||||
RAM functions are defined using a specific toolchain attribute
|
||||
"__attribute__((section(".RamFunc")))".
|
||||
*/
|
||||
#define __RAM_FUNC __attribute__((section(".RamFunc")))
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief __NOINLINE definition
|
||||
*/
|
||||
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ )
|
||||
/* ARM V4/V5 and V6 & GNU Compiler
|
||||
-------------------------------
|
||||
*/
|
||||
#define __NOINLINE __attribute__ ( (noinline) )
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
/* ICCARM Compiler
|
||||
---------------
|
||||
*/
|
||||
#define __NOINLINE _Pragma("optimize = no_inline")
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ___STM32F7xx_HAL_DEF */
|
||||
|
||||
|
||||
@ -0,0 +1,747 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_dma.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of DMA HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file in
|
||||
* the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_DMA_H
|
||||
#define __STM32F7xx_HAL_DMA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMA_Exported_Types DMA Exported Types
|
||||
* @brief DMA Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief DMA Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Channel; /*!< Specifies the channel used for the specified stream.
|
||||
This parameter can be a value of @ref DMAEx_Channel_selection */
|
||||
|
||||
uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
|
||||
from memory to memory or from peripheral to memory.
|
||||
This parameter can be a value of @ref DMA_Data_transfer_direction */
|
||||
|
||||
uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
|
||||
This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
|
||||
|
||||
uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
|
||||
This parameter can be a value of @ref DMA_Memory_incremented_mode */
|
||||
|
||||
uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
|
||||
This parameter can be a value of @ref DMA_Peripheral_data_size */
|
||||
|
||||
uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
|
||||
This parameter can be a value of @ref DMA_Memory_data_size */
|
||||
|
||||
uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx.
|
||||
This parameter can be a value of @ref DMA_mode
|
||||
@note The circular buffer mode cannot be used if the memory-to-memory
|
||||
data transfer is configured on the selected Stream */
|
||||
|
||||
uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx.
|
||||
This parameter can be a value of @ref DMA_Priority_level */
|
||||
|
||||
uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
|
||||
This parameter can be a value of @ref DMA_FIFO_direct_mode
|
||||
@note The Direct mode (FIFO mode disabled) cannot be used if the
|
||||
memory-to-memory data transfer is configured on the selected stream */
|
||||
|
||||
uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
|
||||
This parameter can be a value of @ref DMA_FIFO_threshold_level */
|
||||
|
||||
uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
|
||||
It specifies the amount of data to be transferred in a single non interruptible
|
||||
transaction.
|
||||
This parameter can be a value of @ref DMA_Memory_burst
|
||||
@note The burst mode is possible only if the address Increment mode is enabled. */
|
||||
|
||||
uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
|
||||
It specifies the amount of data to be transferred in a single non interruptible
|
||||
transaction.
|
||||
This parameter can be a value of @ref DMA_Peripheral_burst
|
||||
@note The burst mode is possible only if the address Increment mode is enabled. */
|
||||
}DMA_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DMA State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
|
||||
HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
|
||||
HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
|
||||
HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
|
||||
HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */
|
||||
HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */
|
||||
}HAL_DMA_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DMA Error Code structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
|
||||
HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half Transfer */
|
||||
}HAL_DMA_LevelCompleteTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DMA Error Code structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
|
||||
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */
|
||||
HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */
|
||||
HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */
|
||||
HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */
|
||||
HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */
|
||||
HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */
|
||||
}HAL_DMA_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DMA handle Structure definition
|
||||
*/
|
||||
typedef struct __DMA_HandleTypeDef
|
||||
{
|
||||
DMA_Stream_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
DMA_InitTypeDef Init; /*!< DMA communication parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< DMA locking object */
|
||||
|
||||
__IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
|
||||
|
||||
void *Parent; /*!< Parent object state */
|
||||
|
||||
void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
|
||||
|
||||
void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
|
||||
|
||||
void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */
|
||||
|
||||
void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */
|
||||
|
||||
void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
|
||||
|
||||
void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< DMA Error code */
|
||||
|
||||
uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */
|
||||
|
||||
uint32_t StreamIndex; /*!< DMA Stream Index */
|
||||
|
||||
}DMA_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMA_Exported_Constants DMA Exported Constants
|
||||
* @brief DMA Exported constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Error_Code DMA Error Code
|
||||
* @brief DMA Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */
|
||||
#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */
|
||||
#define HAL_DMA_ERROR_FE 0x00000002U /*!< FIFO error */
|
||||
#define HAL_DMA_ERROR_DME 0x00000004U /*!< Direct Mode error */
|
||||
#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
|
||||
#define HAL_DMA_ERROR_PARAM 0x00000040U /*!< Parameter error */
|
||||
#define HAL_DMA_ERROR_NO_XFER 0x00000080U /*!< Abort requested with no Xfer ongoing */
|
||||
#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
|
||||
* @brief DMA data transfer direction
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
|
||||
#define DMA_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direction */
|
||||
#define DMA_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
|
||||
* @brief DMA peripheral incremented mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PINC_ENABLE DMA_SxCR_PINC /*!< Peripheral increment mode enable */
|
||||
#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode disable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
|
||||
* @brief DMA memory incremented mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_MINC_ENABLE DMA_SxCR_MINC /*!< Memory increment mode enable */
|
||||
#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode disable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
|
||||
* @brief DMA peripheral data size
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */
|
||||
#define DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment: HalfWord */
|
||||
#define DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment: Word */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Memory_data_size DMA Memory data size
|
||||
* @brief DMA memory data size
|
||||
* @{
|
||||
*/
|
||||
#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */
|
||||
#define DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment: HalfWord */
|
||||
#define DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment: Word */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_mode DMA mode
|
||||
* @brief DMA mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_NORMAL 0x00000000U /*!< Normal mode */
|
||||
#define DMA_CIRCULAR DMA_SxCR_CIRC /*!< Circular mode */
|
||||
#define DMA_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Priority_level DMA Priority level
|
||||
* @brief DMA priority levels
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level: Low */
|
||||
#define DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level: Medium */
|
||||
#define DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level: High */
|
||||
#define DMA_PRIORITY_VERY_HIGH DMA_SxCR_PL /*!< Priority level: Very High */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
|
||||
* @brief DMA FIFO direct mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */
|
||||
#define DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode enable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
|
||||
* @brief DMA FIFO level
|
||||
* @{
|
||||
*/
|
||||
#define DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00000000U /*!< FIFO threshold 1 quart full configuration */
|
||||
#define DMA_FIFO_THRESHOLD_HALFFULL DMA_SxFCR_FTH_0 /*!< FIFO threshold half full configuration */
|
||||
#define DMA_FIFO_THRESHOLD_3QUARTERSFULL DMA_SxFCR_FTH_1 /*!< FIFO threshold 3 quarts full configuration */
|
||||
#define DMA_FIFO_THRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO threshold full configuration */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Memory_burst DMA Memory burst
|
||||
* @brief DMA memory burst
|
||||
* @{
|
||||
*/
|
||||
#define DMA_MBURST_SINGLE 0x00000000U
|
||||
#define DMA_MBURST_INC4 DMA_SxCR_MBURST_0
|
||||
#define DMA_MBURST_INC8 DMA_SxCR_MBURST_1
|
||||
#define DMA_MBURST_INC16 DMA_SxCR_MBURST
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Peripheral_burst DMA Peripheral burst
|
||||
* @brief DMA peripheral burst
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PBURST_SINGLE 0x00000000U
|
||||
#define DMA_PBURST_INC4 DMA_SxCR_PBURST_0
|
||||
#define DMA_PBURST_INC8 DMA_SxCR_PBURST_1
|
||||
#define DMA_PBURST_INC16 DMA_SxCR_PBURST
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
|
||||
* @brief DMA interrupts definition
|
||||
* @{
|
||||
*/
|
||||
#define DMA_IT_TC DMA_SxCR_TCIE
|
||||
#define DMA_IT_HT DMA_SxCR_HTIE
|
||||
#define DMA_IT_TE DMA_SxCR_TEIE
|
||||
#define DMA_IT_DME DMA_SxCR_DMEIE
|
||||
#define DMA_IT_FE 0x00000080U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_flag_definitions DMA flag definitions
|
||||
* @brief DMA flag definitions
|
||||
* @{
|
||||
*/
|
||||
#define DMA_FLAG_FEIF0_4 0x00000001U
|
||||
#define DMA_FLAG_DMEIF0_4 0x00000004U
|
||||
#define DMA_FLAG_TEIF0_4 0x00000008U
|
||||
#define DMA_FLAG_HTIF0_4 0x00000010U
|
||||
#define DMA_FLAG_TCIF0_4 0x00000020U
|
||||
#define DMA_FLAG_FEIF1_5 0x00000040U
|
||||
#define DMA_FLAG_DMEIF1_5 0x00000100U
|
||||
#define DMA_FLAG_TEIF1_5 0x00000200U
|
||||
#define DMA_FLAG_HTIF1_5 0x00000400U
|
||||
#define DMA_FLAG_TCIF1_5 0x00000800U
|
||||
#define DMA_FLAG_FEIF2_6 0x00010000U
|
||||
#define DMA_FLAG_DMEIF2_6 0x00040000U
|
||||
#define DMA_FLAG_TEIF2_6 0x00080000U
|
||||
#define DMA_FLAG_HTIF2_6 0x00100000U
|
||||
#define DMA_FLAG_TCIF2_6 0x00200000U
|
||||
#define DMA_FLAG_FEIF3_7 0x00400000U
|
||||
#define DMA_FLAG_DMEIF3_7 0x01000000U
|
||||
#define DMA_FLAG_TEIF3_7 0x02000000U
|
||||
#define DMA_FLAG_HTIF3_7 0x04000000U
|
||||
#define DMA_FLAG_TCIF3_7 0x08000000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/** @brief Reset DMA handle state
|
||||
* @param __HANDLE__ specifies the DMA handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Return the current DMA Stream FIFO filled level.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The FIFO filling state.
|
||||
* - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
|
||||
* and not empty.
|
||||
* - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
|
||||
* - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
|
||||
* - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
|
||||
* - DMA_FIFOStatus_Empty: when FIFO is empty
|
||||
* - DMA_FIFOStatus_Full: when FIFO is full
|
||||
*/
|
||||
#define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
|
||||
|
||||
/**
|
||||
* @brief Enable the specified DMA Stream.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
|
||||
|
||||
/**
|
||||
* @brief Disable the specified DMA Stream.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
|
||||
|
||||
/* Interrupt & Flag management */
|
||||
|
||||
/**
|
||||
* @brief Return the current DMA Stream transfer complete flag.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The specified transfer complete flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
|
||||
DMA_FLAG_TCIF3_7)
|
||||
|
||||
/**
|
||||
* @brief Return the current DMA Stream half transfer complete flag.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The specified half transfer complete flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
|
||||
DMA_FLAG_HTIF3_7)
|
||||
|
||||
/**
|
||||
* @brief Return the current DMA Stream transfer error flag.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The specified transfer error flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
|
||||
DMA_FLAG_TEIF3_7)
|
||||
|
||||
/**
|
||||
* @brief Return the current DMA Stream FIFO error flag.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The specified FIFO error flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
|
||||
DMA_FLAG_FEIF3_7)
|
||||
|
||||
/**
|
||||
* @brief Return the current DMA Stream direct mode error flag.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The specified direct mode error flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
|
||||
DMA_FLAG_DMEIF3_7)
|
||||
|
||||
/**
|
||||
* @brief Get the DMA Stream pending flags.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @param __FLAG__ Get the specified flag.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_FLAG_TCIFx: Transfer complete flag.
|
||||
* @arg DMA_FLAG_HTIFx: Half transfer complete flag.
|
||||
* @arg DMA_FLAG_TEIFx: Transfer error flag.
|
||||
* @arg DMA_FLAG_DMEIFx: Direct mode error flag.
|
||||
* @arg DMA_FLAG_FEIFx: FIFO error flag.
|
||||
* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
|
||||
* @retval The state of FLAG (SET or RESET).
|
||||
*/
|
||||
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
|
||||
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
|
||||
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
|
||||
|
||||
/**
|
||||
* @brief Clear the DMA Stream pending flags.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_FLAG_TCIFx: Transfer complete flag.
|
||||
* @arg DMA_FLAG_HTIFx: Half transfer complete flag.
|
||||
* @arg DMA_FLAG_TEIFx: Transfer error flag.
|
||||
* @arg DMA_FLAG_DMEIFx: Direct mode error flag.
|
||||
* @arg DMA_FLAG_FEIFx: FIFO error flag.
|
||||
* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
|
||||
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
|
||||
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
|
||||
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
|
||||
|
||||
/**
|
||||
* @brief Enable the specified DMA Stream interrupts.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask.
|
||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask.
|
||||
* @arg DMA_IT_TE: Transfer error interrupt mask.
|
||||
* @arg DMA_IT_FE: FIFO error interrupt mask.
|
||||
* @arg DMA_IT_DME: Direct mode error interrupt.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
|
||||
((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
|
||||
|
||||
/**
|
||||
* @brief Disable the specified DMA Stream interrupts.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask.
|
||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask.
|
||||
* @arg DMA_IT_TE: Transfer error interrupt mask.
|
||||
* @arg DMA_IT_FE: FIFO error interrupt mask.
|
||||
* @arg DMA_IT_DME: Direct mode error interrupt.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
|
||||
((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified DMA Stream interrupt is enabled or not.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @param __INTERRUPT__ specifies the DMA interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask.
|
||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask.
|
||||
* @arg DMA_IT_TE: Transfer error interrupt mask.
|
||||
* @arg DMA_IT_FE: FIFO error interrupt mask.
|
||||
* @arg DMA_IT_DME: Direct mode error interrupt.
|
||||
* @retval The state of DMA_IT.
|
||||
*/
|
||||
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
|
||||
((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
|
||||
((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
|
||||
|
||||
/**
|
||||
* @brief Writes the number of data units to be transferred on the DMA Stream.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @param __COUNTER__ Number of data units to be transferred (from 0 to 65535)
|
||||
* Number of data items depends only on the Peripheral data format.
|
||||
*
|
||||
* @note If Peripheral data format is Bytes: number of data units is equal
|
||||
* to total number of bytes to be transferred.
|
||||
*
|
||||
* @note If Peripheral data format is Half-Word: number of data units is
|
||||
* equal to total number of bytes to be transferred / 2.
|
||||
*
|
||||
* @note If Peripheral data format is Word: number of data units is equal
|
||||
* to total number of bytes to be transferred / 4.
|
||||
*
|
||||
* @retval The number of remaining data units in the current DMAy Streamx transfer.
|
||||
*/
|
||||
#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
|
||||
|
||||
/**
|
||||
* @brief Returns the number of remaining data units in the current DMAy Streamx transfer.
|
||||
* @param __HANDLE__ DMA handle
|
||||
*
|
||||
* @retval The number of remaining data units in the current DMA Stream transfer.
|
||||
*/
|
||||
#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
|
||||
|
||||
|
||||
/* Include DMA HAL Extension module */
|
||||
#include "stm32f7xx_hal_dma_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMA_Exported_Functions DMA Exported Functions
|
||||
* @brief DMA Exported functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
|
||||
* @brief I/O operation functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
||||
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
||||
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
|
||||
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
|
||||
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
|
||||
* @brief Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
|
||||
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private Constants -------------------------------------------------------------*/
|
||||
/** @defgroup DMA_Private_Constants DMA Private Constants
|
||||
* @brief DMA private defines and constants
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup DMA_Private_Macros DMA Private Macros
|
||||
* @brief DMA private macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
|
||||
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
|
||||
((DIRECTION) == DMA_MEMORY_TO_MEMORY))
|
||||
|
||||
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
|
||||
|
||||
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
|
||||
((STATE) == DMA_PINC_DISABLE))
|
||||
|
||||
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
|
||||
((STATE) == DMA_MINC_DISABLE))
|
||||
|
||||
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
|
||||
((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
|
||||
((SIZE) == DMA_PDATAALIGN_WORD))
|
||||
|
||||
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
|
||||
((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
|
||||
((SIZE) == DMA_MDATAALIGN_WORD ))
|
||||
|
||||
#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
|
||||
((MODE) == DMA_CIRCULAR) || \
|
||||
((MODE) == DMA_PFCTRL))
|
||||
|
||||
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
|
||||
((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
|
||||
((PRIORITY) == DMA_PRIORITY_HIGH) || \
|
||||
((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
|
||||
|
||||
#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
|
||||
((STATE) == DMA_FIFOMODE_ENABLE))
|
||||
|
||||
#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
|
||||
((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
|
||||
((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
|
||||
((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
|
||||
|
||||
#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
|
||||
((BURST) == DMA_MBURST_INC4) || \
|
||||
((BURST) == DMA_MBURST_INC8) || \
|
||||
((BURST) == DMA_MBURST_INC16))
|
||||
|
||||
#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
|
||||
((BURST) == DMA_PBURST_INC4) || \
|
||||
((BURST) == DMA_PBURST_INC8) || \
|
||||
((BURST) == DMA_PBURST_INC16))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup DMA_Private_Functions DMA Private Functions
|
||||
* @brief DMA private functions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_DMA_H */
|
||||
|
||||
@ -0,0 +1,183 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_dma_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of DMA HAL extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file in
|
||||
* the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_DMA_EX_H
|
||||
#define __STM32F7xx_HAL_DMA_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMAEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
|
||||
* @brief DMAEx Exported types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL DMA Memory definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
MEMORY0 = 0x00U, /*!< Memory 0 */
|
||||
MEMORY1 = 0x01U, /*!< Memory 1 */
|
||||
|
||||
}HAL_DMA_MemoryTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMA_Exported_Constants DMA Exported Constants
|
||||
* @brief DMA Exported constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_Channel_selection DMA Channel selection
|
||||
* @brief DMAEx channel selection
|
||||
* @{
|
||||
*/
|
||||
#define DMA_CHANNEL_0 0x00000000U /*!< DMA Channel 0 */
|
||||
#define DMA_CHANNEL_1 0x02000000U /*!< DMA Channel 1 */
|
||||
#define DMA_CHANNEL_2 0x04000000U /*!< DMA Channel 2 */
|
||||
#define DMA_CHANNEL_3 0x06000000U /*!< DMA Channel 3 */
|
||||
#define DMA_CHANNEL_4 0x08000000U /*!< DMA Channel 4 */
|
||||
#define DMA_CHANNEL_5 0x0A000000U /*!< DMA Channel 5 */
|
||||
#define DMA_CHANNEL_6 0x0C000000U /*!< DMA Channel 6 */
|
||||
#define DMA_CHANNEL_7 0x0E000000U /*!< DMA Channel 7 */
|
||||
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\
|
||||
defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\
|
||||
defined (STM32F779xx) || defined (STM32F730xx)
|
||||
#define DMA_CHANNEL_8 0x10000000U /*!< DMA Channel 8 */
|
||||
#define DMA_CHANNEL_9 0x12000000U /*!< DMA Channel 9 */
|
||||
#define DMA_CHANNEL_10 0x14000000U /*!< DMA Channel 10*/
|
||||
#define DMA_CHANNEL_11 0x16000000U /*!< DMA Channel 11*/
|
||||
#define DMA_CHANNEL_12 0x18000000U /*!< DMA Channel 12*/
|
||||
#define DMA_CHANNEL_13 0x1A000000U /*!< DMA Channel 13*/
|
||||
#define DMA_CHANNEL_14 0x1C000000U /*!< DMA Channel 14*/
|
||||
#define DMA_CHANNEL_15 0x1E000000U /*!< DMA Channel 15*/
|
||||
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||
|
||||
STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
|
||||
* @brief DMAEx Exported functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions
|
||||
* @brief Extended features functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* IO operation functions *******************************************************/
|
||||
HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
|
||||
HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
|
||||
HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup DMAEx_Private_Macros DMA Private Macros
|
||||
* @brief DMAEx private macros
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\
|
||||
defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\
|
||||
defined (STM32F779xx) || defined (STM32F730xx)
|
||||
#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
|
||||
((CHANNEL) == DMA_CHANNEL_1) || \
|
||||
((CHANNEL) == DMA_CHANNEL_2) || \
|
||||
((CHANNEL) == DMA_CHANNEL_3) || \
|
||||
((CHANNEL) == DMA_CHANNEL_4) || \
|
||||
((CHANNEL) == DMA_CHANNEL_5) || \
|
||||
((CHANNEL) == DMA_CHANNEL_6) || \
|
||||
((CHANNEL) == DMA_CHANNEL_7) || \
|
||||
((CHANNEL) == DMA_CHANNEL_8) || \
|
||||
((CHANNEL) == DMA_CHANNEL_9) || \
|
||||
((CHANNEL) == DMA_CHANNEL_10) || \
|
||||
((CHANNEL) == DMA_CHANNEL_11) || \
|
||||
((CHANNEL) == DMA_CHANNEL_12) || \
|
||||
((CHANNEL) == DMA_CHANNEL_13) || \
|
||||
((CHANNEL) == DMA_CHANNEL_14) || \
|
||||
((CHANNEL) == DMA_CHANNEL_15))
|
||||
#else
|
||||
#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
|
||||
((CHANNEL) == DMA_CHANNEL_1) || \
|
||||
((CHANNEL) == DMA_CHANNEL_2) || \
|
||||
((CHANNEL) == DMA_CHANNEL_3) || \
|
||||
((CHANNEL) == DMA_CHANNEL_4) || \
|
||||
((CHANNEL) == DMA_CHANNEL_5) || \
|
||||
((CHANNEL) == DMA_CHANNEL_6) || \
|
||||
((CHANNEL) == DMA_CHANNEL_7))
|
||||
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||
|
||||
STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup DMAEx_Private_Functions DMAEx Private Functions
|
||||
* @brief DMAEx Private functions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_DMA_H */
|
||||
|
||||
@ -0,0 +1,317 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_exti.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of EXTI HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2018 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F7xx_HAL_EXTI_H
|
||||
#define STM32F7xx_HAL_EXTI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI EXTI
|
||||
* @brief EXTI HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Types EXTI Exported Types
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_EXTI_COMMON_CB_ID = 0x00U
|
||||
} EXTI_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief EXTI Handle structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Line; /*!< Exti line number */
|
||||
void (* PendingCallback)(void); /*!< Exti pending callback */
|
||||
} EXTI_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @brief EXTI Configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Line; /*!< The Exti line to be configured. This parameter
|
||||
can be a value of @ref EXTI_Line */
|
||||
uint32_t Mode; /*!< The Exit Mode to be configured for a core.
|
||||
This parameter can be a combination of @ref EXTI_Mode */
|
||||
uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
|
||||
can be a value of @ref EXTI_Trigger */
|
||||
uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
|
||||
This parameter is only possible for line 0 to 15. It
|
||||
can be a value of @ref EXTI_GPIOSel */
|
||||
} EXTI_ConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Line EXTI Line
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */
|
||||
#define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */
|
||||
#define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */
|
||||
#define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */
|
||||
#define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */
|
||||
#define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */
|
||||
#define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */
|
||||
#define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */
|
||||
#define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */
|
||||
#define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */
|
||||
#define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */
|
||||
#define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */
|
||||
#define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */
|
||||
#define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */
|
||||
#define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */
|
||||
#define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */
|
||||
#define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */
|
||||
#define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */
|
||||
#define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */
|
||||
#if defined(ETH)
|
||||
#define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
|
||||
#else
|
||||
#define EXTI_LINE_19 (EXTI_RESERVED | 0x13u) /*!< No interrupt supported in this line */
|
||||
#endif /* ETH */
|
||||
#define EXTI_LINE_20 (EXTI_CONFIG | 0x14u) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */
|
||||
#define EXTI_LINE_21 (EXTI_CONFIG | 0x15u) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
|
||||
#define EXTI_LINE_22 (EXTI_CONFIG | 0x16u) /*!< External interrupt line 22 Connected to the RTC Wakeup event */
|
||||
#define EXTI_LINE_23 (EXTI_CONFIG | 0x17u) /*!< External interrupt line 23 Connected to the LPTIM Wakeup event */
|
||||
#if defined(EXTI_IMR_IM24)
|
||||
#define EXTI_LINE_24 (EXTI_CONFIG | 0x18u) /*!< External interrupt line 24 Connected to the MDIO Slave global Interrupt Wakeup event */
|
||||
#endif /* EXTI_IMR_IM24 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Mode EXTI Mode
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_MODE_NONE 0x00000000u
|
||||
#define EXTI_MODE_INTERRUPT 0x00000001u
|
||||
#define EXTI_MODE_EVENT 0x00000002u
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Trigger EXTI Trigger
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define EXTI_TRIGGER_NONE 0x00000000u
|
||||
#define EXTI_TRIGGER_RISING 0x00000001u
|
||||
#define EXTI_TRIGGER_FALLING 0x00000002u
|
||||
#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_GPIOSel EXTI GPIOSel
|
||||
* @brief
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_GPIOA 0x00000000u
|
||||
#define EXTI_GPIOB 0x00000001u
|
||||
#define EXTI_GPIOC 0x00000002u
|
||||
#define EXTI_GPIOD 0x00000003u
|
||||
#define EXTI_GPIOE 0x00000004u
|
||||
#define EXTI_GPIOF 0x00000005u
|
||||
#define EXTI_GPIOG 0x00000006u
|
||||
#define EXTI_GPIOH 0x00000007u
|
||||
#define EXTI_GPIOI 0x00000008u
|
||||
#define EXTI_GPIOJ 0x00000009u
|
||||
#if defined (GPIOK)
|
||||
#define EXTI_GPIOK 0x0000000Au
|
||||
#endif /* GPIOK */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants --------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Private_Constants EXTI Private Constants
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief EXTI Line property definition
|
||||
*/
|
||||
#define EXTI_PROPERTY_SHIFT 24u
|
||||
#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
|
||||
#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
|
||||
#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)
|
||||
#define EXTI_PROPERTY_MASK (EXTI_CONFIG | EXTI_GPIO)
|
||||
|
||||
/**
|
||||
* @brief EXTI bit usage
|
||||
*/
|
||||
#define EXTI_PIN_MASK 0x0000001Fu
|
||||
|
||||
/**
|
||||
* @brief EXTI Mask for interrupt & event mode
|
||||
*/
|
||||
#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
|
||||
|
||||
/**
|
||||
* @brief EXTI Mask for trigger possibilities
|
||||
*/
|
||||
#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
|
||||
|
||||
/**
|
||||
* @brief EXTI Line number
|
||||
*/
|
||||
#if defined(EXTI_IMR_IM24)
|
||||
#define EXTI_LINE_NB 25u
|
||||
#else
|
||||
#define EXTI_LINE_NB 24u
|
||||
#endif /* EXTI_IMR_IM24 */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Private_Macros EXTI Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \
|
||||
((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
|
||||
(((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
|
||||
(((__EXTI_LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB))
|
||||
|
||||
#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \
|
||||
(((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u))
|
||||
|
||||
#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
|
||||
|
||||
#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) (((__EXTI_LINE__) == EXTI_TRIGGER_FALLING) || \
|
||||
((__EXTI_LINE__) == EXTI_TRIGGER_RISING) || \
|
||||
((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING))
|
||||
|
||||
#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u)
|
||||
|
||||
#if defined (GPIOK)
|
||||
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
|
||||
((__PORT__) == EXTI_GPIOB) || \
|
||||
((__PORT__) == EXTI_GPIOC) || \
|
||||
((__PORT__) == EXTI_GPIOD) || \
|
||||
((__PORT__) == EXTI_GPIOE) || \
|
||||
((__PORT__) == EXTI_GPIOF) || \
|
||||
((__PORT__) == EXTI_GPIOG) || \
|
||||
((__PORT__) == EXTI_GPIOH) || \
|
||||
((__PORT__) == EXTI_GPIOI) || \
|
||||
((__PORT__) == EXTI_GPIOJ) || \
|
||||
((__PORT__) == EXTI_GPIOK))
|
||||
#else
|
||||
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
|
||||
((__PORT__) == EXTI_GPIOB) || \
|
||||
((__PORT__) == EXTI_GPIOC) || \
|
||||
((__PORT__) == EXTI_GPIOD) || \
|
||||
((__PORT__) == EXTI_GPIOE) || \
|
||||
((__PORT__) == EXTI_GPIOF) || \
|
||||
((__PORT__) == EXTI_GPIOG) || \
|
||||
((__PORT__) == EXTI_GPIOH) || \
|
||||
((__PORT__) == EXTI_GPIOI) || \
|
||||
((__PORT__) == EXTI_GPIOJ))
|
||||
#endif /* GPIOK */
|
||||
|
||||
#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
|
||||
* @brief EXTI Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
|
||||
* @brief Configuration functions
|
||||
* @{
|
||||
*/
|
||||
/* Configuration functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
|
||||
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
|
||||
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
|
||||
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
|
||||
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
|
||||
* @brief IO operation functions
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
|
||||
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
|
||||
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
|
||||
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F7xx_HAL_EXTI_H */
|
||||
|
||||
@ -0,0 +1,415 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_flash.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of FLASH HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file in
|
||||
* the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_FLASH_H
|
||||
#define __STM32F7xx_HAL_FLASH_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Types FLASH Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FLASH Procedure structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
FLASH_PROC_NONE = 0U,
|
||||
FLASH_PROC_SECTERASE,
|
||||
FLASH_PROC_MASSERASE,
|
||||
FLASH_PROC_PROGRAM
|
||||
} FLASH_ProcedureTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief FLASH handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO FLASH_ProcedureTypeDef ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */
|
||||
|
||||
__IO uint32_t NbSectorsToErase; /* Internal variable to save the remaining sectors to erase in IT context */
|
||||
|
||||
__IO uint8_t VoltageForErase; /* Internal variable to provide voltage range selected by user in IT context */
|
||||
|
||||
__IO uint32_t Sector; /* Internal variable to define the current sector which is erasing */
|
||||
|
||||
__IO uint32_t Address; /* Internal variable to save address selected for program */
|
||||
|
||||
HAL_LockTypeDef Lock; /* FLASH locking object */
|
||||
|
||||
__IO uint32_t ErrorCode; /* FLASH error code */
|
||||
|
||||
}FLASH_ProcessTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Error_Code FLASH Error Code
|
||||
* @brief FLASH Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
|
||||
#define HAL_FLASH_ERROR_ERS ((uint32_t)0x00000002U) /*!< Programming Sequence error */
|
||||
#define HAL_FLASH_ERROR_PGP ((uint32_t)0x00000004U) /*!< Programming Parallelism error */
|
||||
#define HAL_FLASH_ERROR_PGA ((uint32_t)0x00000008U) /*!< Programming Alignment error */
|
||||
#define HAL_FLASH_ERROR_WRP ((uint32_t)0x00000010U) /*!< Write protection error */
|
||||
#define HAL_FLASH_ERROR_OPERATION ((uint32_t)0x00000020U) /*!< Operation Error */
|
||||
#define HAL_FLASH_ERROR_RD ((uint32_t)0x00000040U) /*!< Read Protection Error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Type_Program FLASH Type Program
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_TYPEPROGRAM_BYTE ((uint32_t)0x00U) /*!< Program byte (8-bit) at a specified address */
|
||||
#define FLASH_TYPEPROGRAM_HALFWORD ((uint32_t)0x01U) /*!< Program a half-word (16-bit) at a specified address */
|
||||
#define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02U) /*!< Program a word (32-bit) at a specified address */
|
||||
#define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03U) /*!< Program a double word (64-bit) at a specified address */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Flag_definition FLASH Flag definition
|
||||
* @brief Flag definition
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */
|
||||
#define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< FLASH operation Error flag */
|
||||
#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */
|
||||
#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */
|
||||
#define FLASH_FLAG_PGPERR FLASH_SR_PGPERR /*!< FLASH Programming Parallelism error flag */
|
||||
#define FLASH_FLAG_ERSERR FLASH_SR_ERSERR /*!< FLASH Erasing Sequence error flag */
|
||||
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
|
||||
|
||||
#if defined (FLASH_OPTCR2_PCROP)
|
||||
#define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< FLASH Read protection error flag */
|
||||
#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
|
||||
FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR | FLASH_FLAG_RDERR)
|
||||
#else
|
||||
#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
|
||||
FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR)
|
||||
#endif /* FLASH_OPTCR2_PCROP */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition
|
||||
* @brief FLASH Interrupt definition
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */
|
||||
#define FLASH_IT_ERR ((uint32_t)0x02000000U) /*!< Error Interrupt source */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000U)
|
||||
#define FLASH_PSIZE_HALF_WORD ((uint32_t)FLASH_CR_PSIZE_0)
|
||||
#define FLASH_PSIZE_WORD ((uint32_t)FLASH_CR_PSIZE_1)
|
||||
#define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)FLASH_CR_PSIZE)
|
||||
#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFFU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Keys FLASH Keys
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_KEY1 ((uint32_t)0x45670123U)
|
||||
#define FLASH_KEY2 ((uint32_t)0xCDEF89ABU)
|
||||
#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3BU)
|
||||
#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7FU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Sectors FLASH Sectors
|
||||
* @{
|
||||
*/
|
||||
#if (FLASH_SECTOR_TOTAL == 2)
|
||||
#define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */
|
||||
#define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */
|
||||
#elif (FLASH_SECTOR_TOTAL == 4)
|
||||
#define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */
|
||||
#define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */
|
||||
#define FLASH_SECTOR_2 ((uint32_t)2U) /*!< Sector Number 2 */
|
||||
#define FLASH_SECTOR_3 ((uint32_t)3U) /*!< Sector Number 3 */
|
||||
#else
|
||||
#define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */
|
||||
#define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */
|
||||
#define FLASH_SECTOR_2 ((uint32_t)2U) /*!< Sector Number 2 */
|
||||
#define FLASH_SECTOR_3 ((uint32_t)3U) /*!< Sector Number 3 */
|
||||
#define FLASH_SECTOR_4 ((uint32_t)4U) /*!< Sector Number 4 */
|
||||
#define FLASH_SECTOR_5 ((uint32_t)5U) /*!< Sector Number 5 */
|
||||
#define FLASH_SECTOR_6 ((uint32_t)6U) /*!< Sector Number 6 */
|
||||
#define FLASH_SECTOR_7 ((uint32_t)7U) /*!< Sector Number 7 */
|
||||
#endif /* FLASH_SECTOR_TOTAL */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Set the FLASH Latency.
|
||||
* @param __LATENCY__ FLASH Latency
|
||||
* The value of this parameter depend on device used within the same series
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_SET_LATENCY(__LATENCY__) \
|
||||
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__))
|
||||
|
||||
/**
|
||||
* @brief Get the FLASH Latency.
|
||||
* @retval FLASH Latency
|
||||
* The value of this parameter depend on device used within the same series
|
||||
*/
|
||||
#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
|
||||
|
||||
/**
|
||||
* @brief Enable the FLASH prefetch buffer.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTEN)
|
||||
|
||||
/**
|
||||
* @brief Disable the FLASH prefetch buffer.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTEN))
|
||||
|
||||
/**
|
||||
* @brief Enable the FLASH Adaptive Real-Time memory accelerator.
|
||||
* @note The ART accelerator is available only for flash access on ITCM interface.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_ART_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ARTEN)
|
||||
|
||||
/**
|
||||
* @brief Disable the FLASH Adaptive Real-Time memory accelerator.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_ART_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ARTEN)
|
||||
|
||||
/**
|
||||
* @brief Resets the FLASH Adaptive Real-Time memory accelerator.
|
||||
* @note This function must be used only when the Adaptive Real-Time memory accelerator
|
||||
* is disabled.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_ART_RESET() (FLASH->ACR |= FLASH_ACR_ARTRST)
|
||||
|
||||
/**
|
||||
* @brief Enable the specified FLASH interrupt.
|
||||
* @param __INTERRUPT__ FLASH interrupt
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
|
||||
* @arg FLASH_IT_ERR: Error Interrupt
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the specified FLASH interrupt.
|
||||
* @param __INTERRUPT__ FLASH interrupt
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
|
||||
* @arg FLASH_IT_ERR: Error Interrupt
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(uint32_t)(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Get the specified FLASH flag status.
|
||||
* @param __FLAG__ specifies the FLASH flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FLASH_FLAG_EOP : FLASH End of Operation flag
|
||||
* @arg FLASH_FLAG_OPERR : FLASH operation Error flag
|
||||
* @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
|
||||
* @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
|
||||
* @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
|
||||
* @arg FLASH_FLAG_ERSERR : FLASH Erasing Sequence error flag
|
||||
* @arg FLASH_FLAG_BSY : FLASH Busy flag
|
||||
* @retval The new state of __FLAG__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__)))
|
||||
|
||||
/**
|
||||
* @brief Clear the specified FLASH flag.
|
||||
* @param __FLAG__ specifies the FLASH flags to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg FLASH_FLAG_EOP : FLASH End of Operation flag
|
||||
* @arg FLASH_FLAG_OPERR : FLASH operation Error flag
|
||||
* @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
|
||||
* @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
|
||||
* @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
|
||||
* @arg FLASH_FLAG_ERSERR : FLASH Erasing Sequence error flag
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include FLASH HAL Extension module */
|
||||
#include "stm32f7xx_hal_flash_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup FLASH_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
/** @addtogroup FLASH_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Program operation functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
|
||||
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
|
||||
/* FLASH IRQ handler method */
|
||||
void HAL_FLASH_IRQHandler(void);
|
||||
/* Callbacks in non blocking modes */
|
||||
void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
|
||||
void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions **********************************************/
|
||||
HAL_StatusTypeDef HAL_FLASH_Unlock(void);
|
||||
HAL_StatusTypeDef HAL_FLASH_Lock(void);
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
|
||||
/* Option bytes control */
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions ************************************************/
|
||||
uint32_t HAL_FLASH_GetError(void);
|
||||
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Variables FLASH Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Constants FLASH Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief OPTCR register byte 1 (Bits[15:8]) base address
|
||||
*/
|
||||
#define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Macros FLASH Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_IS_FLASH_Definitions FLASH Private macros to check input parameters
|
||||
* @{
|
||||
*/
|
||||
#define IS_FLASH_TYPEPROGRAM(VALUE)(((VALUE) == FLASH_TYPEPROGRAM_BYTE) || \
|
||||
((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \
|
||||
((VALUE) == FLASH_TYPEPROGRAM_WORD) || \
|
||||
((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Functions FLASH Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_FLASH_H */
|
||||
|
||||
@ -0,0 +1,697 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_flash_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of FLASH HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file in
|
||||
* the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_FLASH_EX_H
|
||||
#define __STM32F7xx_HAL_FLASH_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASHEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Exported_Types FLASH Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FLASH Erase structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t TypeErase; /*!< Mass erase or sector Erase.
|
||||
This parameter can be a value of @ref FLASHEx_Type_Erase */
|
||||
|
||||
#if defined (FLASH_OPTCR_nDBANK)
|
||||
uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled.
|
||||
This parameter must be a value of @ref FLASHEx_Banks */
|
||||
#endif /* FLASH_OPTCR_nDBANK */
|
||||
|
||||
uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled
|
||||
This parameter must be a value of @ref FLASHEx_Sectors */
|
||||
|
||||
uint32_t NbSectors; /*!< Number of sectors to be erased.
|
||||
This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
|
||||
|
||||
uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism
|
||||
This parameter must be a value of @ref FLASHEx_Voltage_Range */
|
||||
|
||||
} FLASH_EraseInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FLASH Option Bytes Program structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t OptionType; /*!< Option byte to be configured.
|
||||
This parameter can be a value of @ref FLASHEx_Option_Type */
|
||||
|
||||
uint32_t WRPState; /*!< Write protection activation or deactivation.
|
||||
This parameter can be a value of @ref FLASHEx_WRP_State */
|
||||
|
||||
uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected.
|
||||
The value of this parameter depend on device used within the same series */
|
||||
|
||||
uint32_t RDPLevel; /*!< Set the read protection level.
|
||||
This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
|
||||
|
||||
uint32_t BORLevel; /*!< Set the BOR Level.
|
||||
This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */
|
||||
|
||||
uint32_t USERConfig; /*!< Program the FLASH User Option Byte: WWDG_SW / IWDG_SW / RST_STOP / RST_STDBY /
|
||||
IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / nDBANK / nDBOOT.
|
||||
nDBANK / nDBOOT are only available for STM32F76xxx/STM32F77xxx devices */
|
||||
|
||||
uint32_t BootAddr0; /*!< Boot base address when Boot pin = 0.
|
||||
This parameter can be a value of @ref FLASHEx_Boot_Address */
|
||||
|
||||
uint32_t BootAddr1; /*!< Boot base address when Boot pin = 1.
|
||||
This parameter can be a value of @ref FLASHEx_Boot_Address */
|
||||
|
||||
#if defined (FLASH_OPTCR2_PCROP)
|
||||
uint32_t PCROPSector; /*!< Set the PCROP sector.
|
||||
This parameter can be a value of @ref FLASHEx_Option_Bytes_PCROP_Sectors */
|
||||
|
||||
uint32_t PCROPRdp; /*!< Set the PCROP_RDP option.
|
||||
This parameter can be a value of @ref FLASHEx_Option_Bytes_PCROP_RDP */
|
||||
#endif /* FLASH_OPTCR2_PCROP */
|
||||
|
||||
} FLASH_OBProgramInitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Type_Erase FLASH Type Erase
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_TYPEERASE_SECTORS ((uint32_t)0x00U) /*!< Sectors erase only */
|
||||
#define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01U) /*!< Flash Mass erase activation */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_VOLTAGE_RANGE_1 ((uint32_t)0x00U) /*!< Device operating range: 1.8V to 2.1V */
|
||||
#define FLASH_VOLTAGE_RANGE_2 ((uint32_t)0x01U) /*!< Device operating range: 2.1V to 2.7V */
|
||||
#define FLASH_VOLTAGE_RANGE_3 ((uint32_t)0x02U) /*!< Device operating range: 2.7V to 3.6V */
|
||||
#define FLASH_VOLTAGE_RANGE_4 ((uint32_t)0x03U) /*!< Device operating range: 2.7V to 3.6V + External Vpp */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_WRP_State FLASH WRP State
|
||||
* @{
|
||||
*/
|
||||
#define OB_WRPSTATE_DISABLE ((uint32_t)0x00U) /*!< Disable the write protection of the desired bank 1 sectors */
|
||||
#define OB_WRPSTATE_ENABLE ((uint32_t)0x01U) /*!< Enable the write protection of the desired bank 1 sectors */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Option_Type FLASH Option Type
|
||||
* @{
|
||||
*/
|
||||
#define OPTIONBYTE_WRP ((uint32_t)0x01U) /*!< WRP option byte configuration */
|
||||
#define OPTIONBYTE_RDP ((uint32_t)0x02U) /*!< RDP option byte configuration */
|
||||
#define OPTIONBYTE_USER ((uint32_t)0x04U) /*!< USER option byte configuration */
|
||||
#define OPTIONBYTE_BOR ((uint32_t)0x08U) /*!< BOR option byte configuration */
|
||||
#define OPTIONBYTE_BOOTADDR_0 ((uint32_t)0x10U) /*!< Boot 0 Address configuration */
|
||||
#define OPTIONBYTE_BOOTADDR_1 ((uint32_t)0x20U) /*!< Boot 1 Address configuration */
|
||||
#if defined (FLASH_OPTCR2_PCROP)
|
||||
#define OPTIONBYTE_PCROP ((uint32_t)0x40U) /*!< PCROP configuration */
|
||||
#define OPTIONBYTE_PCROP_RDP ((uint32_t)0x80U) /*!< PCROP_RDP configuration */
|
||||
#endif /* FLASH_OPTCR2_PCROP */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection
|
||||
* @{
|
||||
*/
|
||||
#define OB_RDP_LEVEL_0 ((uint8_t)0xAAU)
|
||||
#define OB_RDP_LEVEL_1 ((uint8_t)0x55U)
|
||||
#define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) /*!< Warning: When enabling read protection level 2
|
||||
it s no more possible to go back to level 1 or 0 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Option_Bytes_WWatchdog FLASH Option Bytes WWatchdog
|
||||
* @{
|
||||
*/
|
||||
#define OB_WWDG_SW ((uint32_t)0x10U) /*!< Software WWDG selected */
|
||||
#define OB_WWDG_HW ((uint32_t)0x00U) /*!< Hardware WWDG selected */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog
|
||||
* @{
|
||||
*/
|
||||
#define OB_IWDG_SW ((uint32_t)0x20U) /*!< Software IWDG selected */
|
||||
#define OB_IWDG_HW ((uint32_t)0x00U) /*!< Hardware IWDG selected */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP
|
||||
* @{
|
||||
*/
|
||||
#define OB_STOP_NO_RST ((uint32_t)0x40U) /*!< No reset generated when entering in STOP */
|
||||
#define OB_STOP_RST ((uint32_t)0x00U) /*!< Reset generated when entering in STOP */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY
|
||||
* @{
|
||||
*/
|
||||
#define OB_STDBY_NO_RST ((uint32_t)0x80U) /*!< No reset generated when entering in STANDBY */
|
||||
#define OB_STDBY_RST ((uint32_t)0x00U) /*!< Reset generated when entering in STANDBY */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP
|
||||
* @{
|
||||
*/
|
||||
#define OB_IWDG_STOP_FREEZE ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STOP mode */
|
||||
#define OB_IWDG_STOP_ACTIVE ((uint32_t)0x80000000U) /*!< IWDG counter active in STOP mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY
|
||||
* @{
|
||||
*/
|
||||
#define OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STANDBY mode */
|
||||
#define OB_IWDG_STDBY_ACTIVE ((uint32_t)0x40000000U) /*!< IWDG counter active in STANDBY mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level
|
||||
* @{
|
||||
*/
|
||||
#define OB_BOR_LEVEL3 ((uint32_t)0x00U) /*!< Supply voltage ranges from 2.70 to 3.60 V */
|
||||
#define OB_BOR_LEVEL2 ((uint32_t)0x04U) /*!< Supply voltage ranges from 2.40 to 2.70 V */
|
||||
#define OB_BOR_LEVEL1 ((uint32_t)0x08U) /*!< Supply voltage ranges from 2.10 to 2.40 V */
|
||||
#define OB_BOR_OFF ((uint32_t)0x0CU) /*!< Supply voltage ranges from 1.62 to 2.10 V */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined (FLASH_OPTCR_nDBOOT)
|
||||
/** @defgroup FLASHEx_Option_Bytes_nDBOOT FLASH Option Bytes nDBOOT
|
||||
* @{
|
||||
*/
|
||||
#define OB_DUAL_BOOT_DISABLE ((uint32_t)0x10000000U) /* !< Dual Boot disable. Boot according to boot address option */
|
||||
#define OB_DUAL_BOOT_ENABLE ((uint32_t)0x00000000U) /* !< Dual Boot enable. Boot always from system memory if boot address in flash
|
||||
(Dual bank Boot mode), or RAM if Boot address option in RAM */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* FLASH_OPTCR_nDBOOT */
|
||||
|
||||
#if defined (FLASH_OPTCR_nDBANK)
|
||||
/** @defgroup FLASHEx_Option_Bytes_nDBank FLASH Single Bank or Dual Bank
|
||||
* @{
|
||||
*/
|
||||
#define OB_NDBANK_SINGLE_BANK ((uint32_t)0x20000000U) /*!< NDBANK bit is set : Single Bank mode */
|
||||
#define OB_NDBANK_DUAL_BANK ((uint32_t)0x00000000U) /*!< NDBANK bit is reset : Dual Bank mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* FLASH_OPTCR_nDBANK */
|
||||
|
||||
/** @defgroup FLASHEx_Boot_Address FLASH Boot Address
|
||||
* @{
|
||||
*/
|
||||
#define OB_BOOTADDR_ITCM_RAM ((uint32_t)0x0000U) /*!< Boot from ITCM RAM (0x00000000) */
|
||||
#define OB_BOOTADDR_SYSTEM ((uint32_t)0x0040U) /*!< Boot from System memory bootloader (0x00100000) */
|
||||
#define OB_BOOTADDR_ITCM_FLASH ((uint32_t)0x0080U) /*!< Boot from Flash on ITCM interface (0x00200000) */
|
||||
#define OB_BOOTADDR_AXIM_FLASH ((uint32_t)0x2000U) /*!< Boot from Flash on AXIM interface (0x08000000) */
|
||||
#define OB_BOOTADDR_DTCM_RAM ((uint32_t)0x8000U) /*!< Boot from DTCM RAM (0x20000000) */
|
||||
#define OB_BOOTADDR_SRAM1 ((uint32_t)0x8004U) /*!< Boot from SRAM1 (0x20010000) */
|
||||
#if (SRAM2_BASE == 0x2003C000U)
|
||||
#define OB_BOOTADDR_SRAM2 ((uint32_t)0x800FU) /*!< Boot from SRAM2 (0x2003C000) */
|
||||
#else
|
||||
#define OB_BOOTADDR_SRAM2 ((uint32_t)0x8013U) /*!< Boot from SRAM2 (0x2004C000) */
|
||||
#endif /* SRAM2_BASE == 0x2003C000U */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Latency FLASH Latency
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */
|
||||
#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */
|
||||
#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two Latency cycles */
|
||||
#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycles */
|
||||
#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four Latency cycles */
|
||||
#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */
|
||||
#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */
|
||||
#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */
|
||||
#define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight Latency cycles */
|
||||
#define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine Latency cycles */
|
||||
#define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten Latency cycles */
|
||||
#define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven Latency cycles */
|
||||
#define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve Latency cycles */
|
||||
#define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen Latency cycles */
|
||||
#define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen Latency cycles */
|
||||
#define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen Latency cycles */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined (FLASH_OPTCR_nDBANK)
|
||||
/** @defgroup FLASHEx_Banks FLASH Banks
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_BANK_1 ((uint32_t)0x01U) /*!< Bank 1 */
|
||||
#define FLASH_BANK_2 ((uint32_t)0x02U) /*!< Bank 2 */
|
||||
#define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2)) /*!< Bank1 and Bank2 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* FLASH_OPTCR_nDBANK */
|
||||
|
||||
/** @defgroup FLASHEx_MassErase_bit FLASH Mass Erase bit
|
||||
* @{
|
||||
*/
|
||||
#if defined (FLASH_OPTCR_nDBANK)
|
||||
#define FLASH_MER_BIT (FLASH_CR_MER1 | FLASH_CR_MER2) /*!< 2 MER bits */
|
||||
#else
|
||||
#define FLASH_MER_BIT (FLASH_CR_MER) /*!< only 1 MER bit */
|
||||
#endif /* FLASH_OPTCR_nDBANK */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_Sectors FLASH Sectors
|
||||
* @{
|
||||
*/
|
||||
#if (FLASH_SECTOR_TOTAL == 24)
|
||||
#define FLASH_SECTOR_8 ((uint32_t)8U) /*!< Sector Number 8 */
|
||||
#define FLASH_SECTOR_9 ((uint32_t)9U) /*!< Sector Number 9 */
|
||||
#define FLASH_SECTOR_10 ((uint32_t)10U) /*!< Sector Number 10 */
|
||||
#define FLASH_SECTOR_11 ((uint32_t)11U) /*!< Sector Number 11 */
|
||||
#define FLASH_SECTOR_12 ((uint32_t)12U) /*!< Sector Number 12 */
|
||||
#define FLASH_SECTOR_13 ((uint32_t)13U) /*!< Sector Number 13 */
|
||||
#define FLASH_SECTOR_14 ((uint32_t)14U) /*!< Sector Number 14 */
|
||||
#define FLASH_SECTOR_15 ((uint32_t)15U) /*!< Sector Number 15 */
|
||||
#define FLASH_SECTOR_16 ((uint32_t)16U) /*!< Sector Number 16 */
|
||||
#define FLASH_SECTOR_17 ((uint32_t)17U) /*!< Sector Number 17 */
|
||||
#define FLASH_SECTOR_18 ((uint32_t)18U) /*!< Sector Number 18 */
|
||||
#define FLASH_SECTOR_19 ((uint32_t)19U) /*!< Sector Number 19 */
|
||||
#define FLASH_SECTOR_20 ((uint32_t)20U) /*!< Sector Number 20 */
|
||||
#define FLASH_SECTOR_21 ((uint32_t)21U) /*!< Sector Number 21 */
|
||||
#define FLASH_SECTOR_22 ((uint32_t)22U) /*!< Sector Number 22 */
|
||||
#define FLASH_SECTOR_23 ((uint32_t)23U) /*!< Sector Number 23 */
|
||||
#endif /* FLASH_SECTOR_TOTAL == 24 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if (FLASH_SECTOR_TOTAL == 24)
|
||||
/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
|
||||
* @note For Single Bank mode, use OB_WRP_SECTOR_x defines: In fact, in FLASH_OPTCR register,
|
||||
* nWRP[11:0] bits contain the value of the write-protection option bytes for sectors 0 to 11.
|
||||
* For Dual Bank mode, use OB_WRP_DB_SECTOR_x defines: In fact, in FLASH_OPTCR register,
|
||||
* nWRP[11:0] bits are divided on two groups, one group dedicated for bank 1 and
|
||||
* a second one dedicated for bank 2 (nWRP[i] activates Write protection on sector 2*i and 2*i+1).
|
||||
* This behavior is applicable only for STM32F76xxx / STM32F77xxx devices.
|
||||
* @{
|
||||
*/
|
||||
/* Single Bank Sectors */
|
||||
#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Single Bank Sector0 */
|
||||
#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Single Bank Sector1 */
|
||||
#define OB_WRP_SECTOR_2 ((uint32_t)0x00040000U) /*!< Write protection of Single Bank Sector2 */
|
||||
#define OB_WRP_SECTOR_3 ((uint32_t)0x00080000U) /*!< Write protection of Single Bank Sector3 */
|
||||
#define OB_WRP_SECTOR_4 ((uint32_t)0x00100000U) /*!< Write protection of Single Bank Sector4 */
|
||||
#define OB_WRP_SECTOR_5 ((uint32_t)0x00200000U) /*!< Write protection of Single Bank Sector5 */
|
||||
#define OB_WRP_SECTOR_6 ((uint32_t)0x00400000U) /*!< Write protection of Single Bank Sector6 */
|
||||
#define OB_WRP_SECTOR_7 ((uint32_t)0x00800000U) /*!< Write protection of Single Bank Sector7 */
|
||||
#define OB_WRP_SECTOR_8 ((uint32_t)0x01000000U) /*!< Write protection of Single Bank Sector8 */
|
||||
#define OB_WRP_SECTOR_9 ((uint32_t)0x02000000U) /*!< Write protection of Single Bank Sector9 */
|
||||
#define OB_WRP_SECTOR_10 ((uint32_t)0x04000000U) /*!< Write protection of Single Bank Sector10 */
|
||||
#define OB_WRP_SECTOR_11 ((uint32_t)0x08000000U) /*!< Write protection of Single Bank Sector11 */
|
||||
#define OB_WRP_SECTOR_All ((uint32_t)0x0FFF0000U) /*!< Write protection of all Sectors for Single Bank Flash */
|
||||
|
||||
/* Dual Bank Sectors */
|
||||
#define OB_WRP_DB_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Dual Bank Sector0 */
|
||||
#define OB_WRP_DB_SECTOR_1 ((uint32_t)0x00010000U) /*!< Write protection of Dual Bank Sector1 */
|
||||
#define OB_WRP_DB_SECTOR_2 ((uint32_t)0x00020000U) /*!< Write protection of Dual Bank Sector2 */
|
||||
#define OB_WRP_DB_SECTOR_3 ((uint32_t)0x00020000U) /*!< Write protection of Dual Bank Sector3 */
|
||||
#define OB_WRP_DB_SECTOR_4 ((uint32_t)0x00040000U) /*!< Write protection of Dual Bank Sector4 */
|
||||
#define OB_WRP_DB_SECTOR_5 ((uint32_t)0x00040000U) /*!< Write protection of Dual Bank Sector5 */
|
||||
#define OB_WRP_DB_SECTOR_6 ((uint32_t)0x00080000U) /*!< Write protection of Dual Bank Sector6 */
|
||||
#define OB_WRP_DB_SECTOR_7 ((uint32_t)0x00080000U) /*!< Write protection of Dual Bank Sector7 */
|
||||
#define OB_WRP_DB_SECTOR_8 ((uint32_t)0x00100000U) /*!< Write protection of Dual Bank Sector8 */
|
||||
#define OB_WRP_DB_SECTOR_9 ((uint32_t)0x00100000U) /*!< Write protection of Dual Bank Sector9 */
|
||||
#define OB_WRP_DB_SECTOR_10 ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector10 */
|
||||
#define OB_WRP_DB_SECTOR_11 ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector11 */
|
||||
#define OB_WRP_DB_SECTOR_12 ((uint32_t)0x00400000U) /*!< Write protection of Dual Bank Sector12 */
|
||||
#define OB_WRP_DB_SECTOR_13 ((uint32_t)0x00400000U) /*!< Write protection of Dual Bank Sector13 */
|
||||
#define OB_WRP_DB_SECTOR_14 ((uint32_t)0x00800000U) /*!< Write protection of Dual Bank Sector14 */
|
||||
#define OB_WRP_DB_SECTOR_15 ((uint32_t)0x00800000U) /*!< Write protection of Dual Bank Sector15 */
|
||||
#define OB_WRP_DB_SECTOR_16 ((uint32_t)0x01000000U) /*!< Write protection of Dual Bank Sector16 */
|
||||
#define OB_WRP_DB_SECTOR_17 ((uint32_t)0x01000000U) /*!< Write protection of Dual Bank Sector17 */
|
||||
#define OB_WRP_DB_SECTOR_18 ((uint32_t)0x02000000U) /*!< Write protection of Dual Bank Sector18 */
|
||||
#define OB_WRP_DB_SECTOR_19 ((uint32_t)0x02000000U) /*!< Write protection of Dual Bank Sector19 */
|
||||
#define OB_WRP_DB_SECTOR_20 ((uint32_t)0x04000000U) /*!< Write protection of Dual Bank Sector20 */
|
||||
#define OB_WRP_DB_SECTOR_21 ((uint32_t)0x04000000U) /*!< Write protection of Dual Bank Sector21 */
|
||||
#define OB_WRP_DB_SECTOR_22 ((uint32_t)0x08000000U) /*!< Write protection of Dual Bank Sector22 */
|
||||
#define OB_WRP_DB_SECTOR_23 ((uint32_t)0x08000000U) /*!< Write protection of Dual Bank Sector23 */
|
||||
#define OB_WRP_DB_SECTOR_All ((uint32_t)0x0FFF0000U) /*!< Write protection of all Sectors for Dual Bank Flash */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* FLASH_SECTOR_TOTAL == 24 */
|
||||
|
||||
#if (FLASH_SECTOR_TOTAL == 8)
|
||||
/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
|
||||
* @{
|
||||
*/
|
||||
#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Sector0 */
|
||||
#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Sector1 */
|
||||
#define OB_WRP_SECTOR_2 ((uint32_t)0x00040000U) /*!< Write protection of Sector2 */
|
||||
#define OB_WRP_SECTOR_3 ((uint32_t)0x00080000U) /*!< Write protection of Sector3 */
|
||||
#define OB_WRP_SECTOR_4 ((uint32_t)0x00100000U) /*!< Write protection of Sector4 */
|
||||
#define OB_WRP_SECTOR_5 ((uint32_t)0x00200000U) /*!< Write protection of Sector5 */
|
||||
#define OB_WRP_SECTOR_6 ((uint32_t)0x00400000U) /*!< Write protection of Sector6 */
|
||||
#define OB_WRP_SECTOR_7 ((uint32_t)0x00800000U) /*!< Write protection of Sector7 */
|
||||
#define OB_WRP_SECTOR_All ((uint32_t)0x00FF0000U) /*!< Write protection of all Sectors */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* FLASH_SECTOR_TOTAL == 8 */
|
||||
|
||||
#if (FLASH_SECTOR_TOTAL == 4)
|
||||
/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
|
||||
* @{
|
||||
*/
|
||||
#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Sector0 */
|
||||
#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Sector1 */
|
||||
#define OB_WRP_SECTOR_2 ((uint32_t)0x00040000U) /*!< Write protection of Sector2 */
|
||||
#define OB_WRP_SECTOR_3 ((uint32_t)0x00080000U) /*!< Write protection of Sector3 */
|
||||
#define OB_WRP_SECTOR_All ((uint32_t)0x000F0000U) /*!< Write protection of all Sectors */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* FLASH_SECTOR_TOTAL == 4 */
|
||||
|
||||
#if (FLASH_SECTOR_TOTAL == 2)
|
||||
/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
|
||||
* @{
|
||||
*/
|
||||
#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Sector0 */
|
||||
#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Sector1 */
|
||||
#define OB_WRP_SECTOR_All ((uint32_t)0x00030000U) /*!< Write protection of all Sectors */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* FLASH_SECTOR_TOTAL == 2 */
|
||||
|
||||
#if defined (FLASH_OPTCR2_PCROP)
|
||||
#if (FLASH_SECTOR_TOTAL == 8)
|
||||
/** @defgroup FLASHEx_Option_Bytes_PCROP_Sectors FLASH Option Bytes PCROP Sectors
|
||||
* @{
|
||||
*/
|
||||
#define OB_PCROP_SECTOR_0 ((uint32_t)0x00000001U) /*!< PC Readout protection of Sector0 */
|
||||
#define OB_PCROP_SECTOR_1 ((uint32_t)0x00000002U) /*!< PC Readout protection of Sector1 */
|
||||
#define OB_PCROP_SECTOR_2 ((uint32_t)0x00000004U) /*!< PC Readout protection of Sector2 */
|
||||
#define OB_PCROP_SECTOR_3 ((uint32_t)0x00000008U) /*!< PC Readout protection of Sector3 */
|
||||
#define OB_PCROP_SECTOR_4 ((uint32_t)0x00000010U) /*!< PC Readout protection of Sector4 */
|
||||
#define OB_PCROP_SECTOR_5 ((uint32_t)0x00000020U) /*!< PC Readout protection of Sector5 */
|
||||
#define OB_PCROP_SECTOR_6 ((uint32_t)0x00000040U) /*!< PC Readout protection of Sector6 */
|
||||
#define OB_PCROP_SECTOR_7 ((uint32_t)0x00000080U) /*!< PC Readout protection of Sector7 */
|
||||
#define OB_PCROP_SECTOR_All ((uint32_t)0x000000FFU) /*!< PC Readout protection of all Sectors */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* FLASH_SECTOR_TOTAL == 8 */
|
||||
|
||||
#if (FLASH_SECTOR_TOTAL == 4)
|
||||
/** @defgroup FLASHEx_Option_Bytes_PCROP_Sectors FLASH Option Bytes PCROP Sectors
|
||||
* @{
|
||||
*/
|
||||
#define OB_PCROP_SECTOR_0 ((uint32_t)0x00000001U) /*!< PC Readout protection of Sector0 */
|
||||
#define OB_PCROP_SECTOR_1 ((uint32_t)0x00000002U) /*!< PC Readout protection of Sector1 */
|
||||
#define OB_PCROP_SECTOR_2 ((uint32_t)0x00000004U) /*!< PC Readout protection of Sector2 */
|
||||
#define OB_PCROP_SECTOR_3 ((uint32_t)0x00000008U) /*!< PC Readout protection of Sector3 */
|
||||
#define OB_PCROP_SECTOR_All ((uint32_t)0x0000000FU) /*!< PC Readout protection of all Sectors */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* FLASH_SECTOR_TOTAL == 4 */
|
||||
|
||||
/** @defgroup FLASHEx_Option_Bytes_PCROP_RDP FLASH Option Bytes PCROP_RDP Bit
|
||||
* @{
|
||||
*/
|
||||
#define OB_PCROP_RDP_ENABLE ((uint32_t)0x80000000U) /*!< PCROP_RDP Enable */
|
||||
#define OB_PCROP_RDP_DISABLE ((uint32_t)0x00000000U) /*!< PCROP_RDP Disable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* FLASH_OPTCR2_PCROP */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Calculate the FLASH Boot Base Address (BOOT_ADD0 or BOOT_ADD1)
|
||||
* @note Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14].
|
||||
* @param __ADDRESS__ FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB)
|
||||
* @retval The FLASH Boot Base Address
|
||||
*/
|
||||
#define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup FLASHEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASHEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Extension Program operation functions *************************************/
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
|
||||
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
|
||||
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Private_Macros FLASH Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASHEx_IS_FLASH_Definitions FLASH Private macros to check input parameters
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FLASH_TYPEERASE(VALUE)(((VALUE) == FLASH_TYPEERASE_SECTORS) || \
|
||||
((VALUE) == FLASH_TYPEERASE_MASSERASE))
|
||||
|
||||
#define IS_VOLTAGERANGE(RANGE)(((RANGE) == FLASH_VOLTAGE_RANGE_1) || \
|
||||
((RANGE) == FLASH_VOLTAGE_RANGE_2) || \
|
||||
((RANGE) == FLASH_VOLTAGE_RANGE_3) || \
|
||||
((RANGE) == FLASH_VOLTAGE_RANGE_4))
|
||||
|
||||
#define IS_WRPSTATE(VALUE)(((VALUE) == OB_WRPSTATE_DISABLE) || \
|
||||
((VALUE) == OB_WRPSTATE_ENABLE))
|
||||
|
||||
#if defined (FLASH_OPTCR2_PCROP)
|
||||
#define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
|
||||
OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1 |\
|
||||
OPTIONBYTE_PCROP | OPTIONBYTE_PCROP_RDP)))
|
||||
#else
|
||||
#define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
|
||||
OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1)))
|
||||
#endif /* FLASH_OPTCR2_PCROP */
|
||||
|
||||
#define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013)
|
||||
|
||||
#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
|
||||
((LEVEL) == OB_RDP_LEVEL_1) ||\
|
||||
((LEVEL) == OB_RDP_LEVEL_2))
|
||||
|
||||
#define IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))
|
||||
|
||||
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
|
||||
|
||||
#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
|
||||
|
||||
#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
|
||||
|
||||
#define IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE))
|
||||
|
||||
#define IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE))
|
||||
|
||||
#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
|
||||
((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
|
||||
|
||||
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
|
||||
((LATENCY) == FLASH_LATENCY_1) || \
|
||||
((LATENCY) == FLASH_LATENCY_2) || \
|
||||
((LATENCY) == FLASH_LATENCY_3) || \
|
||||
((LATENCY) == FLASH_LATENCY_4) || \
|
||||
((LATENCY) == FLASH_LATENCY_5) || \
|
||||
((LATENCY) == FLASH_LATENCY_6) || \
|
||||
((LATENCY) == FLASH_LATENCY_7) || \
|
||||
((LATENCY) == FLASH_LATENCY_8) || \
|
||||
((LATENCY) == FLASH_LATENCY_9) || \
|
||||
((LATENCY) == FLASH_LATENCY_10) || \
|
||||
((LATENCY) == FLASH_LATENCY_11) || \
|
||||
((LATENCY) == FLASH_LATENCY_12) || \
|
||||
((LATENCY) == FLASH_LATENCY_13) || \
|
||||
((LATENCY) == FLASH_LATENCY_14) || \
|
||||
((LATENCY) == FLASH_LATENCY_15))
|
||||
|
||||
#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) || \
|
||||
(((ADDRESS) >= FLASH_OTP_BASE) && ((ADDRESS) <= FLASH_OTP_END)))
|
||||
#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0U) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
|
||||
|
||||
#if (FLASH_SECTOR_TOTAL == 8)
|
||||
#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
|
||||
((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
|
||||
((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\
|
||||
((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7))
|
||||
|
||||
#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFF00FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U))
|
||||
#endif /* FLASH_SECTOR_TOTAL == 8 */
|
||||
|
||||
#if (FLASH_SECTOR_TOTAL == 24)
|
||||
#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
|
||||
((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
|
||||
((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\
|
||||
((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7) ||\
|
||||
((SECTOR) == FLASH_SECTOR_8) || ((SECTOR) == FLASH_SECTOR_9) ||\
|
||||
((SECTOR) == FLASH_SECTOR_10) || ((SECTOR) == FLASH_SECTOR_11) ||\
|
||||
((SECTOR) == FLASH_SECTOR_12) || ((SECTOR) == FLASH_SECTOR_13) ||\
|
||||
((SECTOR) == FLASH_SECTOR_14) || ((SECTOR) == FLASH_SECTOR_15) ||\
|
||||
((SECTOR) == FLASH_SECTOR_16) || ((SECTOR) == FLASH_SECTOR_17) ||\
|
||||
((SECTOR) == FLASH_SECTOR_18) || ((SECTOR) == FLASH_SECTOR_19) ||\
|
||||
((SECTOR) == FLASH_SECTOR_20) || ((SECTOR) == FLASH_SECTOR_21) ||\
|
||||
((SECTOR) == FLASH_SECTOR_22) || ((SECTOR) == FLASH_SECTOR_23))
|
||||
|
||||
#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xF000FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U))
|
||||
#endif /* FLASH_SECTOR_TOTAL == 24 */
|
||||
|
||||
#if (FLASH_SECTOR_TOTAL == 4)
|
||||
#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
|
||||
((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3))
|
||||
|
||||
#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFFF0FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U))
|
||||
#endif /* FLASH_SECTOR_TOTAL == 4 */
|
||||
|
||||
#if (FLASH_SECTOR_TOTAL == 2)
|
||||
#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1))
|
||||
|
||||
#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFFFCFFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U))
|
||||
#endif /* FLASH_SECTOR_TOTAL == 2 */
|
||||
|
||||
#if defined (FLASH_OPTCR_nDBANK)
|
||||
#define IS_OB_NDBANK(VALUE) (((VALUE) == OB_NDBANK_SINGLE_BANK) || \
|
||||
((VALUE) == OB_NDBANK_DUAL_BANK))
|
||||
|
||||
#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \
|
||||
((BANK) == FLASH_BANK_2) || \
|
||||
((BANK) == FLASH_BANK_BOTH))
|
||||
#endif /* FLASH_OPTCR_nDBANK */
|
||||
|
||||
#if defined (FLASH_OPTCR_nDBOOT)
|
||||
#define IS_OB_NDBOOT(VALUE) (((VALUE) == OB_DUAL_BOOT_DISABLE) || \
|
||||
((VALUE) == OB_DUAL_BOOT_ENABLE))
|
||||
#endif /* FLASH_OPTCR_nDBOOT */
|
||||
|
||||
#if defined (FLASH_OPTCR2_PCROP)
|
||||
#define IS_OB_PCROP_SECTOR(SECTOR) (((SECTOR) & (uint32_t)0xFFFFFF00U) == 0x00000000U)
|
||||
#define IS_OB_PCROP_RDP_VALUE(VALUE) (((VALUE) == OB_PCROP_RDP_DISABLE) || \
|
||||
((VALUE) == OB_PCROP_RDP_ENABLE))
|
||||
#endif /* FLASH_OPTCR2_PCROP */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Private_Functions FLASH Private Functions
|
||||
* @{
|
||||
*/
|
||||
void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_FLASH_EX_H */
|
||||
|
||||
@ -0,0 +1,323 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_gpio.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of GPIO HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_GPIO_H
|
||||
#define __STM32F7xx_HAL_GPIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Exported_Types GPIO Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief GPIO Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
|
||||
This parameter can be any value of @ref GPIO_pins_define */
|
||||
|
||||
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_mode_define */
|
||||
|
||||
uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_pull_define */
|
||||
|
||||
uint32_t Speed; /*!< Specifies the speed for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_speed_define */
|
||||
|
||||
uint32_t Alternate; /*!< Peripheral to be connected to the selected pins.
|
||||
This parameter can be a value of @ref GPIO_Alternate_function_selection */
|
||||
}GPIO_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief GPIO Bit SET and Bit RESET enumeration
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_PIN_RESET = 0,
|
||||
GPIO_PIN_SET
|
||||
}GPIO_PinState;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_pins_define GPIO pins define
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */
|
||||
#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */
|
||||
#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */
|
||||
#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */
|
||||
#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */
|
||||
#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */
|
||||
#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */
|
||||
#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */
|
||||
#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */
|
||||
#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */
|
||||
#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */
|
||||
#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */
|
||||
#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */
|
||||
#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */
|
||||
#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */
|
||||
#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */
|
||||
#define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */
|
||||
|
||||
#define GPIO_PIN_MASK ((uint32_t)0x0000FFFFU) /* PIN mask for assert test */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_mode_define GPIO mode define
|
||||
* @brief GPIO Configuration Mode
|
||||
* Elements values convention: 0x00WX00YZ
|
||||
* - W : EXTI trigger detection on 3 bits
|
||||
* - X : EXTI mode (IT or Event) on 2 bits
|
||||
* - Y : Output type (Push Pull or Open Drain) on 1 bit
|
||||
* - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */
|
||||
#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */
|
||||
#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */
|
||||
#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */
|
||||
#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */
|
||||
|
||||
#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */
|
||||
|
||||
#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
||||
|
||||
#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_speed_define GPIO speed define
|
||||
* @brief GPIO Output Maximum frequency
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000U) /*!< Low speed */
|
||||
#define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001U) /*!< Medium speed */
|
||||
#define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002U) /*!< Fast speed */
|
||||
#define GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003U) /*!< High speed */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_pull_define GPIO pull define
|
||||
* @brief GPIO Pull-Up or Pull-Down Activation
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_NOPULL ((uint32_t)0x00000000U) /*!< No Pull-up or Pull-down activation */
|
||||
#define GPIO_PULLUP ((uint32_t)0x00000001U) /*!< Pull-up activation */
|
||||
#define GPIO_PULLDOWN ((uint32_t)0x00000002U) /*!< Pull-down activation */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified EXTI line flag is set or not.
|
||||
* @param __EXTI_LINE__ specifies the EXTI line flag to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval The new state of __EXTI_LINE__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Clears the EXTI's line pending flags.
|
||||
* @param __EXTI_LINE__ specifies the EXTI lines flags to clear.
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified EXTI line is asserted or not.
|
||||
* @param __EXTI_LINE__ specifies the EXTI line to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval The new state of __EXTI_LINE__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Clears the EXTI's line pending bits.
|
||||
* @param __EXTI_LINE__ specifies the EXTI lines to clear.
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Generates a Software interrupt on selected EXTI line.
|
||||
* @param __EXTI_LINE__ specifies the EXTI line to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include GPIO HAL Extension module */
|
||||
#include "stm32f7xx_hal_gpio_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup GPIO_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
|
||||
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
|
||||
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Private_Constants GPIO Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_MODE_Pos 0U
|
||||
#define GPIO_MODE (0x3UL << GPIO_MODE_Pos)
|
||||
#define MODE_INPUT (0x0UL << GPIO_MODE_Pos)
|
||||
#define MODE_OUTPUT (0x1UL << GPIO_MODE_Pos)
|
||||
#define MODE_AF (0x2UL << GPIO_MODE_Pos)
|
||||
#define MODE_ANALOG (0x3UL << GPIO_MODE_Pos)
|
||||
#define OUTPUT_TYPE_Pos 4U
|
||||
#define OUTPUT_TYPE (0x1UL << OUTPUT_TYPE_Pos)
|
||||
#define OUTPUT_PP (0x0UL << OUTPUT_TYPE_Pos)
|
||||
#define OUTPUT_OD (0x1UL << OUTPUT_TYPE_Pos)
|
||||
#define EXTI_MODE_Pos 16U
|
||||
#define EXTI_MODE (0x3UL << EXTI_MODE_Pos)
|
||||
#define EXTI_IT (0x1UL << EXTI_MODE_Pos)
|
||||
#define EXTI_EVT (0x2UL << EXTI_MODE_Pos)
|
||||
#define TRIGGER_MODE_Pos 20U
|
||||
#define TRIGGER_MODE (0x7UL << TRIGGER_MODE_Pos)
|
||||
#define TRIGGER_RISING (0x1UL << TRIGGER_MODE_Pos)
|
||||
#define TRIGGER_FALLING (0x2UL << TRIGGER_MODE_Pos)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Private_Macros GPIO Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
|
||||
#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U))
|
||||
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
|
||||
((MODE) == GPIO_MODE_OUTPUT_PP) ||\
|
||||
((MODE) == GPIO_MODE_OUTPUT_OD) ||\
|
||||
((MODE) == GPIO_MODE_AF_PP) ||\
|
||||
((MODE) == GPIO_MODE_AF_OD) ||\
|
||||
((MODE) == GPIO_MODE_IT_RISING) ||\
|
||||
((MODE) == GPIO_MODE_IT_FALLING) ||\
|
||||
((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\
|
||||
((MODE) == GPIO_MODE_EVT_RISING) ||\
|
||||
((MODE) == GPIO_MODE_EVT_FALLING) ||\
|
||||
((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
|
||||
((MODE) == GPIO_MODE_ANALOG))
|
||||
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_LOW) || ((SPEED) == GPIO_SPEED_MEDIUM) || \
|
||||
((SPEED) == GPIO_SPEED_FAST) || ((SPEED) == GPIO_SPEED_HIGH))
|
||||
#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
|
||||
((PULL) == GPIO_PULLDOWN))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Private_Functions GPIO Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_GPIO_H */
|
||||
|
||||
@ -0,0 +1,656 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_gpio_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of GPIO HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_GPIO_EX_H
|
||||
#define __STM32F7xx_HAL_GPIO_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIOEx GPIOEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection
|
||||
* @{
|
||||
*/
|
||||
/*--------------- STM32F74xxx/STM32F75xxx/STM32F76xxx/STM32F77xxx -------------*/
|
||||
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) ||\
|
||||
defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx)
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
*/
|
||||
#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
|
||||
#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
*/
|
||||
#define GPIO_AF1_TIM1 ((uint8_t)0x01U) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
|
||||
#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
|
||||
#define GPIO_AF1_UART5 ((uint8_t)0x01U) /* UART5 Alternate Function mapping */
|
||||
#define GPIO_AF1_I2C4 ((uint8_t)0x01U) /* I2C4 Alternate Function mapping */
|
||||
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
*/
|
||||
#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM5 ((uint8_t)0x02U) /* TIM5 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
#define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM9 ((uint8_t)0x03U) /* TIM9 Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM10 ((uint8_t)0x03U) /* TIM10 Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM11 ((uint8_t)0x03U) /* TIM11 Alternate Function mapping */
|
||||
#define GPIO_AF3_LPTIM1 ((uint8_t)0x03U) /* LPTIM1 Alternate Function mapping */
|
||||
#define GPIO_AF3_CEC ((uint8_t)0x03U) /* CEC Alternate Function mapping */
|
||||
#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
|
||||
#define GPIO_AF3_DFSDM1 ((uint8_t)0x03U) /* DFSDM1 Alternate Function mapping */
|
||||
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
*/
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C3 ((uint8_t)0x04U) /* I2C3 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C4 ((uint8_t)0x04U) /* I2C4 Alternate Function mapping */
|
||||
#define GPIO_AF4_CEC ((uint8_t)0x04U) /* CEC Alternate Function mapping */
|
||||
#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
|
||||
#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */
|
||||
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
*/
|
||||
#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI4 ((uint8_t)0x05U) /* SPI4 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI5 ((uint8_t)0x05U) /* SPI5 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI6 ((uint8_t)0x05U) /* SPI6 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
*/
|
||||
#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */
|
||||
#define GPIO_AF6_SAI1 ((uint8_t)0x06U) /* SAI1 Alternate Function mapping */
|
||||
#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
|
||||
#define GPIO_AF6_UART4 ((uint8_t)0x06U) /* UART4 Alternate Function mapping */
|
||||
#define GPIO_AF6_DFSDM1 ((uint8_t)0x06U) /* DFSDM1 Alternate Function mapping */
|
||||
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
*/
|
||||
#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
|
||||
#define GPIO_AF7_UART5 ((uint8_t)0x07U) /* UART5 Alternate Function mapping */
|
||||
#define GPIO_AF7_SPDIFRX ((uint8_t)0x07U) /* SPDIF-RX Alternate Function mapping */
|
||||
#define GPIO_AF7_SPI2 ((uint8_t)0x07U) /* SPI2 Alternate Function mapping */
|
||||
#define GPIO_AF7_SPI3 ((uint8_t)0x07U) /* SPI3 Alternate Function mapping */
|
||||
#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
|
||||
#define GPIO_AF7_SPI6 ((uint8_t)0x07U) /* SPI6 Alternate Function mapping */
|
||||
#define GPIO_AF7_DFSDM1 ((uint8_t)0x07U) /* DFSDM1 Alternate Function mapping */
|
||||
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
|
||||
/**
|
||||
* @brief AF 8 selection
|
||||
*/
|
||||
#define GPIO_AF8_UART4 ((uint8_t)0x08U) /* UART4 Alternate Function mapping */
|
||||
#define GPIO_AF8_UART5 ((uint8_t)0x08U) /* UART5 Alternate Function mapping */
|
||||
#define GPIO_AF8_USART6 ((uint8_t)0x08U) /* USART6 Alternate Function mapping */
|
||||
#define GPIO_AF8_UART7 ((uint8_t)0x08U) /* UART7 Alternate Function mapping */
|
||||
#define GPIO_AF8_UART8 ((uint8_t)0x08U) /* UART8 Alternate Function mapping */
|
||||
#define GPIO_AF8_SPDIFRX ((uint8_t)0x08U) /* SPIDIF-RX Alternate Function mapping */
|
||||
#define GPIO_AF8_SAI2 ((uint8_t)0x08U) /* SAI2 Alternate Function mapping */
|
||||
#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
|
||||
#define GPIO_AF8_SPI6 ((uint8_t)0x08U) /* SPI6 Alternate Function mapping */
|
||||
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
|
||||
|
||||
/**
|
||||
* @brief AF 9 selection
|
||||
*/
|
||||
#define GPIO_AF9_CAN1 ((uint8_t)0x09U) /* CAN1 Alternate Function mapping */
|
||||
#define GPIO_AF9_CAN2 ((uint8_t)0x09U) /* CAN2 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM12 ((uint8_t)0x09U) /* TIM12 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM13 ((uint8_t)0x09U) /* TIM13 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM14 ((uint8_t)0x09U) /* TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF9_QUADSPI ((uint8_t)0x09U) /* QUADSPI Alternate Function mapping */
|
||||
#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined(STM32F750xx)
|
||||
#define GPIO_AF9_LTDC ((uint8_t)0x09U) /* LCD-TFT Alternate Function mapping */
|
||||
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
|
||||
#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F765xx) || defined(STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined(STM32F750xx)
|
||||
#define GPIO_AF9_FMC ((uint8_t)0x09U) /* FMC Alternate Function mapping */
|
||||
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
|
||||
/**
|
||||
* @brief AF 10 selection
|
||||
*/
|
||||
#define GPIO_AF10_OTG_FS ((uint8_t)0xAU) /* OTG_FS Alternate Function mapping */
|
||||
#define GPIO_AF10_OTG_HS ((uint8_t)0xAU) /* OTG_HS Alternate Function mapping */
|
||||
#define GPIO_AF10_QUADSPI ((uint8_t)0xAU) /* QUADSPI Alternate Function mapping */
|
||||
#define GPIO_AF10_SAI2 ((uint8_t)0xAU) /* SAI2 Alternate Function mapping */
|
||||
#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
|
||||
#define GPIO_AF10_DFSDM1 ((uint8_t)0x0AU) /* DFSDM1 Alternate Function mapping */
|
||||
#define GPIO_AF10_SDMMC2 ((uint8_t)0x0AU) /* SDMMC2 Alternate Function mapping */
|
||||
#define GPIO_AF10_LTDC ((uint8_t)0x0AU) /* LCD-TFT Alternate Function mapping */
|
||||
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
|
||||
/**
|
||||
* @brief AF 11 selection
|
||||
*/
|
||||
#define GPIO_AF11_ETH ((uint8_t)0x0BU) /* ETHERNET Alternate Function mapping */
|
||||
#if defined(STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
|
||||
#define GPIO_AF11_CAN3 ((uint8_t)0x0BU) /* CAN3 Alternate Function mapping */
|
||||
#define GPIO_AF11_SDMMC2 ((uint8_t)0x0BU) /* SDMMC2 Alternate Function mapping */
|
||||
#define GPIO_AF11_I2C4 ((uint8_t)0x0BU) /* I2C4 Alternate Function mapping */
|
||||
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
|
||||
/**
|
||||
* @brief AF 12 selection
|
||||
*/
|
||||
#define GPIO_AF12_FMC ((uint8_t)0xCU) /* FMC Alternate Function mapping */
|
||||
#define GPIO_AF12_OTG_HS_FS ((uint8_t)0xCU) /* OTG HS configured in FS, Alternate Function mapping */
|
||||
#define GPIO_AF12_SDMMC1 ((uint8_t)0xCU) /* SDMMC1 Alternate Function mapping */
|
||||
#if defined(STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
|
||||
#define GPIO_AF12_MDIOS ((uint8_t)0xCU) /* SDMMC1 Alternate Function mapping */
|
||||
#define GPIO_AF12_UART7 ((uint8_t)0xCU) /* UART7 Alternate Function mapping */
|
||||
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
|
||||
/**
|
||||
* @brief AF 13 selection
|
||||
*/
|
||||
#define GPIO_AF13_DCMI ((uint8_t)0x0DU) /* DCMI Alternate Function mapping */
|
||||
#if defined (STM32F769xx) || defined (STM32F779xx)
|
||||
#define GPIO_AF13_DSI ((uint8_t)0x0DU) /* DSI Alternate Function mapping */
|
||||
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined(STM32F750xx)
|
||||
#define GPIO_AF13_LTDC ((uint8_t)0x0DU) /* LTDC Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 14 selection
|
||||
*/
|
||||
#define GPIO_AF14_LTDC ((uint8_t)0x0EU) /* LCD-TFT Alternate Function mapping */
|
||||
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
|
||||
/**
|
||||
* @brief AF 15 selection
|
||||
*/
|
||||
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
|
||||
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
/*---------------------------- STM32F72xxx/STM32F73xxx -----------------------*/
|
||||
#if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F732xx) || defined(STM32F733xx) || defined(STM32F730xx)
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
*/
|
||||
#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
|
||||
#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
*/
|
||||
#define GPIO_AF1_TIM1 ((uint8_t)0x01U) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
*/
|
||||
#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM5 ((uint8_t)0x02U) /* TIM5 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
#define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM9 ((uint8_t)0x03U) /* TIM9 Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM10 ((uint8_t)0x03U) /* TIM10 Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM11 ((uint8_t)0x03U) /* TIM11 Alternate Function mapping */
|
||||
#define GPIO_AF3_LPTIM1 ((uint8_t)0x03U) /* LPTIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
*/
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C3 ((uint8_t)0x04U) /* I2C3 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
*/
|
||||
#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI4 ((uint8_t)0x05U) /* SPI4 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI5 ((uint8_t)0x05U) /* SPI5 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
*/
|
||||
#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */
|
||||
#define GPIO_AF6_SAI1 ((uint8_t)0x06U) /* SAI1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
*/
|
||||
#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
|
||||
#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
|
||||
#define GPIO_AF7_UART5 ((uint8_t)0x07U) /* UART5 Alternate Function mapping */
|
||||
#define GPIO_AF7_SPI2 ((uint8_t)0x07U) /* SPI2 Alternate Function mapping */
|
||||
#define GPIO_AF7_SPI3 ((uint8_t)0x07U) /* SPI3 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 8 selection
|
||||
*/
|
||||
#define GPIO_AF8_UART4 ((uint8_t)0x08U) /* UART4 Alternate Function mapping */
|
||||
#define GPIO_AF8_UART5 ((uint8_t)0x08U) /* UART5 Alternate Function mapping */
|
||||
#define GPIO_AF8_USART6 ((uint8_t)0x08U) /* USART6 Alternate Function mapping */
|
||||
#define GPIO_AF8_UART7 ((uint8_t)0x08U) /* UART7 Alternate Function mapping */
|
||||
#define GPIO_AF8_UART8 ((uint8_t)0x08U) /* UART8 Alternate Function mapping */
|
||||
#define GPIO_AF8_SAI2 ((uint8_t)0x08U) /* SAI2 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 9 selection
|
||||
*/
|
||||
#define GPIO_AF9_CAN1 ((uint8_t)0x09U) /* CAN1 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM12 ((uint8_t)0x09U) /* TIM12 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM13 ((uint8_t)0x09U) /* TIM13 Alternate Function mapping */
|
||||
#define GPIO_AF9_TIM14 ((uint8_t)0x09U) /* TIM14 Alternate Function mapping */
|
||||
#define GPIO_AF9_QUADSPI ((uint8_t)0x09U) /* QUADSPI Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 10 selection
|
||||
*/
|
||||
#define GPIO_AF10_OTG_FS ((uint8_t)0xAU) /* OTG_FS Alternate Function mapping */
|
||||
#define GPIO_AF10_OTG_HS ((uint8_t)0xAU) /* OTG_HS Alternate Function mapping */
|
||||
#define GPIO_AF10_QUADSPI ((uint8_t)0xAU) /* QUADSPI Alternate Function mapping */
|
||||
#define GPIO_AF10_SAI2 ((uint8_t)0xAU) /* SAI2 Alternate Function mapping */
|
||||
#define GPIO_AF10_SDMMC2 ((uint8_t)0x0AU) /* SDMMC2 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 11 selection
|
||||
*/
|
||||
#define GPIO_AF11_SDMMC2 ((uint8_t)0x0BU) /* SDMMC2 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 12 selection
|
||||
*/
|
||||
#define GPIO_AF12_FMC ((uint8_t)0xCU) /* FMC Alternate Function mapping */
|
||||
#define GPIO_AF12_OTG_HS_FS ((uint8_t)0xCU) /* OTG HS configured in FS, Alternate Function mapping */
|
||||
#define GPIO_AF12_SDMMC1 ((uint8_t)0xCU) /* SDMMC1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 13 selection
|
||||
*/
|
||||
#define GPIO_AF13_RNG ((uint8_t)0x0DU) /* RNG Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 15 selection
|
||||
*/
|
||||
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
|
||||
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup GPIOEx_Private_Constants GPIO Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief GPIO pin available on the platform
|
||||
*/
|
||||
/* Defines the available pins per GPIOs */
|
||||
#define GPIOA_PIN_AVAILABLE GPIO_PIN_All
|
||||
#define GPIOB_PIN_AVAILABLE GPIO_PIN_All
|
||||
#define GPIOC_PIN_AVAILABLE GPIO_PIN_All
|
||||
#define GPIOD_PIN_AVAILABLE GPIO_PIN_All
|
||||
#define GPIOE_PIN_AVAILABLE GPIO_PIN_All
|
||||
#define GPIOF_PIN_AVAILABLE GPIO_PIN_All
|
||||
#define GPIOG_PIN_AVAILABLE GPIO_PIN_All
|
||||
#define GPIOI_PIN_AVAILABLE GPIO_PIN_All
|
||||
#define GPIOJ_PIN_AVAILABLE GPIO_PIN_All
|
||||
#define GPIOH_PIN_AVAILABLE GPIO_PIN_All
|
||||
#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | \
|
||||
GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup GPIOEx_Private_Macros GPIO Private Macros
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\
|
||||
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\
|
||||
defined (STM32F750xx)
|
||||
#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
|
||||
((__GPIOx__) == (GPIOB))? 1U :\
|
||||
((__GPIOx__) == (GPIOC))? 2U :\
|
||||
((__GPIOx__) == (GPIOD))? 3U :\
|
||||
((__GPIOx__) == (GPIOE))? 4U :\
|
||||
((__GPIOx__) == (GPIOF))? 5U :\
|
||||
((__GPIOx__) == (GPIOG))? 6U :\
|
||||
((__GPIOx__) == (GPIOH))? 7U :\
|
||||
((__GPIOx__) == (GPIOI))? 8U :\
|
||||
((__GPIOx__) == (GPIOJ))? 9U : 10U)
|
||||
#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */
|
||||
|
||||
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)
|
||||
#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
|
||||
((__GPIOx__) == (GPIOB))? 1U :\
|
||||
((__GPIOx__) == (GPIOC))? 2U :\
|
||||
((__GPIOx__) == (GPIOD))? 3U :\
|
||||
((__GPIOx__) == (GPIOE))? 4U :\
|
||||
((__GPIOx__) == (GPIOF))? 5U :\
|
||||
((__GPIOx__) == (GPIOG))? 6U :\
|
||||
((__GPIOx__) == (GPIOH))? 7U : 8U)
|
||||
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define IS_GPIO_PIN_AVAILABLE(__INSTANCE__,__PIN__) \
|
||||
((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \
|
||||
(((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || \
|
||||
(((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || \
|
||||
(((__INSTANCE__) == GPIOD) && (((__PIN__) & (GPIOD_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOD_PIN_AVAILABLE)) == (GPIOD_PIN_AVAILABLE))) || \
|
||||
(((__INSTANCE__) == GPIOE) && (((__PIN__) & (GPIOE_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOE_PIN_AVAILABLE)) == (GPIOE_PIN_AVAILABLE))) || \
|
||||
(((__INSTANCE__) == GPIOF) && (((__PIN__) & (GPIOF_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOF_PIN_AVAILABLE)) == (GPIOF_PIN_AVAILABLE))) || \
|
||||
(((__INSTANCE__) == GPIOG) && (((__PIN__) & (GPIOG_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOG_PIN_AVAILABLE)) == (GPIOG_PIN_AVAILABLE))) || \
|
||||
(((__INSTANCE__) == GPIOI) && (((__PIN__) & (GPIOI_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOI_PIN_AVAILABLE)) == (GPIOI_PIN_AVAILABLE))) || \
|
||||
(((__INSTANCE__) == GPIOJ) && (((__PIN__) & (GPIOJ_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOJ_PIN_AVAILABLE)) == (GPIOJ_PIN_AVAILABLE))) || \
|
||||
(((__INSTANCE__) == GPIOK) && (((__PIN__) & (GPIOK_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOK_PIN_AVAILABLE)) == (GPIOK_PIN_AVAILABLE))) || \
|
||||
(((__INSTANCE__) == GPIOH) && (((__PIN__) & (GPIOH_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOH_PIN_AVAILABLE)) == (GPIOH_PIN_AVAILABLE))))
|
||||
/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F756xx) || defined(STM32F746xx) || defined(STM32F750xx)
|
||||
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \
|
||||
((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
|
||||
((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \
|
||||
((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
|
||||
((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
|
||||
((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \
|
||||
((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \
|
||||
((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \
|
||||
((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
|
||||
((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \
|
||||
((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \
|
||||
((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \
|
||||
((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \
|
||||
((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \
|
||||
((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \
|
||||
((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
|
||||
((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \
|
||||
((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \
|
||||
((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \
|
||||
((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \
|
||||
((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \
|
||||
((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
|
||||
((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \
|
||||
((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \
|
||||
((AF) == GPIO_AF9_LTDC) || ((AF) == GPIO_AF10_OTG_FS) || \
|
||||
((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \
|
||||
((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \
|
||||
((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \
|
||||
((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT) || \
|
||||
((AF) == GPIO_AF13_DCMI) || ((AF) == GPIO_AF14_LTDC))
|
||||
#elif defined(STM32F745xx)
|
||||
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \
|
||||
((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
|
||||
((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \
|
||||
((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
|
||||
((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
|
||||
((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \
|
||||
((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \
|
||||
((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \
|
||||
((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
|
||||
((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \
|
||||
((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \
|
||||
((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \
|
||||
((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \
|
||||
((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \
|
||||
((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \
|
||||
((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
|
||||
((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \
|
||||
((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \
|
||||
((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \
|
||||
((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \
|
||||
((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \
|
||||
((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
|
||||
((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \
|
||||
((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \
|
||||
((AF) == GPIO_AF13_DCMI) || ((AF) == GPIO_AF10_OTG_FS) || \
|
||||
((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \
|
||||
((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \
|
||||
((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \
|
||||
((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT))
|
||||
#elif defined(STM32F767xx) || defined(STM32F777xx)
|
||||
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \
|
||||
((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
|
||||
((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \
|
||||
((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
|
||||
((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
|
||||
((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \
|
||||
((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \
|
||||
((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \
|
||||
((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
|
||||
((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \
|
||||
((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \
|
||||
((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \
|
||||
((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \
|
||||
((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \
|
||||
((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \
|
||||
((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
|
||||
((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \
|
||||
((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \
|
||||
((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \
|
||||
((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \
|
||||
((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \
|
||||
((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
|
||||
((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \
|
||||
((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \
|
||||
((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF9_LTDC) || \
|
||||
((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \
|
||||
((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \
|
||||
((AF) == GPIO_AF10_SDMMC2) || ((AF) == GPIO_AF11_SDMMC2) || \
|
||||
((AF) == GPIO_AF11_CAN3) || ((AF) == GPIO_AF12_OTG_HS_FS) || \
|
||||
((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \
|
||||
((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \
|
||||
((AF) == GPIO_AF14_LTDC))
|
||||
#elif defined(STM32F769xx) || defined(STM32F779xx)
|
||||
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \
|
||||
((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
|
||||
((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \
|
||||
((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
|
||||
((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
|
||||
((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \
|
||||
((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \
|
||||
((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \
|
||||
((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
|
||||
((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \
|
||||
((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \
|
||||
((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \
|
||||
((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \
|
||||
((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \
|
||||
((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \
|
||||
((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
|
||||
((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \
|
||||
((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \
|
||||
((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \
|
||||
((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \
|
||||
((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \
|
||||
((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
|
||||
((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \
|
||||
((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \
|
||||
((AF) == GPIO_AF9_LTDC) || ((AF) == GPIO_AF10_OTG_FS) || \
|
||||
((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \
|
||||
((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \
|
||||
((AF) == GPIO_AF10_SDMMC2) || ((AF) == GPIO_AF11_SDMMC2) || \
|
||||
((AF) == GPIO_AF11_CAN3) || ((AF) == GPIO_AF12_OTG_HS_FS) || \
|
||||
((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \
|
||||
((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \
|
||||
((AF) == GPIO_AF14_LTDC) || ((AF) == GPIO_AF13_DSI))
|
||||
#elif defined(STM32F765xx)
|
||||
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \
|
||||
((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
|
||||
((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \
|
||||
((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
|
||||
((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
|
||||
((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \
|
||||
((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \
|
||||
((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \
|
||||
((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
|
||||
((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \
|
||||
((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \
|
||||
((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \
|
||||
((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \
|
||||
((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \
|
||||
((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \
|
||||
((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
|
||||
((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \
|
||||
((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \
|
||||
((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \
|
||||
((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \
|
||||
((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \
|
||||
((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
|
||||
((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \
|
||||
((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \
|
||||
((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \
|
||||
((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \
|
||||
((AF) == GPIO_AF10_SDMMC2) || ((AF) == GPIO_AF11_SDMMC2) || \
|
||||
((AF) == GPIO_AF11_CAN3) || ((AF) == GPIO_AF12_OTG_HS_FS) || \
|
||||
((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \
|
||||
((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \
|
||||
((AF) == GPIO_AF10_OTG_FS))
|
||||
#elif defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx)
|
||||
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \
|
||||
((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
|
||||
((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \
|
||||
((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
|
||||
((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
|
||||
((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \
|
||||
((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \
|
||||
((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
|
||||
((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \
|
||||
((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF5_SPI3) || \
|
||||
((AF) == GPIO_AF5_SPI4) || ((AF) == GPIO_AF5_SPI5) || \
|
||||
((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \
|
||||
((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \
|
||||
((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
|
||||
((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \
|
||||
((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \
|
||||
((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \
|
||||
((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \
|
||||
((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_TIM12) || \
|
||||
((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM14) || \
|
||||
((AF) == GPIO_AF9_QUADSPI) || ((AF) == GPIO_AF10_OTG_HS) || \
|
||||
((AF) == GPIO_AF10_SAI2) || ((AF) == GPIO_AF10_QUADSPI) || \
|
||||
((AF) == GPIO_AF10_SDMMC2) || ((AF) == GPIO_AF11_SDMMC2) || \
|
||||
((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \
|
||||
((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT) || \
|
||||
((AF) == GPIO_AF10_OTG_FS))
|
||||
#endif /* STM32F756xx || STM32F746xx || STM32F750xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup GPIOEx_Private_Functions GPIO Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_GPIO_EX_H */
|
||||
|
||||
@ -0,0 +1,835 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_i2c.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of I2C HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F7xx_HAL_I2C_H
|
||||
#define STM32F7xx_HAL_I2C_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup I2C_Exported_Types I2C Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
|
||||
* @brief I2C Configuration Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.
|
||||
This parameter calculated by referring to I2C initialization section
|
||||
in Reference manual */
|
||||
|
||||
uint32_t OwnAddress1; /*!< Specifies the first device own address.
|
||||
This parameter can be a 7-bit or 10-bit address. */
|
||||
|
||||
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
|
||||
This parameter can be a value of @ref I2C_ADDRESSING_MODE */
|
||||
|
||||
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
|
||||
This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
|
||||
|
||||
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
|
||||
This parameter can be a 7-bit address. */
|
||||
|
||||
uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing
|
||||
mode is selected.
|
||||
This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
|
||||
|
||||
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
|
||||
This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
|
||||
|
||||
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
|
||||
This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
|
||||
|
||||
} I2C_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_state_structure_definition HAL state structure definition
|
||||
* @brief HAL State structure definition
|
||||
* @note HAL I2C State value coding follow below described bitmap :\n
|
||||
* b7-b6 Error information\n
|
||||
* 00 : No Error\n
|
||||
* 01 : Abort (Abort user request on going)\n
|
||||
* 10 : Timeout\n
|
||||
* 11 : Error\n
|
||||
* b5 Peripheral initialization status\n
|
||||
* 0 : Reset (peripheral not initialized)\n
|
||||
* 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n
|
||||
* b4 (not used)\n
|
||||
* x : Should be set to 0\n
|
||||
* b3\n
|
||||
* 0 : Ready or Busy (No Listen mode ongoing)\n
|
||||
* 1 : Listen (peripheral in Address Listen Mode)\n
|
||||
* b2 Intrinsic process state\n
|
||||
* 0 : Ready\n
|
||||
* 1 : Busy (peripheral busy with some configuration or internal operations)\n
|
||||
* b1 Rx state\n
|
||||
* 0 : Ready (no Rx operation ongoing)\n
|
||||
* 1 : Busy (Rx operation ongoing)\n
|
||||
* b0 Tx state\n
|
||||
* 0 : Ready (no Tx operation ongoing)\n
|
||||
* 1 : Busy (Tx operation ongoing)
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
|
||||
HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
|
||||
HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
|
||||
HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
|
||||
HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
|
||||
HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
|
||||
HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
|
||||
process is ongoing */
|
||||
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
|
||||
process is ongoing */
|
||||
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
|
||||
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
|
||||
HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
|
||||
|
||||
} HAL_I2C_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_mode_structure_definition HAL mode structure definition
|
||||
* @brief HAL Mode structure definition
|
||||
* @note HAL I2C Mode value coding follow below described bitmap :\n
|
||||
* b7 (not used)\n
|
||||
* x : Should be set to 0\n
|
||||
* b6\n
|
||||
* 0 : None\n
|
||||
* 1 : Memory (HAL I2C communication is in Memory Mode)\n
|
||||
* b5\n
|
||||
* 0 : None\n
|
||||
* 1 : Slave (HAL I2C communication is in Slave Mode)\n
|
||||
* b4\n
|
||||
* 0 : None\n
|
||||
* 1 : Master (HAL I2C communication is in Master Mode)\n
|
||||
* b3-b2-b1-b0 (not used)\n
|
||||
* xxxx : Should be set to 0000
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
|
||||
HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
|
||||
HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
|
||||
HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
|
||||
|
||||
} HAL_I2C_ModeTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Error_Code_definition I2C Error Code definition
|
||||
* @brief I2C Error Code definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */
|
||||
#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */
|
||||
#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */
|
||||
#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */
|
||||
#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
|
||||
#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
|
||||
#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */
|
||||
#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
|
||||
* @brief I2C handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct __I2C_HandleTypeDef
|
||||
{
|
||||
I2C_TypeDef *Instance; /*!< I2C registers base address */
|
||||
|
||||
I2C_InitTypeDef Init; /*!< I2C communication parameters */
|
||||
|
||||
uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
|
||||
|
||||
uint16_t XferSize; /*!< I2C transfer size */
|
||||
|
||||
__IO uint16_t XferCount; /*!< I2C transfer counter */
|
||||
|
||||
__IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can
|
||||
be a value of @ref I2C_XFEROPTIONS */
|
||||
|
||||
__IO uint32_t PreviousState; /*!< I2C communication Previous state */
|
||||
|
||||
HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
|
||||
/*!< I2C transfer IRQ handler function pointer */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< I2C locking object */
|
||||
|
||||
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
|
||||
|
||||
__IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< I2C Error code */
|
||||
|
||||
__IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
|
||||
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Master Tx Transfer completed callback */
|
||||
void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Master Rx Transfer completed callback */
|
||||
void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Slave Tx Transfer completed callback */
|
||||
void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Slave Rx Transfer completed callback */
|
||||
void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Listen Complete callback */
|
||||
void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Memory Tx Transfer completed callback */
|
||||
void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Memory Rx Transfer completed callback */
|
||||
void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Error callback */
|
||||
void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Abort callback */
|
||||
|
||||
void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
|
||||
/*!< I2C Slave Address Match callback */
|
||||
|
||||
void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);
|
||||
/*!< I2C Msp DeInit callback */
|
||||
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
} I2C_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL I2C Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */
|
||||
HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */
|
||||
HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */
|
||||
HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */
|
||||
HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */
|
||||
HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */
|
||||
HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */
|
||||
HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */
|
||||
HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */
|
||||
|
||||
HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */
|
||||
HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */
|
||||
|
||||
} HAL_I2C_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL I2C Callback pointer definition
|
||||
*/
|
||||
typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c);
|
||||
/*!< pointer to an I2C callback function */
|
||||
typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection,
|
||||
uint16_t AddrMatchCode);
|
||||
/*!< pointer to an I2C Address Match callback function */
|
||||
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2C_Exported_Constants I2C Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options
|
||||
* @{
|
||||
*/
|
||||
#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
|
||||
#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
|
||||
#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
|
||||
#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
|
||||
#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
|
||||
#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE)
|
||||
|
||||
/* List of XferOptions in usage of :
|
||||
* 1- Restart condition in all use cases (direction change or not)
|
||||
*/
|
||||
#define I2C_OTHER_FRAME (0x000000AAU)
|
||||
#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_ADDRESSINGMODE_7BIT (0x00000001U)
|
||||
#define I2C_ADDRESSINGMODE_10BIT (0x00000002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_DUALADDRESS_DISABLE (0x00000000U)
|
||||
#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
|
||||
* @{
|
||||
*/
|
||||
#define I2C_OA2_NOMASK ((uint8_t)0x00U)
|
||||
#define I2C_OA2_MASK01 ((uint8_t)0x01U)
|
||||
#define I2C_OA2_MASK02 ((uint8_t)0x02U)
|
||||
#define I2C_OA2_MASK03 ((uint8_t)0x03U)
|
||||
#define I2C_OA2_MASK04 ((uint8_t)0x04U)
|
||||
#define I2C_OA2_MASK05 ((uint8_t)0x05U)
|
||||
#define I2C_OA2_MASK06 ((uint8_t)0x06U)
|
||||
#define I2C_OA2_MASK07 ((uint8_t)0x07U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_GENERALCALL_DISABLE (0x00000000U)
|
||||
#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_NOSTRETCH_DISABLE (0x00000000U)
|
||||
#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
|
||||
* @{
|
||||
*/
|
||||
#define I2C_MEMADD_SIZE_8BIT (0x00000001U)
|
||||
#define I2C_MEMADD_SIZE_16BIT (0x00000002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
|
||||
* @{
|
||||
*/
|
||||
#define I2C_DIRECTION_TRANSMIT (0x00000000U)
|
||||
#define I2C_DIRECTION_RECEIVE (0x00000001U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_RELOAD_MODE I2C_CR2_RELOAD
|
||||
#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
|
||||
#define I2C_SOFTEND_MODE (0x00000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_NO_STARTSTOP (0x00000000U)
|
||||
#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
|
||||
#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
|
||||
#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
|
||||
* @brief I2C Interrupt definition
|
||||
* Elements values convention: 0xXXXXXXXX
|
||||
* - XXXXXXXX : Interrupt control mask
|
||||
* @{
|
||||
*/
|
||||
#define I2C_IT_ERRI I2C_CR1_ERRIE
|
||||
#define I2C_IT_TCI I2C_CR1_TCIE
|
||||
#define I2C_IT_STOPI I2C_CR1_STOPIE
|
||||
#define I2C_IT_NACKI I2C_CR1_NACKIE
|
||||
#define I2C_IT_ADDRI I2C_CR1_ADDRIE
|
||||
#define I2C_IT_RXI I2C_CR1_RXIE
|
||||
#define I2C_IT_TXI I2C_CR1_TXIE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Flag_definition I2C Flag definition
|
||||
* @{
|
||||
*/
|
||||
#define I2C_FLAG_TXE I2C_ISR_TXE
|
||||
#define I2C_FLAG_TXIS I2C_ISR_TXIS
|
||||
#define I2C_FLAG_RXNE I2C_ISR_RXNE
|
||||
#define I2C_FLAG_ADDR I2C_ISR_ADDR
|
||||
#define I2C_FLAG_AF I2C_ISR_NACKF
|
||||
#define I2C_FLAG_STOPF I2C_ISR_STOPF
|
||||
#define I2C_FLAG_TC I2C_ISR_TC
|
||||
#define I2C_FLAG_TCR I2C_ISR_TCR
|
||||
#define I2C_FLAG_BERR I2C_ISR_BERR
|
||||
#define I2C_FLAG_ARLO I2C_ISR_ARLO
|
||||
#define I2C_FLAG_OVR I2C_ISR_OVR
|
||||
#define I2C_FLAG_PECERR I2C_ISR_PECERR
|
||||
#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
|
||||
#define I2C_FLAG_ALERT I2C_ISR_ALERT
|
||||
#define I2C_FLAG_BUSY I2C_ISR_BUSY
|
||||
#define I2C_FLAG_DIR I2C_ISR_DIR
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2C_Exported_Macros I2C Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset I2C handle state.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_I2C_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
|
||||
/** @brief Enable the specified I2C interrupt.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref I2C_IT_ERRI Errors interrupt enable
|
||||
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
|
||||
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
|
||||
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
|
||||
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
|
||||
* @arg @ref I2C_IT_RXI RX interrupt enable
|
||||
* @arg @ref I2C_IT_TXI TX interrupt enable
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
|
||||
|
||||
/** @brief Disable the specified I2C interrupt.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref I2C_IT_ERRI Errors interrupt enable
|
||||
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
|
||||
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
|
||||
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
|
||||
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
|
||||
* @arg @ref I2C_IT_RXI RX interrupt enable
|
||||
* @arg @ref I2C_IT_TXI TX interrupt enable
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
|
||||
|
||||
/** @brief Check whether the specified I2C interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __INTERRUPT__ specifies the I2C interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref I2C_IT_ERRI Errors interrupt enable
|
||||
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
|
||||
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
|
||||
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
|
||||
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
|
||||
* @arg @ref I2C_IT_RXI RX interrupt enable
|
||||
* @arg @ref I2C_IT_TXI TX interrupt enable
|
||||
*
|
||||
* @retval The new state of __INTERRUPT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \
|
||||
(__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified I2C flag is set or not.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref I2C_FLAG_TXE Transmit data register empty
|
||||
* @arg @ref I2C_FLAG_TXIS Transmit interrupt status
|
||||
* @arg @ref I2C_FLAG_RXNE Receive data register not empty
|
||||
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
|
||||
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
|
||||
* @arg @ref I2C_FLAG_STOPF STOP detection flag
|
||||
* @arg @ref I2C_FLAG_TC Transfer complete (master mode)
|
||||
* @arg @ref I2C_FLAG_TCR Transfer complete reload
|
||||
* @arg @ref I2C_FLAG_BERR Bus error
|
||||
* @arg @ref I2C_FLAG_ARLO Arbitration lost
|
||||
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
|
||||
* @arg @ref I2C_FLAG_PECERR PEC error in reception
|
||||
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
|
||||
* @arg @ref I2C_FLAG_ALERT SMBus alert
|
||||
* @arg @ref I2C_FLAG_BUSY Bus busy
|
||||
* @arg @ref I2C_FLAG_DIR Transfer direction (slave mode)
|
||||
*
|
||||
* @retval The new state of __FLAG__ (SET or RESET).
|
||||
*/
|
||||
#define I2C_FLAG_MASK (0x0001FFFFU)
|
||||
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \
|
||||
(__FLAG__)) == (__FLAG__)) ? SET : RESET)
|
||||
|
||||
/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref I2C_FLAG_TXE Transmit data register empty
|
||||
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
|
||||
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
|
||||
* @arg @ref I2C_FLAG_STOPF STOP detection flag
|
||||
* @arg @ref I2C_FLAG_BERR Bus error
|
||||
* @arg @ref I2C_FLAG_ARLO Arbitration lost
|
||||
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
|
||||
* @arg @ref I2C_FLAG_PECERR PEC error in reception
|
||||
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
|
||||
* @arg @ref I2C_FLAG_ALERT SMBus alert
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \
|
||||
((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
|
||||
((__HANDLE__)->Instance->ICR = (__FLAG__)))
|
||||
|
||||
/** @brief Enable the specified I2C peripheral.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
|
||||
|
||||
/** @brief Disable the specified I2C peripheral.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
|
||||
|
||||
/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include I2C HAL Extended module */
|
||||
#include "stm32f7xx_hal_i2c_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup I2C_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions******************************/
|
||||
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
|
||||
pI2C_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions ****************************************************/
|
||||
/******* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
|
||||
uint32_t Timeout);
|
||||
|
||||
/******* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
|
||||
|
||||
/******* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
||||
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
|
||||
uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
|
||||
uint32_t XferOptions);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
|
||||
* @{
|
||||
*/
|
||||
/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
|
||||
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
|
||||
void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State, Mode and Error functions *********************************/
|
||||
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
|
||||
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
|
||||
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup I2C_Private_Constants I2C Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup I2C_Private_Macro I2C Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
|
||||
((MODE) == I2C_ADDRESSINGMODE_10BIT))
|
||||
|
||||
#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
|
||||
((ADDRESS) == I2C_DUALADDRESS_ENABLE))
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \
|
||||
((MASK) == I2C_OA2_MASK01) || \
|
||||
((MASK) == I2C_OA2_MASK02) || \
|
||||
((MASK) == I2C_OA2_MASK03) || \
|
||||
((MASK) == I2C_OA2_MASK04) || \
|
||||
((MASK) == I2C_OA2_MASK05) || \
|
||||
((MASK) == I2C_OA2_MASK06) || \
|
||||
((MASK) == I2C_OA2_MASK07))
|
||||
|
||||
#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
|
||||
((CALL) == I2C_GENERALCALL_ENABLE))
|
||||
|
||||
#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
|
||||
((STRETCH) == I2C_NOSTRETCH_ENABLE))
|
||||
|
||||
#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
|
||||
((SIZE) == I2C_MEMADD_SIZE_16BIT))
|
||||
|
||||
#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \
|
||||
((MODE) == I2C_AUTOEND_MODE) || \
|
||||
((MODE) == I2C_SOFTEND_MODE))
|
||||
|
||||
#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
|
||||
((REQUEST) == I2C_GENERATE_START_READ) || \
|
||||
((REQUEST) == I2C_GENERATE_START_WRITE) || \
|
||||
((REQUEST) == I2C_NO_STARTSTOP))
|
||||
|
||||
#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
|
||||
((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
|
||||
((REQUEST) == I2C_NEXT_FRAME) || \
|
||||
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
|
||||
((REQUEST) == I2C_LAST_FRAME) || \
|
||||
((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \
|
||||
IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
|
||||
|
||||
#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \
|
||||
((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
|
||||
|
||||
#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
|
||||
(uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \
|
||||
I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
|
||||
I2C_CR2_RD_WRN)))
|
||||
|
||||
#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \
|
||||
>> 16U))
|
||||
#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \
|
||||
>> 16U))
|
||||
#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
|
||||
#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
|
||||
#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
|
||||
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
|
||||
|
||||
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \
|
||||
(uint16_t)(0xFF00U))) >> 8U)))
|
||||
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
|
||||
|
||||
#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \
|
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
|
||||
(I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
|
||||
(~I2C_CR2_RD_WRN)) : \
|
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
|
||||
(I2C_CR2_ADD10) | (I2C_CR2_START)) & \
|
||||
(~I2C_CR2_RD_WRN)))
|
||||
|
||||
#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
|
||||
((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
|
||||
#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Functions ---------------------------------------------------------*/
|
||||
/** @defgroup I2C_Private_Functions I2C Private Functions
|
||||
* @{
|
||||
*/
|
||||
/* Private functions are defined in stm32f7xx_hal_i2c.c file */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* STM32F7xx_HAL_I2C_H */
|
||||
@ -0,0 +1,212 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_i2c_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of I2C HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F7xx_HAL_I2C_EX_H
|
||||
#define STM32F7xx_HAL_I2C_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2CEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
|
||||
* @{
|
||||
*/
|
||||
#define I2C_ANALOGFILTER_ENABLE 0x00000000U
|
||||
#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
|
||||
* @{
|
||||
*/
|
||||
#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */
|
||||
#if defined(SYSCFG_PMC_I2C_PB6_FMP)
|
||||
#define I2C_FASTMODEPLUS_PB6 SYSCFG_PMC_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
|
||||
#define I2C_FASTMODEPLUS_PB7 SYSCFG_PMC_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
|
||||
#else
|
||||
#define I2C_FASTMODEPLUS_PB6 (uint32_t)(0x00000004U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB6 not supported */
|
||||
#define I2C_FASTMODEPLUS_PB7 (uint32_t)(0x00000008U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB7 not supported */
|
||||
#endif /* SYSCFG_PMC_I2C_PB6_FMP */
|
||||
#if defined(SYSCFG_PMC_I2C_PB8_FMP)
|
||||
#define I2C_FASTMODEPLUS_PB8 SYSCFG_PMC_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
|
||||
#define I2C_FASTMODEPLUS_PB9 SYSCFG_PMC_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
|
||||
#else
|
||||
#define I2C_FASTMODEPLUS_PB8 (uint32_t)(0x00000010U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB8 not supported */
|
||||
#define I2C_FASTMODEPLUS_PB9 (uint32_t)(0x00000012U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB9 not supported */
|
||||
#endif /* SYSCFG_PMC_I2C_PB8_FMP */
|
||||
#if defined(SYSCFG_PMC_I2C1_FMP)
|
||||
#define I2C_FASTMODEPLUS_I2C1 SYSCFG_PMC_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
|
||||
#else
|
||||
#define I2C_FASTMODEPLUS_I2C1 (uint32_t)(0x00000100U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C1 not supported */
|
||||
#endif /* SYSCFG_PMC_I2C1_FMP */
|
||||
#if defined(SYSCFG_PMC_I2C2_FMP)
|
||||
#define I2C_FASTMODEPLUS_I2C2 SYSCFG_PMC_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
|
||||
#else
|
||||
#define I2C_FASTMODEPLUS_I2C2 (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported */
|
||||
#endif /* SYSCFG_PMC_I2C2_FMP */
|
||||
#if defined(SYSCFG_PMC_I2C3_FMP)
|
||||
#define I2C_FASTMODEPLUS_I2C3 SYSCFG_PMC_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
|
||||
#else
|
||||
#define I2C_FASTMODEPLUS_I2C3 (uint32_t)(0x00000400U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported */
|
||||
#endif /* SYSCFG_PMC_I2C3_FMP */
|
||||
#if defined(SYSCFG_PMC_I2C4_FMP)
|
||||
#define I2C_FASTMODEPLUS_I2C4 SYSCFG_PMC_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */
|
||||
#else
|
||||
#define I2C_FASTMODEPLUS_I2C4 (uint32_t)(0x00000800U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C4 not supported */
|
||||
#endif /* SYSCFG_PMC_I2C4_FMP */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ************************************************/
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#if (defined(SYSCFG_PMC_I2C_PB6_FMP) || defined(SYSCFG_PMC_I2C_PB7_FMP)) || (defined(SYSCFG_PMC_I2C_PB8_FMP) || defined(SYSCFG_PMC_I2C_PB9_FMP)) || (defined(SYSCFG_PMC_I2C1_FMP)) || (defined(SYSCFG_PMC_I2C2_FMP)) || defined(SYSCFG_PMC_I2C3_FMP) || defined(SYSCFG_PMC_I2C4_FMP)
|
||||
|
||||
/** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
|
||||
* @{
|
||||
*/
|
||||
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
|
||||
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* Fast Mode Plus Availability */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
|
||||
((FILTER) == I2C_ANALOGFILTER_DISABLE))
|
||||
|
||||
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
|
||||
|
||||
#if defined(SYSCFG_PMC_I2C4_FMP)
|
||||
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C4) == I2C_FASTMODEPLUS_I2C4))
|
||||
#elif defined(SYSCFG_PMC_I2C3_FMP)
|
||||
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3))
|
||||
#elif defined(SYSCFG_PMC_I2C2_FMP)
|
||||
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2))
|
||||
#elif defined(SYSCFG_PMC_I2C1_FMP)
|
||||
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \
|
||||
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1))
|
||||
#endif /* SYSCFG_PMC_I2C1_FMP && SYSCFG_PMC_I2C2_FMP && SYSCFG_PMC_I2C3_FMP && SYSCFG_PMC_I2C4_FMP */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Functions ---------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
|
||||
* @{
|
||||
*/
|
||||
/* Private functions are defined in stm32f7xx_hal_i2c_ex.c file */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F7xx_HAL_I2C_EX_H */
|
||||
@ -0,0 +1,402 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_pwr.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of PWR HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_PWR_H
|
||||
#define __STM32F7xx_HAL_PWR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWR_Exported_Types PWR Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief PWR PVD configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
|
||||
This parameter can be a value of @ref PWR_PVD_detection_level */
|
||||
|
||||
uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref PWR_PVD_Mode */
|
||||
}PWR_PVDTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup PWR_Exported_Constants PWR Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_PVD_detection_level PWR PVD detection level
|
||||
* @{
|
||||
*/
|
||||
#define PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0
|
||||
#define PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1
|
||||
#define PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2
|
||||
#define PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3
|
||||
#define PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4
|
||||
#define PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5
|
||||
#define PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6
|
||||
#define PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7/* External input analog voltage
|
||||
(Compare internally to VREFINT) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_PVD_Mode PWR PVD Mode
|
||||
* @{
|
||||
*/
|
||||
#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000U) /*!< basic mode is used */
|
||||
#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */
|
||||
#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */
|
||||
#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
||||
#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001U) /*!< Event Mode with Rising edge trigger detection */
|
||||
#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U) /*!< Event Mode with Falling edge trigger detection */
|
||||
#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
|
||||
* @{
|
||||
*/
|
||||
#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000U)
|
||||
#define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPDS
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
|
||||
* @{
|
||||
*/
|
||||
#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U)
|
||||
#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
|
||||
* @{
|
||||
*/
|
||||
#define PWR_STOPENTRY_WFI ((uint8_t)0x01U)
|
||||
#define PWR_STOPENTRY_WFE ((uint8_t)0x02U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale
|
||||
* @{
|
||||
*/
|
||||
#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS
|
||||
#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1
|
||||
#define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR1_VOS_0
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Flag PWR Flag
|
||||
* @{
|
||||
*/
|
||||
#define PWR_FLAG_WU PWR_CSR1_WUIF
|
||||
#define PWR_FLAG_SB PWR_CSR1_SBF
|
||||
#define PWR_FLAG_PVDO PWR_CSR1_PVDO
|
||||
#define PWR_FLAG_BRR PWR_CSR1_BRR
|
||||
#define PWR_FLAG_VOSRDY PWR_CSR1_VOSRDY
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup PWR_Exported_Macro PWR Exported Macro
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief macros configure the main internal regulator output voltage.
|
||||
* @param __REGULATOR__ specifies the regulator output voltage to achieve
|
||||
* a tradeoff between performance and power consumption when the device does
|
||||
* not operate at the maximum frequency (refer to the datasheets for more details).
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
|
||||
* @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
|
||||
* @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
/** @brief Check PWR flag is set or not.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
|
||||
* was received on the internal wakeup line in standby mode (RTC alarm (Alarm A or Alarm B),
|
||||
* RTC Tamper event, RTC TimeStamp event or RTC Wakeup)).
|
||||
* @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
|
||||
* resumed from StandBy mode.
|
||||
* @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
|
||||
* by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
|
||||
* For this reason, this bit is equal to 0 after Standby or reset
|
||||
* until the PVDE bit is set.
|
||||
* @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
|
||||
* when the device wakes up from Standby mode or by a system reset
|
||||
* or power reset.
|
||||
* @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage
|
||||
* scaling output selection is ready.
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clear the PWR's pending flags.
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_FLAG_SB: StandBy flag
|
||||
*/
|
||||
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR1 |= (__FLAG__) << 2)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVD Exti Line 16.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
|
||||
|
||||
/**
|
||||
* @brief Disable the PVD EXTI Line 16.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
|
||||
|
||||
/**
|
||||
* @brief Enable event on PVD Exti Line 16.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
|
||||
|
||||
/**
|
||||
* @brief Disable event on PVD Exti Line 16.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
|
||||
|
||||
/**
|
||||
* @brief Enable the PVD Extended Interrupt Rising Trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVD Extended Interrupt Rising Trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVD Extended Interrupt Falling Trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable the PVD Extended Interrupt Falling Trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
|
||||
|
||||
|
||||
/**
|
||||
* @brief PVD EXTI line configuration: set rising & falling edge trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
|
||||
|
||||
/**
|
||||
* @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
|
||||
|
||||
/**
|
||||
* @brief checks whether the specified PVD Exti interrupt flag is set or not.
|
||||
* @retval EXTI PVD Line Status.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
|
||||
|
||||
/**
|
||||
* @brief Clear the PVD Exti flag.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
|
||||
|
||||
/**
|
||||
* @brief Generates a Software interrupt on PVD EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include PWR HAL Extension module */
|
||||
#include "stm32f7xx_hal_pwr_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup PWR_Exported_Functions PWR Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
void HAL_PWR_DeInit(void);
|
||||
void HAL_PWR_EnableBkUpAccess(void);
|
||||
void HAL_PWR_DisableBkUpAccess(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions **********************************************/
|
||||
/* PVD configuration */
|
||||
void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
|
||||
void HAL_PWR_EnablePVD(void);
|
||||
void HAL_PWR_DisablePVD(void);
|
||||
|
||||
/* WakeUp pins configuration */
|
||||
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
|
||||
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
|
||||
|
||||
/* Low Power modes entry */
|
||||
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
|
||||
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
|
||||
void HAL_PWR_EnterSTANDBYMode(void);
|
||||
|
||||
/* Power PVD IRQ Handler */
|
||||
void HAL_PWR_PVD_IRQHandler(void);
|
||||
void HAL_PWR_PVDCallback(void);
|
||||
|
||||
/* Cortex System Control functions *******************************************/
|
||||
void HAL_PWR_EnableSleepOnExit(void);
|
||||
void HAL_PWR_DisableSleepOnExit(void);
|
||||
void HAL_PWR_EnableSEVOnPend(void);
|
||||
void HAL_PWR_DisableSEVOnPend(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup PWR_Private_Constants PWR Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
|
||||
* @{
|
||||
*/
|
||||
#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_IM16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup PWR_Private_Macros PWR Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
|
||||
* @{
|
||||
*/
|
||||
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
|
||||
((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
|
||||
((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
|
||||
((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
|
||||
#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
|
||||
((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
|
||||
((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
|
||||
((MODE) == PWR_PVD_MODE_NORMAL))
|
||||
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
|
||||
((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
|
||||
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
|
||||
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
|
||||
#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
|
||||
((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
|
||||
((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __STM32F7xx_HAL_PWR_H */
|
||||
|
||||
@ -0,0 +1,260 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_pwr_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of PWR HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F7xx_HAL_PWR_EX_H
|
||||
#define __STM32F7xx_HAL_PWR_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWREx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup PWREx_WakeUp_Pins PWREx Wake Up Pins
|
||||
* @{
|
||||
*/
|
||||
#define PWR_WAKEUP_PIN1 PWR_CSR2_EWUP1
|
||||
#define PWR_WAKEUP_PIN2 PWR_CSR2_EWUP2
|
||||
#define PWR_WAKEUP_PIN3 PWR_CSR2_EWUP3
|
||||
#define PWR_WAKEUP_PIN4 PWR_CSR2_EWUP4
|
||||
#define PWR_WAKEUP_PIN5 PWR_CSR2_EWUP5
|
||||
#define PWR_WAKEUP_PIN6 PWR_CSR2_EWUP6
|
||||
#define PWR_WAKEUP_PIN1_HIGH PWR_CSR2_EWUP1
|
||||
#define PWR_WAKEUP_PIN2_HIGH PWR_CSR2_EWUP2
|
||||
#define PWR_WAKEUP_PIN3_HIGH PWR_CSR2_EWUP3
|
||||
#define PWR_WAKEUP_PIN4_HIGH PWR_CSR2_EWUP4
|
||||
#define PWR_WAKEUP_PIN5_HIGH PWR_CSR2_EWUP5
|
||||
#define PWR_WAKEUP_PIN6_HIGH PWR_CSR2_EWUP6
|
||||
#define PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR2_WUPP1<<6) | PWR_CSR2_EWUP1)
|
||||
#define PWR_WAKEUP_PIN2_LOW (uint32_t)((PWR_CR2_WUPP2<<6) | PWR_CSR2_EWUP2)
|
||||
#define PWR_WAKEUP_PIN3_LOW (uint32_t)((PWR_CR2_WUPP3<<6) | PWR_CSR2_EWUP3)
|
||||
#define PWR_WAKEUP_PIN4_LOW (uint32_t)((PWR_CR2_WUPP4<<6) | PWR_CSR2_EWUP4)
|
||||
#define PWR_WAKEUP_PIN5_LOW (uint32_t)((PWR_CR2_WUPP5<<6) | PWR_CSR2_EWUP5)
|
||||
#define PWR_WAKEUP_PIN6_LOW (uint32_t)((PWR_CR2_WUPP6<<6) | PWR_CSR2_EWUP6)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_Regulator_state_in_UnderDrive_mode PWREx Regulator state in UnderDrive mode
|
||||
* @{
|
||||
*/
|
||||
#define PWR_MAINREGULATOR_UNDERDRIVE_ON PWR_CR1_MRUDS
|
||||
#define PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON ((uint32_t)(PWR_CR1_LPDS | PWR_CR1_LPUDS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_Over_Under_Drive_Flag PWREx Over Under Drive Flag
|
||||
* @{
|
||||
*/
|
||||
#define PWR_FLAG_ODRDY PWR_CSR1_ODRDY
|
||||
#define PWR_FLAG_ODSWRDY PWR_CSR1_ODSWRDY
|
||||
#define PWR_FLAG_UDRDY PWR_CSR1_UDRDY
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_Wakeup_Pins_Flag PWREx Wake Up Pin Flags
|
||||
* @{
|
||||
*/
|
||||
#define PWR_WAKEUP_PIN_FLAG1 PWR_CSR2_WUPF1
|
||||
#define PWR_WAKEUP_PIN_FLAG2 PWR_CSR2_WUPF2
|
||||
#define PWR_WAKEUP_PIN_FLAG3 PWR_CSR2_WUPF3
|
||||
#define PWR_WAKEUP_PIN_FLAG4 PWR_CSR2_WUPF4
|
||||
#define PWR_WAKEUP_PIN_FLAG5 PWR_CSR2_WUPF5
|
||||
#define PWR_WAKEUP_PIN_FLAG6 PWR_CSR2_WUPF6
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup PWREx_Exported_Macro PWREx Exported Macro
|
||||
* @{
|
||||
*/
|
||||
/** @brief Macros to enable or disable the Over drive mode.
|
||||
*/
|
||||
#define __HAL_PWR_OVERDRIVE_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_ODEN)
|
||||
#define __HAL_PWR_OVERDRIVE_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODEN))
|
||||
|
||||
/** @brief Macros to enable or disable the Over drive switching.
|
||||
*/
|
||||
#define __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_ODSWEN)
|
||||
#define __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODSWEN))
|
||||
|
||||
/** @brief Macros to enable or disable the Under drive mode.
|
||||
* @note This mode is enabled only with STOP low power mode.
|
||||
* In this mode, the 1.2V domain is preserved in reduced leakage mode. This
|
||||
* mode is only available when the main regulator or the low power regulator
|
||||
* is in low voltage mode.
|
||||
* @note If the Under-drive mode was enabled, it is automatically disabled after
|
||||
* exiting Stop mode.
|
||||
* When the voltage regulator operates in Under-drive mode, an additional
|
||||
* startup delay is induced when waking up from Stop mode.
|
||||
*/
|
||||
#define __HAL_PWR_UNDERDRIVE_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_UDEN)
|
||||
#define __HAL_PWR_UNDERDRIVE_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_UDEN))
|
||||
|
||||
/** @brief Check PWR flag is set or not.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode
|
||||
* is ready
|
||||
* @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode
|
||||
* switching is ready
|
||||
* @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode
|
||||
* is enabled in Stop mode
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_PWR_GET_ODRUDR_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clear the Under-Drive Ready flag.
|
||||
*/
|
||||
#define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR1 |= (PWR_FLAG_UDRDY | PWR_CSR1_EIWUP))
|
||||
|
||||
/** @brief Check Wake Up flag is set or not.
|
||||
* @param __WUFLAG__ specifies the Wake Up flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_WAKEUP_PIN_FLAG1: Wakeup Pin Flag for PA0
|
||||
* @arg PWR_WAKEUP_PIN_FLAG2: Wakeup Pin Flag for PA2
|
||||
* @arg PWR_WAKEUP_PIN_FLAG3: Wakeup Pin Flag for PC1
|
||||
* @arg PWR_WAKEUP_PIN_FLAG4: Wakeup Pin Flag for PC13
|
||||
* @arg PWR_WAKEUP_PIN_FLAG5: Wakeup Pin Flag for PI8
|
||||
* @arg PWR_WAKEUP_PIN_FLAG6: Wakeup Pin Flag for PI11
|
||||
*/
|
||||
#define __HAL_PWR_GET_WAKEUP_FLAG(__WUFLAG__) (PWR->CSR2 & (__WUFLAG__))
|
||||
|
||||
/** @brief Clear the WakeUp pins flags.
|
||||
* @param __WUFLAG__ specifies the Wake Up pin flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_WAKEUP_PIN_FLAG1: Wakeup Pin Flag for PA0
|
||||
* @arg PWR_WAKEUP_PIN_FLAG2: Wakeup Pin Flag for PA2
|
||||
* @arg PWR_WAKEUP_PIN_FLAG3: Wakeup Pin Flag for PC1
|
||||
* @arg PWR_WAKEUP_PIN_FLAG4: Wakeup Pin Flag for PC13
|
||||
* @arg PWR_WAKEUP_PIN_FLAG5: Wakeup Pin Flag for PI8
|
||||
* @arg PWR_WAKEUP_PIN_FLAG6: Wakeup Pin Flag for PI11
|
||||
*/
|
||||
#define __HAL_PWR_CLEAR_WAKEUP_FLAG(__WUFLAG__) (PWR->CR2 |= (__WUFLAG__))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWREx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
uint32_t HAL_PWREx_GetVoltageRange(void);
|
||||
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
|
||||
|
||||
void HAL_PWREx_EnableFlashPowerDown(void);
|
||||
void HAL_PWREx_DisableFlashPowerDown(void);
|
||||
HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);
|
||||
HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);
|
||||
|
||||
void HAL_PWREx_EnableMainRegulatorLowVoltage(void);
|
||||
void HAL_PWREx_DisableMainRegulatorLowVoltage(void);
|
||||
void HAL_PWREx_EnableLowRegulatorLowVoltage(void);
|
||||
void HAL_PWREx_DisableLowRegulatorLowVoltage(void);
|
||||
|
||||
HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void);
|
||||
HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void);
|
||||
HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup PWREx_Private_Macros PWREx Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters
|
||||
* @{
|
||||
*/
|
||||
#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || \
|
||||
((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON))
|
||||
#define IS_PWR_WAKEUP_PIN(__PIN__) (((__PIN__) == PWR_WAKEUP_PIN1) || \
|
||||
((__PIN__) == PWR_WAKEUP_PIN2) || \
|
||||
((__PIN__) == PWR_WAKEUP_PIN3) || \
|
||||
((__PIN__) == PWR_WAKEUP_PIN4) || \
|
||||
((__PIN__) == PWR_WAKEUP_PIN5) || \
|
||||
((__PIN__) == PWR_WAKEUP_PIN6) || \
|
||||
((__PIN__) == PWR_WAKEUP_PIN1_HIGH) || \
|
||||
((__PIN__) == PWR_WAKEUP_PIN2_HIGH) || \
|
||||
((__PIN__) == PWR_WAKEUP_PIN3_HIGH) || \
|
||||
((__PIN__) == PWR_WAKEUP_PIN4_HIGH) || \
|
||||
((__PIN__) == PWR_WAKEUP_PIN5_HIGH) || \
|
||||
((__PIN__) == PWR_WAKEUP_PIN6_HIGH) || \
|
||||
((__PIN__) == PWR_WAKEUP_PIN1_LOW) || \
|
||||
((__PIN__) == PWR_WAKEUP_PIN2_LOW) || \
|
||||
((__PIN__) == PWR_WAKEUP_PIN3_LOW) || \
|
||||
((__PIN__) == PWR_WAKEUP_PIN4_LOW) || \
|
||||
((__PIN__) == PWR_WAKEUP_PIN5_LOW) || \
|
||||
((__PIN__) == PWR_WAKEUP_PIN6_LOW))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __STM32F7xx_HAL_PWR_EX_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,358 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_tim_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of TIM HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F7xx_HAL_TIM_EX_H
|
||||
#define STM32F7xx_HAL_TIM_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief TIM Hall sensor Configuration Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
|
||||
|
||||
uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
|
||||
|
||||
uint32_t IC1Filter; /*!< Specifies the input capture filter.
|
||||
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
|
||||
|
||||
uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
|
||||
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
|
||||
} TIM_HallSensor_InitTypeDef;
|
||||
#if defined(TIM_BREAK_INPUT_SUPPORT)
|
||||
|
||||
/**
|
||||
* @brief TIM Break/Break2 input configuration
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Source; /*!< Specifies the source of the timer break input.
|
||||
This parameter can be a value of @ref TIMEx_Break_Input_Source */
|
||||
uint32_t Enable; /*!< Specifies whether or not the break input source is enabled.
|
||||
This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */
|
||||
uint32_t Polarity; /*!< Specifies the break input source polarity.
|
||||
This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity
|
||||
Not relevant when analog watchdog output of the DFSDM1 used as break input source */
|
||||
} TIMEx_BreakInputConfigTypeDef;
|
||||
|
||||
#endif /* TIM_BREAK_INPUT_SUPPORT */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of exported types -----------------------------------------------------*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup TIMEx_Remap TIM Extended Remapping
|
||||
* @{
|
||||
*/
|
||||
#define TIM_TIM2_TIM8_TRGO (0x00000000U)
|
||||
#define TIM_TIM2_ETH_PTP (0x00000400U)
|
||||
#define TIM_TIM2_USBFS_SOF (0x00000800U)
|
||||
#define TIM_TIM2_USBHS_SOF (0x00000C00U)
|
||||
#define TIM_TIM5_GPIO (0x00000000U)
|
||||
#define TIM_TIM5_LSI (0x00000040U)
|
||||
#define TIM_TIM5_LSE (0x00000080U)
|
||||
#define TIM_TIM5_RTC (0x000000C0U)
|
||||
#define TIM_TIM11_GPIO (0x00000000U)
|
||||
#define TIM_TIM11_SPDIFRX (0x00000001U)
|
||||
#define TIM_TIM11_HSE (0x00000002U)
|
||||
#define TIM_TIM11_MCO1 (0x00000003U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#if defined(TIM_BREAK_INPUT_SUPPORT)
|
||||
|
||||
/** @defgroup TIMEx_Break_Input TIM Extended Break input
|
||||
* @{
|
||||
*/
|
||||
#define TIM_BREAKINPUT_BRK 0x00000001U /*!< Timer break input */
|
||||
#define TIM_BREAKINPUT_BRK2 0x00000002U /*!< Timer break2 input */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source
|
||||
* @{
|
||||
*/
|
||||
#define TIM_BREAKINPUTSOURCE_BKIN (0x00000001U) /* !< An external source (GPIO) is connected to the BKIN pin */
|
||||
#define TIM_BREAKINPUTSOURCE_DFSDM1 (0x00000008U) /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling
|
||||
* @{
|
||||
*/
|
||||
#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /*!< Break input source is disabled */
|
||||
#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /*!< Break input source is enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity
|
||||
* @{
|
||||
*/
|
||||
#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /*!< Break input source is active low */
|
||||
#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /*!< Break input source is active_high */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* TIM_BREAK_INPUT_SUPPORT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of exported constants -------------------------------------------------*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of exported macro -----------------------------------------------------*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_TIM_REMAP(__TIM_REMAP__) (((__TIM_REMAP__) == TIM_TIM2_TIM8_TRGO)||\
|
||||
((__TIM_REMAP__) == TIM_TIM2_ETH_PTP) ||\
|
||||
((__TIM_REMAP__) == TIM_TIM2_USBFS_SOF)||\
|
||||
((__TIM_REMAP__) == TIM_TIM2_USBHS_SOF)||\
|
||||
((__TIM_REMAP__) == TIM_TIM5_GPIO) ||\
|
||||
((__TIM_REMAP__) == TIM_TIM5_LSI) ||\
|
||||
((__TIM_REMAP__) == TIM_TIM5_LSE) ||\
|
||||
((__TIM_REMAP__) == TIM_TIM5_RTC) ||\
|
||||
((__TIM_REMAP__) == TIM_TIM11_GPIO) ||\
|
||||
((__TIM_REMAP__) == TIM_TIM11_SPDIFRX) ||\
|
||||
((__TIM_REMAP__) == TIM_TIM11_HSE) ||\
|
||||
((__TIM_REMAP__) == TIM_TIM11_MCO1))
|
||||
#if defined(TIM_BREAK_INPUT_SUPPORT)
|
||||
|
||||
#define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \
|
||||
((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
|
||||
|
||||
#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \
|
||||
((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM))
|
||||
|
||||
#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \
|
||||
((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
|
||||
|
||||
#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \
|
||||
((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
|
||||
#endif /* TIM_BREAK_INPUT_SUPPORT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of private macro ------------------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
|
||||
* @brief Timer Hall Sensor functions
|
||||
* @{
|
||||
*/
|
||||
/* Timer Hall Sensor functions **********************************************/
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
|
||||
|
||||
void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
|
||||
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
|
||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
|
||||
* @brief Timer Complementary Output Compare functions
|
||||
* @{
|
||||
*/
|
||||
/* Timer Complementary Output Compare functions *****************************/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
|
||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
|
||||
* @brief Timer Complementary PWM functions
|
||||
* @{
|
||||
*/
|
||||
/* Timer Complementary PWM functions ****************************************/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
|
||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
|
||||
* @brief Timer Complementary One Pulse functions
|
||||
* @{
|
||||
*/
|
||||
/* Timer Complementary One Pulse functions **********************************/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
|
||||
* @brief Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
/* Extended Control functions ************************************************/
|
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
|
||||
uint32_t CommutationSource);
|
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
|
||||
uint32_t CommutationSource);
|
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
|
||||
uint32_t CommutationSource);
|
||||
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
|
||||
TIM_MasterConfigTypeDef *sMasterConfig);
|
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
|
||||
TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
|
||||
#if defined(TIM_BREAK_INPUT_SUPPORT)
|
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput,
|
||||
TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
|
||||
#endif /* TIM_BREAK_INPUT_SUPPORT */
|
||||
HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
|
||||
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
|
||||
* @brief Extended Callbacks functions
|
||||
* @{
|
||||
*/
|
||||
/* Extended Callback **********************************************************/
|
||||
void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
|
||||
* @brief Extended Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
/* Extended Peripheral State functions ***************************************/
|
||||
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
|
||||
HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of exported functions -------------------------------------------------*/
|
||||
|
||||
/* Private functions----------------------------------------------------------*/
|
||||
/** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions
|
||||
* @{
|
||||
*/
|
||||
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
|
||||
void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of private functions --------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* STM32F7xx_HAL_TIM_EX_H */
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,428 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_uart_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of UART HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F7xx_HAL_UART_EX_H
|
||||
#define STM32F7xx_HAL_UART_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup UARTEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup UARTEx_Exported_Types UARTEx Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(USART_CR1_UESM)
|
||||
/**
|
||||
* @brief UART wake up from stop mode parameters
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t WakeUpEvent; /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF).
|
||||
This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
|
||||
If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
|
||||
be filled up. */
|
||||
|
||||
uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long.
|
||||
This parameter can be a value of @ref UARTEx_WakeUp_Address_Length. */
|
||||
|
||||
uint8_t Address; /*!< UART/USART node address (7-bit long max). */
|
||||
} UART_WakeUpTypeDef;
|
||||
|
||||
#endif /* USART_CR1_UESM */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup UARTEx_Word_Length UARTEx Word Length
|
||||
* @{
|
||||
*/
|
||||
#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */
|
||||
#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */
|
||||
#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length
|
||||
* @{
|
||||
*/
|
||||
#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */
|
||||
#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup UARTEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup UARTEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
|
||||
uint32_t DeassertionTime);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup UARTEx_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(USART_CR1_UESM)
|
||||
void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
|
||||
|
||||
#endif /* USART_CR1_UESM */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup UARTEx_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions **********************************************/
|
||||
#if defined(USART_CR1_UESM)
|
||||
HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
|
||||
HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
|
||||
HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
|
||||
|
||||
#endif/* USART_CR1_UESM */
|
||||
#if defined(USART_CR3_UCESM)
|
||||
HAL_StatusTypeDef HAL_UARTEx_EnableClockStopMode(UART_HandleTypeDef *huart);
|
||||
HAL_StatusTypeDef HAL_UARTEx_DisableClockStopMode(UART_HandleTypeDef *huart);
|
||||
|
||||
#endif /* USART_CR3_UCESM */
|
||||
HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
|
||||
|
||||
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup UARTEx_Private_Macros UARTEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Report the UART clock source.
|
||||
* @param __HANDLE__ specifies the UART Handle.
|
||||
* @param __CLOCKSOURCE__ output variable.
|
||||
* @retval UART clocking source, written in __CLOCKSOURCE__.
|
||||
*/
|
||||
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK2: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART2) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART2_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART2CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART2CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART3) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART3_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART3CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART3CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == UART4) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_UART4_SOURCE()) \
|
||||
{ \
|
||||
case RCC_UART4CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_UART4CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_UART4CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_UART4CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Instance == UART5) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_UART5_SOURCE()) \
|
||||
{ \
|
||||
case RCC_UART5CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_UART5CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_UART5CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_UART5CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if((__HANDLE__)->Instance == USART6) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART6_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART6CLKSOURCE_PCLK2: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
|
||||
break; \
|
||||
case RCC_USART6CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART6CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART6CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Instance == UART7) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_UART7_SOURCE()) \
|
||||
{ \
|
||||
case RCC_UART7CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_UART7CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_UART7CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_UART7CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Instance == UART8) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_UART8_SOURCE()) \
|
||||
{ \
|
||||
case RCC_UART8CLKSOURCE_PCLK1: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
|
||||
break; \
|
||||
case RCC_UART8CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_UART8CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_UART8CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0U)
|
||||
|
||||
/** @brief Report the UART mask to apply to retrieve the received data
|
||||
* according to the word length and to the parity bits activation.
|
||||
* @note If PCE = 1, the parity bit is not included in the data extracted
|
||||
* by the reception API().
|
||||
* This masking operation is not carried out in the case of
|
||||
* DMA transfers.
|
||||
* @param __HANDLE__ specifies the UART Handle.
|
||||
* @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.
|
||||
*/
|
||||
#define UART_MASK_COMPUTATION(__HANDLE__) \
|
||||
do { \
|
||||
if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x01FFU ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FFU ; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FFU ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x007FU ; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x007FU ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x003FU ; \
|
||||
} \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x0000U; \
|
||||
} \
|
||||
} while(0U)
|
||||
|
||||
/**
|
||||
* @brief Ensure that UART frame length is valid.
|
||||
* @param __LENGTH__ UART frame length.
|
||||
* @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
|
||||
*/
|
||||
#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
|
||||
((__LENGTH__) == UART_WORDLENGTH_8B) || \
|
||||
((__LENGTH__) == UART_WORDLENGTH_9B))
|
||||
|
||||
/**
|
||||
* @brief Ensure that UART wake-up address length is valid.
|
||||
* @param __ADDRESS__ UART wake-up address length.
|
||||
* @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
|
||||
*/
|
||||
#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
|
||||
((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F7xx_HAL_UART_EX_H */
|
||||
|
||||
@ -0,0 +1,6 @@
|
||||
This software component is provided to you as part of a software package and
|
||||
applicable license terms are in the Package_license file. If you received this
|
||||
software component outside of a package or without applicable license terms,
|
||||
the terms of the BSD-3-Clause license shall apply.
|
||||
You may obtain a copy of the BSD-3-Clause at:
|
||||
https://opensource.org/licenses/BSD-3-Clause
|
||||
@ -0,0 +1 @@
|
||||
License.md file kept for legacy purpose
|
||||
@ -0,0 +1,619 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal.c
|
||||
* @author MCD Application Team
|
||||
* @brief HAL module driver.
|
||||
* This is the common part of the HAL initialization
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
The common HAL driver contains a set of generic and common APIs that can be
|
||||
used by the PPP peripheral drivers and the user to start using the HAL.
|
||||
[..]
|
||||
The HAL contains two APIs' categories:
|
||||
(+) Common HAL APIs
|
||||
(+) Services HAL APIs
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL HAL
|
||||
* @brief HAL module driver.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @addtogroup HAL_Private_Constants
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief STM32F7xx HAL Driver version number V1.2.10
|
||||
*/
|
||||
#define __STM32F7xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
|
||||
#define __STM32F7xx_HAL_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
|
||||
#define __STM32F7xx_HAL_VERSION_SUB2 (0x0A) /*!< [15:8] sub2 version */
|
||||
#define __STM32F7xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32F7xx_HAL_VERSION ((__STM32F7xx_HAL_VERSION_MAIN << 24)\
|
||||
|(__STM32F7xx_HAL_VERSION_SUB1 << 16)\
|
||||
|(__STM32F7xx_HAL_VERSION_SUB2 << 8 )\
|
||||
|(__STM32F7xx_HAL_VERSION_RC))
|
||||
|
||||
#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Exported variables ---------------------------------------------------------*/
|
||||
/** @addtogroup HAL_Exported_Variables
|
||||
* @{
|
||||
*/
|
||||
__IO uint32_t uwTick;
|
||||
uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
|
||||
HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup HAL_Exported_Functions HAL Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
|
||||
* @brief Initialization and de-initialization functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and Configuration functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Initializes the Flash interface the NVIC allocation and initial clock
|
||||
configuration. It initializes the systick also when timeout is needed
|
||||
and the backup domain when enabled.
|
||||
(+) De-Initializes common part of the HAL.
|
||||
(+) Configure the time base source to have 1ms time base with a dedicated
|
||||
Tick interrupt priority.
|
||||
(++) SysTick timer is used by default as source of time base, but user
|
||||
can eventually implement his proper time base source (a general purpose
|
||||
timer for example or other time source), keeping in mind that Time base
|
||||
duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
|
||||
handled in milliseconds basis.
|
||||
(++) Time base configuration function (HAL_InitTick ()) is called automatically
|
||||
at the beginning of the program after reset by HAL_Init() or at any time
|
||||
when clock is configured, by HAL_RCC_ClockConfig().
|
||||
(++) Source of time base is configured to generate interrupts at regular
|
||||
time intervals. Care must be taken if HAL_Delay() is called from a
|
||||
peripheral ISR process, the Tick interrupt line must have higher priority
|
||||
(numerically lower) than the peripheral interrupt. Otherwise the caller
|
||||
ISR process will be blocked.
|
||||
(++) functions affecting time base configurations are declared as __weak
|
||||
to make override possible in case of other implementations in user file.
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function is used to initialize the HAL Library; it must be the first
|
||||
* instruction to be executed in the main program (before to call any other
|
||||
* HAL function), it performs the following:
|
||||
* Configure the Flash prefetch, and instruction cache through ART accelerator.
|
||||
* Configures the SysTick to generate an interrupt each 1 millisecond,
|
||||
* which is clocked by the HSI (at this stage, the clock is not yet
|
||||
* configured and thus the system is running from the internal HSI at 16 MHz).
|
||||
* Set NVIC Group Priority to 4.
|
||||
* Calls the HAL_MspInit() callback function defined in user file
|
||||
* "stm32f7xx_hal_msp.c" to do the global low level hardware initialization
|
||||
*
|
||||
* @note SysTick is used as time base for the HAL_Delay() function, the application
|
||||
* need to ensure that the SysTick time base is always set to 1 millisecond
|
||||
* to have correct HAL operation.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_Init(void)
|
||||
{
|
||||
/* Configure Instruction cache through ART accelerator */
|
||||
#if (ART_ACCLERATOR_ENABLE != 0)
|
||||
__HAL_FLASH_ART_ENABLE();
|
||||
#endif /* ART_ACCLERATOR_ENABLE */
|
||||
|
||||
/* Configure Flash prefetch */
|
||||
#if (PREFETCH_ENABLE != 0U)
|
||||
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
|
||||
#endif /* PREFETCH_ENABLE */
|
||||
|
||||
/* Set Interrupt Group Priority */
|
||||
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
||||
|
||||
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
|
||||
HAL_InitTick(TICK_INT_PRIORITY);
|
||||
|
||||
/* Init the low level hardware */
|
||||
HAL_MspInit();
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function de-Initializes common part of the HAL and stops the systick.
|
||||
* This function is optional.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DeInit(void)
|
||||
{
|
||||
/* Reset of all peripherals */
|
||||
__HAL_RCC_APB1_FORCE_RESET();
|
||||
__HAL_RCC_APB1_RELEASE_RESET();
|
||||
|
||||
__HAL_RCC_APB2_FORCE_RESET();
|
||||
__HAL_RCC_APB2_RELEASE_RESET();
|
||||
|
||||
__HAL_RCC_AHB1_FORCE_RESET();
|
||||
__HAL_RCC_AHB1_RELEASE_RESET();
|
||||
|
||||
__HAL_RCC_AHB2_FORCE_RESET();
|
||||
__HAL_RCC_AHB2_RELEASE_RESET();
|
||||
|
||||
__HAL_RCC_AHB3_FORCE_RESET();
|
||||
__HAL_RCC_AHB3_RELEASE_RESET();
|
||||
|
||||
/* De-Init the low level hardware */
|
||||
HAL_MspDeInit();
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize the MSP.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_MspInit(void)
|
||||
{
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_MspInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the MSP.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_MspDeInit(void)
|
||||
{
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_MspDeInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function configures the source of the time base.
|
||||
* The time source is configured to have 1ms time base with a dedicated
|
||||
* Tick interrupt priority.
|
||||
* @note This function is called automatically at the beginning of program after
|
||||
* reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
|
||||
* @note In the default implementation, SysTick timer is the source of time base.
|
||||
* It is used to generate interrupts at regular time intervals.
|
||||
* Care must be taken if HAL_Delay() is called from a peripheral ISR process,
|
||||
* The SysTick interrupt must have higher priority (numerically lower)
|
||||
* than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
|
||||
* The function is declared as __weak to be overwritten in case of other
|
||||
* implementation in user file.
|
||||
* @param TickPriority Tick interrupt priority.
|
||||
* @retval HAL status
|
||||
*/
|
||||
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
||||
{
|
||||
/* Configure the SysTick to have interrupt in 1ms time basis*/
|
||||
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Configure the SysTick IRQ priority */
|
||||
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
||||
{
|
||||
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
|
||||
uwTickPrio = TickPriority;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
|
||||
* @brief HAL Control functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### HAL Control functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Provide a tick value in millisecond
|
||||
(+) Provide a blocking delay in millisecond
|
||||
(+) Suspend the time base source interrupt
|
||||
(+) Resume the time base source interrupt
|
||||
(+) Get the HAL API driver version
|
||||
(+) Get the device identifier
|
||||
(+) Get the device revision identifier
|
||||
(+) Enable/Disable Debug module during SLEEP mode
|
||||
(+) Enable/Disable Debug module during STOP mode
|
||||
(+) Enable/Disable Debug module during STANDBY mode
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function is called to increment a global variable "uwTick"
|
||||
* used as application time base.
|
||||
* @note In the default implementation, this variable is incremented each 1ms
|
||||
* in SysTick ISR.
|
||||
* @note This function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_IncTick(void)
|
||||
{
|
||||
uwTick += uwTickFreq;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Provides a tick value in millisecond.
|
||||
* @note This function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @retval tick value
|
||||
*/
|
||||
__weak uint32_t HAL_GetTick(void)
|
||||
{
|
||||
return uwTick;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function returns a tick priority.
|
||||
* @retval tick priority
|
||||
*/
|
||||
uint32_t HAL_GetTickPrio(void)
|
||||
{
|
||||
return uwTickPrio;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set new tick Freq.
|
||||
* @retval Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
HAL_TickFreqTypeDef prevTickFreq;
|
||||
|
||||
assert_param(IS_TICKFREQ(Freq));
|
||||
|
||||
if (uwTickFreq != Freq)
|
||||
{
|
||||
/* Back up uwTickFreq frequency */
|
||||
prevTickFreq = uwTickFreq;
|
||||
|
||||
/* Update uwTickFreq global variable used by HAL_InitTick() */
|
||||
uwTickFreq = Freq;
|
||||
|
||||
/* Apply the new tick Freq */
|
||||
status = HAL_InitTick(uwTickPrio);
|
||||
|
||||
if (status != HAL_OK)
|
||||
{
|
||||
/* Restore previous tick frequency */
|
||||
uwTickFreq = prevTickFreq;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return tick frequency.
|
||||
* @retval tick period in Hz
|
||||
*/
|
||||
HAL_TickFreqTypeDef HAL_GetTickFreq(void)
|
||||
{
|
||||
return uwTickFreq;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function provides minimum delay (in milliseconds) based
|
||||
* on variable incremented.
|
||||
* @note In the default implementation , SysTick timer is the source of time base.
|
||||
* It is used to generate interrupts at regular time intervals where uwTick
|
||||
* is incremented.
|
||||
* @note This function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @param Delay specifies the delay time length, in milliseconds.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_Delay(uint32_t Delay)
|
||||
{
|
||||
uint32_t tickstart = HAL_GetTick();
|
||||
uint32_t wait = Delay;
|
||||
|
||||
/* Add a freq to guarantee minimum wait */
|
||||
if (wait < HAL_MAX_DELAY)
|
||||
{
|
||||
wait += (uint32_t)(uwTickFreq);
|
||||
}
|
||||
|
||||
while ((HAL_GetTick() - tickstart) < wait)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Suspend Tick increment.
|
||||
* @note In the default implementation , SysTick timer is the source of time base. It is
|
||||
* used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
|
||||
* is called, the SysTick interrupt will be disabled and so Tick increment
|
||||
* is suspended.
|
||||
* @note This function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_SuspendTick(void)
|
||||
{
|
||||
/* Disable SysTick Interrupt */
|
||||
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resume Tick increment.
|
||||
* @note In the default implementation , SysTick timer is the source of time base. It is
|
||||
* used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
|
||||
* is called, the SysTick interrupt will be enabled and so Tick increment
|
||||
* is resumed.
|
||||
* @note This function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_ResumeTick(void)
|
||||
{
|
||||
/* Enable SysTick Interrupt */
|
||||
SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the HAL revision
|
||||
* @retval version : 0xXYZR (8bits for each decimal, R for RC)
|
||||
*/
|
||||
uint32_t HAL_GetHalVersion(void)
|
||||
{
|
||||
return __STM32F7xx_HAL_VERSION;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the device revision identifier.
|
||||
* @retval Device revision identifier
|
||||
*/
|
||||
uint32_t HAL_GetREVID(void)
|
||||
{
|
||||
return((DBGMCU->IDCODE) >> 16U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the device identifier.
|
||||
* @retval Device identifier
|
||||
*/
|
||||
uint32_t HAL_GetDEVID(void)
|
||||
{
|
||||
return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns first word of the unique device identifier (UID based on 96 bits)
|
||||
* @retval Device identifier
|
||||
*/
|
||||
uint32_t HAL_GetUIDw0(void)
|
||||
{
|
||||
return(READ_REG(*((uint32_t *)UID_BASE)));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns second word of the unique device identifier (UID based on 96 bits)
|
||||
* @retval Device identifier
|
||||
*/
|
||||
uint32_t HAL_GetUIDw1(void)
|
||||
{
|
||||
return(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns third word of the unique device identifier (UID based on 96 bits)
|
||||
* @retval Device identifier
|
||||
*/
|
||||
uint32_t HAL_GetUIDw2(void)
|
||||
{
|
||||
return(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the Debug Module during SLEEP mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_EnableDBGSleepMode(void)
|
||||
{
|
||||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the Debug Module during SLEEP mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_DisableDBGSleepMode(void)
|
||||
{
|
||||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the Debug Module during STOP mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_EnableDBGStopMode(void)
|
||||
{
|
||||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the Debug Module during STOP mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_DisableDBGStopMode(void)
|
||||
{
|
||||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the Debug Module during STANDBY mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_EnableDBGStandbyMode(void)
|
||||
{
|
||||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the Debug Module during STANDBY mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_DisableDBGStandbyMode(void)
|
||||
{
|
||||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the I/O Compensation Cell.
|
||||
* @note The I/O compensation cell can be used only when the device supply
|
||||
* voltage ranges from 2.4 to 3.6 V.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_EnableCompensationCell(void)
|
||||
{
|
||||
SYSCFG->CMPCR |= SYSCFG_CMPCR_CMP_PD;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Power-down the I/O Compensation Cell.
|
||||
* @note The I/O compensation cell can be used only when the device supply
|
||||
* voltage ranges from 2.4 to 3.6 V.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DisableCompensationCell(void)
|
||||
{
|
||||
SYSCFG->CMPCR &= (uint32_t)~((uint32_t)SYSCFG_CMPCR_CMP_PD);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the FMC Memory Mapping Swapping.
|
||||
*
|
||||
* @note SDRAM is accessible at 0x60000000
|
||||
* and NOR/RAM is accessible at 0xC0000000
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_EnableFMCMemorySwapping(void)
|
||||
{
|
||||
SYSCFG->MEMRMP |= SYSCFG_MEMRMP_SWP_FMC_0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the FMC Memory Mapping Swapping
|
||||
*
|
||||
* @note SDRAM is accessible at 0xC0000000 (default mapping)
|
||||
* and NOR/RAM is accessible at 0x60000000 (default mapping)
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DisableFMCMemorySwapping(void)
|
||||
{
|
||||
SYSCFG->MEMRMP &= (uint32_t)~((uint32_t)SYSCFG_MEMRMP_SWP_FMC);
|
||||
}
|
||||
|
||||
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
|
||||
/**
|
||||
* @brief Enable the Internal FLASH Bank Swapping.
|
||||
*
|
||||
* @note This function can be used only for STM32F77xx/STM32F76xx devices.
|
||||
*
|
||||
* @note Flash Bank2 mapped at 0x08000000 (AXI) (aliased at 0x00200000 (TCM))
|
||||
* and Flash Bank1 mapped at 0x08100000 (AXI) (aliased at 0x00300000 (TCM))
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_EnableMemorySwappingBank(void)
|
||||
{
|
||||
SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the Internal FLASH Bank Swapping.
|
||||
*
|
||||
* @note This function can be used only for STM32F77xx/STM32F76xx devices.
|
||||
*
|
||||
* @note The default state : Flash Bank1 mapped at 0x08000000 (AXI) (aliased at 0x00200000 (TCM))
|
||||
* and Flash Bank2 mapped at 0x08100000 (AXI)( aliased at 0x00300000 (TCM))
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DisableMemorySwappingBank(void)
|
||||
{
|
||||
CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB);
|
||||
}
|
||||
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
@ -0,0 +1,503 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_cortex.c
|
||||
* @author MCD Application Team
|
||||
* @brief CORTEX HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the CORTEX:
|
||||
* + Initialization and de-initialization functions
|
||||
* + Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
|
||||
[..]
|
||||
*** How to configure Interrupts using CORTEX HAL driver ***
|
||||
===========================================================
|
||||
[..]
|
||||
This section provides functions allowing to configure the NVIC interrupts (IRQ).
|
||||
The Cortex-M4 exceptions are managed by CMSIS functions.
|
||||
|
||||
(#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
|
||||
function according to the following table.
|
||||
(#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
|
||||
(#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
|
||||
(#) please refer to programming manual for details in how to configure priority.
|
||||
|
||||
-@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
|
||||
The pending IRQ priority will be managed only by the sub priority.
|
||||
|
||||
-@- IRQ priority order (sorted by highest to lowest priority):
|
||||
(+@) Lowest preemption priority
|
||||
(+@) Lowest sub priority
|
||||
(+@) Lowest hardware priority (IRQ number)
|
||||
|
||||
[..]
|
||||
*** How to configure Systick using CORTEX HAL driver ***
|
||||
========================================================
|
||||
[..]
|
||||
Setup SysTick Timer for time base.
|
||||
|
||||
(+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
|
||||
is a CMSIS function that:
|
||||
(++) Configures the SysTick Reload register with value passed as function parameter.
|
||||
(++) Configures the SysTick IRQ priority to the lowest value (0x0F).
|
||||
(++) Resets the SysTick Counter register.
|
||||
(++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
|
||||
(++) Enables the SysTick Interrupt.
|
||||
(++) Starts the SysTick Counter.
|
||||
|
||||
(+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
|
||||
__HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
|
||||
HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
|
||||
inside the stm32f7xx_hal_cortex.h file.
|
||||
|
||||
(+) You can change the SysTick IRQ priority by calling the
|
||||
HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
|
||||
call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
|
||||
|
||||
(+) To adjust the SysTick time base, use the following formula:
|
||||
|
||||
Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
|
||||
(++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
|
||||
(++) Reload Value should not exceed 0xFFFFFF
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file in
|
||||
* the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX CORTEX
|
||||
* @brief CORTEX HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_CORTEX_MODULE_ENABLED
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This section provides the CORTEX HAL driver functions allowing to configure Interrupts
|
||||
Systick functionalities
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Sets the priority grouping field (preemption priority and subpriority)
|
||||
* using the required unlock sequence.
|
||||
* @param PriorityGroup The priority grouping bits length.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
|
||||
* 4 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
|
||||
* 3 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
|
||||
* 2 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
|
||||
* 1 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
|
||||
* 0 bits for subpriority
|
||||
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
|
||||
* The pending IRQ priority will be managed only by the subpriority.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
||||
|
||||
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
|
||||
NVIC_SetPriorityGrouping(PriorityGroup);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the priority of an interrupt.
|
||||
* @param IRQn External interrupt number.
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
|
||||
* @param PreemptPriority The preemption priority for the IRQn channel.
|
||||
* This parameter can be a value between 0 and 15
|
||||
* A lower priority value indicates a higher priority
|
||||
* @param SubPriority the subpriority level for the IRQ channel.
|
||||
* This parameter can be a value between 0 and 15
|
||||
* A lower priority value indicates a higher priority.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||
{
|
||||
uint32_t prioritygroup = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
|
||||
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
||||
|
||||
prioritygroup = NVIC_GetPriorityGrouping();
|
||||
|
||||
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables a device specific interrupt in the NVIC interrupt controller.
|
||||
* @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
|
||||
* function should be called before.
|
||||
* @param IRQn External interrupt number.
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||||
|
||||
/* Enable interrupt */
|
||||
NVIC_EnableIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables a device specific interrupt in the NVIC interrupt controller.
|
||||
* @param IRQn External interrupt number.
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||||
|
||||
/* Disable interrupt */
|
||||
NVIC_DisableIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initiates a system reset request to reset the MCU.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_SystemReset(void)
|
||||
{
|
||||
/* System Reset */
|
||||
NVIC_SystemReset();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||
* Counter is in free running mode to generate periodic interrupts.
|
||||
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
|
||||
* @retval status: - 0 Function succeeded.
|
||||
* - 1 Function failed.
|
||||
*/
|
||||
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
||||
{
|
||||
return SysTick_Config(TicksNumb);
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief Cortex control functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control the CORTEX
|
||||
(NVIC, SYSTICK, MPU) functionalities.
|
||||
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (__MPU_PRESENT == 1)
|
||||
/**
|
||||
* @brief Disables the MPU
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_MPU_Disable(void)
|
||||
{
|
||||
/* Make sure outstanding transfers are done */
|
||||
__DMB();
|
||||
|
||||
/* Disable fault exceptions */
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
|
||||
/* Disable the MPU and clear the control register*/
|
||||
MPU->CTRL = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the MPU
|
||||
* @param MPU_Control Specifies the control mode of the MPU during hard fault,
|
||||
* NMI, FAULTMASK and privileged access to the default memory
|
||||
* This parameter can be one of the following values:
|
||||
* @arg MPU_HFNMI_PRIVDEF_NONE
|
||||
* @arg MPU_HARDFAULT_NMI
|
||||
* @arg MPU_PRIVILEGED_DEFAULT
|
||||
* @arg MPU_HFNMI_PRIVDEF
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
/* Enable the MPU */
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
|
||||
/* Enable fault exceptions */
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
|
||||
/* Ensure MPU setting take effects */
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes and configures the Region and the memory to be protected.
|
||||
* @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
|
||||
* the initialization and configuration information.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
|
||||
assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
|
||||
|
||||
/* Set the Region number */
|
||||
MPU->RNR = MPU_Init->Number;
|
||||
|
||||
if ((MPU_Init->Enable) != RESET)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
|
||||
assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
|
||||
assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
|
||||
assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
|
||||
assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
|
||||
assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
|
||||
assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
|
||||
assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
|
||||
|
||||
MPU->RBAR = MPU_Init->BaseAddress;
|
||||
MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
|
||||
((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
|
||||
((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
|
||||
((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
|
||||
((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
|
||||
((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
|
||||
((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
|
||||
((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
|
||||
((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
|
||||
}
|
||||
else
|
||||
{
|
||||
MPU->RBAR = 0x00;
|
||||
MPU->RASR = 0x00;
|
||||
}
|
||||
}
|
||||
#endif /* __MPU_PRESENT */
|
||||
|
||||
/**
|
||||
* @brief Gets the priority grouping field from the NVIC Interrupt Controller.
|
||||
* @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
|
||||
*/
|
||||
uint32_t HAL_NVIC_GetPriorityGrouping(void)
|
||||
{
|
||||
/* Get the PRIGROUP[10:8] field value */
|
||||
return NVIC_GetPriorityGrouping();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets the priority of an interrupt.
|
||||
* @param IRQn External interrupt number.
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
|
||||
* @param PriorityGroup the priority grouping bits length.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
|
||||
* 4 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
|
||||
* 3 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
|
||||
* 2 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
|
||||
* 1 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
|
||||
* 0 bits for subpriority
|
||||
* @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
|
||||
* @param pSubPriority Pointer on the Subpriority value (starting from 0).
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
||||
/* Get priority for Cortex-M system or device specific interrupts */
|
||||
NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets Pending bit of an external interrupt.
|
||||
* @param IRQn External interrupt number
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||||
|
||||
/* Set interrupt pending */
|
||||
NVIC_SetPendingIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets Pending Interrupt (reads the pending register in the NVIC
|
||||
* and returns the pending bit for the specified interrupt).
|
||||
* @param IRQn External interrupt number.
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
|
||||
* @retval status: - 0 Interrupt status is not pending.
|
||||
* - 1 Interrupt status is pending.
|
||||
*/
|
||||
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||||
|
||||
/* Return 1 if pending else 0 */
|
||||
return NVIC_GetPendingIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the pending bit of an external interrupt.
|
||||
* @param IRQn External interrupt number.
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||||
|
||||
/* Clear pending interrupt */
|
||||
NVIC_ClearPendingIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
|
||||
* @param IRQn External interrupt number
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
|
||||
* @retval status: - 0 Interrupt status is not pending.
|
||||
* - 1 Interrupt status is pending.
|
||||
*/
|
||||
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||||
|
||||
/* Return 1 if active else 0 */
|
||||
return NVIC_GetActive(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the SysTick clock source.
|
||||
* @param CLKSource specifies the SysTick clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
|
||||
* @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
|
||||
if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
|
||||
{
|
||||
SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
|
||||
}
|
||||
else
|
||||
{
|
||||
SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles SYSTICK interrupt request.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SYSTICK_IRQHandler(void)
|
||||
{
|
||||
HAL_SYSTICK_Callback();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SYSTICK callback.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_SYSTICK_Callback(void)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_SYSTICK_Callback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_CORTEX_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,308 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_dma_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief DMA Extension HAL module driver
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the DMA Extension peripheral:
|
||||
* + Extended features functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
The DMA Extension HAL driver can be used as follows:
|
||||
(+) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function
|
||||
for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.
|
||||
|
||||
-@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
|
||||
-@- When Multi (Double) Buffer mode is enabled, the transfer is circular by default.
|
||||
-@- In Multi (Double) buffer mode, it is possible to update the base address for
|
||||
the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file in
|
||||
* the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx DMAEx
|
||||
* @brief DMA Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_DMA_MODULE_ENABLED
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private Constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @addtogroup DMAEx_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions ---------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup DMAEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup DMAEx_Exported_Functions_Group1
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Extended features functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure the source, destination address and data length and
|
||||
Start MultiBuffer DMA transfer
|
||||
(+) Configure the source, destination address and data length and
|
||||
Start MultiBuffer DMA transfer with interrupt
|
||||
(+) Change on the fly the memory0 or memory1 address.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Starts the multi_buffer DMA Transfer.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Stream.
|
||||
* @param SrcAddress The source memory Buffer address
|
||||
* @param DstAddress The destination memory Buffer address
|
||||
* @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer
|
||||
* @param DataLength The length of data to be transferred from source to destination
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
|
||||
|
||||
/* Memory-to-memory transfer not supported in double buffering mode */
|
||||
if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
|
||||
{
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hdma);
|
||||
|
||||
if(HAL_DMA_STATE_READY == hdma->State)
|
||||
{
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_BUSY;
|
||||
|
||||
/* Enable the double buffer mode */
|
||||
hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
|
||||
|
||||
/* Configure DMA Stream destination address */
|
||||
hdma->Instance->M1AR = SecondMemAddress;
|
||||
|
||||
/* Configure the source, destination address and the data length */
|
||||
DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
|
||||
|
||||
/* Enable the peripheral */
|
||||
__HAL_DMA_ENABLE(hdma);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Return error status */
|
||||
status = HAL_BUSY;
|
||||
}
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Starts the multi_buffer DMA Transfer with interrupt enabled.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Stream.
|
||||
* @param SrcAddress The source memory Buffer address
|
||||
* @param DstAddress The destination memory Buffer address
|
||||
* @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer
|
||||
* @param DataLength The length of data to be transferred from source to destination
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
|
||||
|
||||
/* Memory-to-memory transfer not supported in double buffering mode */
|
||||
if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
|
||||
{
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdma);
|
||||
|
||||
if(HAL_DMA_STATE_READY == hdma->State)
|
||||
{
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_BUSY;
|
||||
|
||||
/* Initialize the error code */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
||||
|
||||
/* Enable the Double buffer mode */
|
||||
hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
|
||||
|
||||
/* Configure DMA Stream destination address */
|
||||
hdma->Instance->M1AR = SecondMemAddress;
|
||||
|
||||
/* Configure the source, destination address and the data length */
|
||||
DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
|
||||
|
||||
/* Clear all flags */
|
||||
__HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
|
||||
__HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
|
||||
__HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
|
||||
__HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
|
||||
__HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
|
||||
|
||||
/* Enable Common interrupts*/
|
||||
hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
|
||||
hdma->Instance->FCR |= DMA_IT_FE;
|
||||
|
||||
if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
|
||||
{
|
||||
hdma->Instance->CR |= DMA_IT_HT;
|
||||
}
|
||||
|
||||
/* Enable the peripheral */
|
||||
__HAL_DMA_ENABLE(hdma);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
/* Return error status */
|
||||
status = HAL_BUSY;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Change the memory0 or memory1 address on the fly.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Stream.
|
||||
* @param Address The new address
|
||||
* @param memory the memory to be changed, This parameter can be one of
|
||||
* the following values:
|
||||
* MEMORY0 /
|
||||
* MEMORY1
|
||||
* @note The MEMORY0 address can be changed only when the current transfer use
|
||||
* MEMORY1 and the MEMORY1 address can be changed only when the current
|
||||
* transfer use MEMORY0.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
|
||||
{
|
||||
if(memory == MEMORY0)
|
||||
{
|
||||
/* change the memory0 address */
|
||||
hdma->Instance->M0AR = Address;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* change the memory1 address */
|
||||
hdma->Instance->M1AR = Address;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMAEx_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set the DMA Transfer parameter.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Stream.
|
||||
* @param SrcAddress The source memory Buffer address
|
||||
* @param DstAddress The destination memory Buffer address
|
||||
* @param DataLength The length of data to be transferred from source to destination
|
||||
* @retval HAL status
|
||||
*/
|
||||
static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
||||
{
|
||||
/* Configure DMA Stream data length */
|
||||
hdma->Instance->NDTR = DataLength;
|
||||
|
||||
/* Peripheral to Memory */
|
||||
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
|
||||
{
|
||||
/* Configure DMA Stream destination address */
|
||||
hdma->Instance->PAR = DstAddress;
|
||||
|
||||
/* Configure DMA Stream source address */
|
||||
hdma->Instance->M0AR = SrcAddress;
|
||||
}
|
||||
/* Memory to Peripheral */
|
||||
else
|
||||
{
|
||||
/* Configure DMA Stream source address */
|
||||
hdma->Instance->PAR = SrcAddress;
|
||||
|
||||
/* Configure DMA Stream destination address */
|
||||
hdma->Instance->M0AR = DstAddress;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@ -0,0 +1,547 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32F7xx_hal_exti.c
|
||||
* @author MCD Application Team
|
||||
* @brief EXTI HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Extended Interrupts and events controller (EXTI) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + IO operation functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2018 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### EXTI Peripheral features #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(+) Each Exti line can be configured within this driver.
|
||||
|
||||
(+) Exti line can be configured in 3 different modes
|
||||
(++) Interrupt
|
||||
(++) Event
|
||||
(++) Both of them
|
||||
|
||||
(+) Configurable Exti lines can be configured with 3 different triggers
|
||||
(++) Rising
|
||||
(++) Falling
|
||||
(++) Both of them
|
||||
|
||||
(+) When set in interrupt mode, configurable Exti lines have two different
|
||||
interrupts pending registers which allow to distinguish which transition
|
||||
occurs:
|
||||
(++) Rising edge pending interrupt
|
||||
(++) Falling
|
||||
|
||||
(+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
|
||||
be selected through multiplexer.
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
|
||||
(#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
|
||||
(++) Choose the interrupt line number by setting "Line" member from
|
||||
EXTI_ConfigTypeDef structure.
|
||||
(++) Configure the interrupt and/or event mode using "Mode" member from
|
||||
EXTI_ConfigTypeDef structure.
|
||||
(++) For configurable lines, configure rising and/or falling trigger
|
||||
"Trigger" member from EXTI_ConfigTypeDef structure.
|
||||
(++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
|
||||
member from GPIO_InitTypeDef structure.
|
||||
|
||||
(#) Get current Exti configuration of a dedicated line using
|
||||
HAL_EXTI_GetConfigLine().
|
||||
(++) Provide exiting handle as parameter.
|
||||
(++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
|
||||
|
||||
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
|
||||
(++) Provide exiting handle as parameter.
|
||||
|
||||
(#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
|
||||
(++) Provide exiting handle as first parameter.
|
||||
(++) Provide which callback will be registered using one value from
|
||||
EXTI_CallbackIDTypeDef.
|
||||
(++) Provide callback function pointer.
|
||||
|
||||
(#) Get interrupt pending bit using HAL_EXTI_GetPending().
|
||||
|
||||
(#) Clear interrupt pending bit using HAL_EXTI_GetPending().
|
||||
|
||||
(#) Generate software interrupt using HAL_EXTI_GenerateSWI().
|
||||
|
||||
@endverbatim
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI
|
||||
* @{
|
||||
*/
|
||||
/** MISRA C:2012 deviation rule has been granted for following rule:
|
||||
* Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out
|
||||
* of bounds [0,3] in following API :
|
||||
* HAL_EXTI_SetConfigLine
|
||||
* HAL_EXTI_GetConfigLine
|
||||
* HAL_EXTI_ClearConfigLine
|
||||
*/
|
||||
|
||||
#ifdef HAL_EXTI_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Private_Constants EXTI Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup EXTI_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI_Exported_Functions_Group1
|
||||
* @brief Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Configuration functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set configuration of a dedicated Exti line.
|
||||
* @param hexti Exti handle.
|
||||
* @param pExtiConfig Pointer on EXTI configuration to be set.
|
||||
* @retval HAL Status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t linepos;
|
||||
uint32_t maskline;
|
||||
|
||||
/* Check null pointer */
|
||||
if ((hexti == NULL) || (pExtiConfig == NULL))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_EXTI_LINE(pExtiConfig->Line));
|
||||
assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
|
||||
|
||||
/* Assign line number to handle */
|
||||
hexti->Line = pExtiConfig->Line;
|
||||
|
||||
/* Compute line mask */
|
||||
linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
|
||||
maskline = (1uL << linepos);
|
||||
|
||||
/* Configure triggers for configurable lines */
|
||||
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
|
||||
{
|
||||
assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
|
||||
|
||||
/* Configure rising trigger */
|
||||
/* Mask or set line */
|
||||
if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u)
|
||||
{
|
||||
EXTI->RTSR |= maskline;
|
||||
}
|
||||
else
|
||||
{
|
||||
EXTI->RTSR &= ~maskline;
|
||||
}
|
||||
|
||||
/* Configure falling trigger */
|
||||
/* Mask or set line */
|
||||
if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u)
|
||||
{
|
||||
EXTI->FTSR |= maskline;
|
||||
}
|
||||
else
|
||||
{
|
||||
EXTI->FTSR &= ~maskline;
|
||||
}
|
||||
|
||||
|
||||
/* Configure gpio port selection in case of gpio exti line */
|
||||
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
|
||||
{
|
||||
assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
|
||||
assert_param(IS_EXTI_GPIO_PIN(linepos));
|
||||
|
||||
regval = SYSCFG->EXTICR[linepos >> 2u];
|
||||
regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
|
||||
regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
|
||||
SYSCFG->EXTICR[linepos >> 2u] = regval;
|
||||
}
|
||||
}
|
||||
|
||||
/* Configure interrupt mode : read current mode */
|
||||
/* Mask or set line */
|
||||
if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u)
|
||||
{
|
||||
EXTI->IMR |= maskline;
|
||||
}
|
||||
else
|
||||
{
|
||||
EXTI->IMR &= ~maskline;
|
||||
}
|
||||
|
||||
/* Configure event mode : read current mode */
|
||||
/* Mask or set line */
|
||||
if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u)
|
||||
{
|
||||
EXTI->EMR |= maskline;
|
||||
}
|
||||
else
|
||||
{
|
||||
EXTI->EMR &= ~maskline;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get configuration of a dedicated Exti line.
|
||||
* @param hexti Exti handle.
|
||||
* @param pExtiConfig Pointer on structure to store Exti configuration.
|
||||
* @retval HAL Status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t linepos;
|
||||
uint32_t maskline;
|
||||
|
||||
/* Check null pointer */
|
||||
if ((hexti == NULL) || (pExtiConfig == NULL))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameter */
|
||||
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||
|
||||
/* Store handle line number to configuration structure */
|
||||
pExtiConfig->Line = hexti->Line;
|
||||
|
||||
/* Compute line mask */
|
||||
linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
|
||||
maskline = (1uL << linepos);
|
||||
|
||||
/* 1] Get core mode : interrupt */
|
||||
|
||||
/* Check if selected line is enable */
|
||||
if ((EXTI->IMR & maskline) != 0x00u)
|
||||
{
|
||||
pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
|
||||
}
|
||||
else
|
||||
{
|
||||
pExtiConfig->Mode = EXTI_MODE_NONE;
|
||||
}
|
||||
|
||||
/* Get event mode */
|
||||
/* Check if selected line is enable */
|
||||
if ((EXTI->EMR & maskline) != 0x00u)
|
||||
{
|
||||
pExtiConfig->Mode |= EXTI_MODE_EVENT;
|
||||
}
|
||||
|
||||
/* Get default Trigger and GPIOSel configuration */
|
||||
pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
|
||||
pExtiConfig->GPIOSel = 0x00u;
|
||||
|
||||
/* 2] Get trigger for configurable lines : rising */
|
||||
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
|
||||
{
|
||||
/* Check if configuration of selected line is enable */
|
||||
if ((EXTI->RTSR & maskline) != 0x00u)
|
||||
{
|
||||
pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
|
||||
}
|
||||
|
||||
/* Get falling configuration */
|
||||
/* Check if configuration of selected line is enable */
|
||||
if ((EXTI->FTSR & maskline) != 0x00u)
|
||||
{
|
||||
pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
|
||||
}
|
||||
|
||||
/* Get Gpio port selection for gpio lines */
|
||||
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
|
||||
{
|
||||
assert_param(IS_EXTI_GPIO_PIN(linepos));
|
||||
|
||||
regval = SYSCFG->EXTICR[linepos >> 2u];
|
||||
pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24);
|
||||
}
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear whole configuration of a dedicated Exti line.
|
||||
* @param hexti Exti handle.
|
||||
* @retval HAL Status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t linepos;
|
||||
uint32_t maskline;
|
||||
|
||||
/* Check null pointer */
|
||||
if (hexti == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameter */
|
||||
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||
|
||||
/* compute line mask */
|
||||
linepos = (hexti->Line & EXTI_PIN_MASK);
|
||||
maskline = (1uL << linepos);
|
||||
|
||||
/* 1] Clear interrupt mode */
|
||||
EXTI->IMR = (EXTI->IMR & ~maskline);
|
||||
|
||||
/* 2] Clear event mode */
|
||||
EXTI->EMR = (EXTI->EMR & ~maskline);
|
||||
|
||||
/* 3] Clear triggers in case of configurable lines */
|
||||
if ((hexti->Line & EXTI_CONFIG) != 0x00u)
|
||||
{
|
||||
EXTI->RTSR = (EXTI->RTSR & ~maskline);
|
||||
EXTI->FTSR = (EXTI->FTSR & ~maskline);
|
||||
|
||||
/* Get Gpio port selection for gpio lines */
|
||||
if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
|
||||
{
|
||||
assert_param(IS_EXTI_GPIO_PIN(linepos));
|
||||
|
||||
regval = SYSCFG->EXTICR[linepos >> 2u];
|
||||
regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
|
||||
SYSCFG->EXTICR[linepos >> 2u] = regval;
|
||||
}
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Register callback for a dedicated Exti line.
|
||||
* @param hexti Exti handle.
|
||||
* @param CallbackID User callback identifier.
|
||||
* This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
|
||||
* @param pPendingCbfn function pointer to be stored as callback.
|
||||
* @retval HAL Status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_EXTI_COMMON_CB_ID:
|
||||
hexti->PendingCallback = pPendingCbfn;
|
||||
break;
|
||||
|
||||
default:
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Store line number as handle private field.
|
||||
* @param hexti Exti handle.
|
||||
* @param ExtiLine Exti line number.
|
||||
* This parameter can be from 0 to @ref EXTI_LINE_NB.
|
||||
* @retval HAL Status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_LINE(ExtiLine));
|
||||
|
||||
/* Check null pointer */
|
||||
if (hexti == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Store line number as handle private field */
|
||||
hexti->Line = ExtiLine;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI_Exported_Functions_Group2
|
||||
* @brief EXTI IO functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Handle EXTI interrupt request.
|
||||
* @param hexti Exti handle.
|
||||
* @retval none.
|
||||
*/
|
||||
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t maskline;
|
||||
|
||||
/* Compute line mask */
|
||||
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
|
||||
|
||||
/* Get pending bit */
|
||||
regval = (EXTI->PR & maskline);
|
||||
if (regval != 0x00u)
|
||||
{
|
||||
/* Clear pending bit */
|
||||
EXTI->PR = maskline;
|
||||
|
||||
/* Call callback */
|
||||
if (hexti->PendingCallback != NULL)
|
||||
{
|
||||
hexti->PendingCallback();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get interrupt pending bit of a dedicated line.
|
||||
* @param hexti Exti handle.
|
||||
* @param Edge Specify which pending edge as to be checked.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref EXTI_TRIGGER_RISING_FALLING
|
||||
* This parameter is kept for compatibility with other series.
|
||||
* @retval 1 if interrupt is pending else 0.
|
||||
*/
|
||||
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t linepos;
|
||||
uint32_t maskline;
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
|
||||
assert_param(IS_EXTI_PENDING_EDGE(Edge));
|
||||
|
||||
/* Compute line mask */
|
||||
linepos = (hexti->Line & EXTI_PIN_MASK);
|
||||
maskline = (1uL << linepos);
|
||||
|
||||
/* return 1 if bit is set else 0 */
|
||||
regval = ((EXTI->PR & maskline) >> linepos);
|
||||
return regval;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear interrupt pending bit of a dedicated line.
|
||||
* @param hexti Exti handle.
|
||||
* @param Edge Specify which pending edge as to be clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref EXTI_TRIGGER_RISING_FALLING
|
||||
* This parameter is kept for compatibility with other series.
|
||||
* @retval None.
|
||||
*/
|
||||
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
|
||||
{
|
||||
uint32_t maskline;
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
|
||||
assert_param(IS_EXTI_PENDING_EDGE(Edge));
|
||||
|
||||
/* Compute line mask */
|
||||
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
|
||||
|
||||
/* Clear Pending bit */
|
||||
EXTI->PR = maskline;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Generate a software interrupt for a dedicated line.
|
||||
* @param hexti Exti handle.
|
||||
* @retval None.
|
||||
*/
|
||||
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
|
||||
{
|
||||
uint32_t maskline;
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
|
||||
|
||||
/* Compute line mask */
|
||||
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
|
||||
|
||||
/* Generate Software interrupt */
|
||||
EXTI->SWIER = maskline;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_EXTI_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@ -0,0 +1,819 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_flash.c
|
||||
* @author MCD Application Team
|
||||
* @brief FLASH HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the internal FLASH memory:
|
||||
* + Program operations functions
|
||||
* + Memory Control functions
|
||||
* + Peripheral Errors functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### FLASH peripheral features #####
|
||||
==============================================================================
|
||||
|
||||
[..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
|
||||
to the Flash memory. It implements the erase and program Flash memory operations
|
||||
and the read and write protection mechanisms.
|
||||
|
||||
[..] The Flash memory interface accelerates code execution with a system of instruction
|
||||
prefetch and cache lines.
|
||||
|
||||
[..] The FLASH main features are:
|
||||
(+) Flash memory read operations
|
||||
(+) Flash memory program/erase operations
|
||||
(+) Read / write protections
|
||||
(+) Prefetch on I-Code
|
||||
(+) 64 cache lines of 128 bits on I-Code
|
||||
(+) 8 cache lines of 128 bits on D-Code
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This driver provides functions and macros to configure and program the FLASH
|
||||
memory of all STM32F7xx devices.
|
||||
|
||||
(#) FLASH Memory IO Programming functions:
|
||||
(++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
|
||||
HAL_FLASH_Lock() functions
|
||||
(++) Program functions: byte, half word, word and double word
|
||||
(++) There Two modes of programming :
|
||||
(+++) Polling mode using HAL_FLASH_Program() function
|
||||
(+++) Interrupt mode using HAL_FLASH_Program_IT() function
|
||||
|
||||
(#) Interrupts and flags management functions :
|
||||
(++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
|
||||
(++) Wait for last FLASH operation according to its status
|
||||
(++) Get error flag status by calling HAL_SetErrorCode()
|
||||
[..]
|
||||
In addition to these functions, this driver includes a set of macros allowing
|
||||
to handle the following operations:
|
||||
(+) Set the latency
|
||||
(+) Enable/Disable the prefetch buffer
|
||||
(+) Enable/Disable the Instruction cache and the Data cache
|
||||
(+) Reset the Instruction cache and the Data cache
|
||||
(+) Enable/Disable the FLASH interrupts
|
||||
(+) Monitor the FLASH flags status
|
||||
[..]
|
||||
(@) For any Flash memory program operation (erase or program), the CPU clock frequency
|
||||
(HCLK) must be at least 1MHz.
|
||||
(@) The contents of the Flash memory are not guaranteed if a device reset occurs during
|
||||
a Flash memory operation.
|
||||
(@) Any attempt to read the Flash memory while it is being written or erased, causes the
|
||||
bus to stall. Read operations are processed correctly once the program operation has
|
||||
completed. This means that code or data fetches cannot be performed while a write/erase
|
||||
operation is ongoing.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file in
|
||||
* the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH FLASH
|
||||
* @brief FLASH HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @addtogroup FLASH_Private_Constants
|
||||
* @{
|
||||
*/
|
||||
#define SECTOR_MASK ((uint32_t)0xFFFFFF07U)
|
||||
#define FLASH_TIMEOUT_VALUE ((uint32_t)50000U)/* 50 s */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @addtogroup FLASH_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
/* Variable used for Erase sectors under interruption */
|
||||
FLASH_ProcessTypeDef pFlash;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/** @addtogroup FLASH_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
/* Program operations */
|
||||
static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);
|
||||
static void FLASH_Program_Word(uint32_t Address, uint32_t Data);
|
||||
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);
|
||||
static void FLASH_Program_Byte(uint32_t Address, uint8_t Data);
|
||||
static void FLASH_SetErrorCode(void);
|
||||
|
||||
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
|
||||
* @brief Programming operation functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Programming operation functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to manage the FLASH
|
||||
program operations.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Program byte, halfword, word or double word at a specified address
|
||||
* @param TypeProgram Indicate the way to program at a specified address.
|
||||
* This parameter can be a value of @ref FLASH_Type_Program
|
||||
* @param Address specifies the address to be programmed.
|
||||
* @param Data specifies the data to be programmed
|
||||
*
|
||||
* @retval HAL_StatusTypeDef HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_ERROR;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
switch(TypeProgram)
|
||||
{
|
||||
case FLASH_TYPEPROGRAM_BYTE :
|
||||
{
|
||||
/*Program byte (8-bit) at a specified address.*/
|
||||
FLASH_Program_Byte(Address, (uint8_t) Data);
|
||||
break;
|
||||
}
|
||||
|
||||
case FLASH_TYPEPROGRAM_HALFWORD :
|
||||
{
|
||||
/*Program halfword (16-bit) at a specified address.*/
|
||||
FLASH_Program_HalfWord(Address, (uint16_t) Data);
|
||||
break;
|
||||
}
|
||||
|
||||
case FLASH_TYPEPROGRAM_WORD :
|
||||
{
|
||||
/*Program word (32-bit) at a specified address.*/
|
||||
FLASH_Program_Word(Address, (uint32_t) Data);
|
||||
break;
|
||||
}
|
||||
|
||||
case FLASH_TYPEPROGRAM_DOUBLEWORD :
|
||||
{
|
||||
/*Program double word (64-bit) at a specified address.*/
|
||||
FLASH_Program_DoubleWord(Address, Data);
|
||||
break;
|
||||
}
|
||||
default :
|
||||
break;
|
||||
}
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* If the program operation is completed, disable the PG Bit */
|
||||
FLASH->CR &= (~FLASH_CR_PG);
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Program byte, halfword, word or double word at a specified address with interrupt enabled.
|
||||
* @param TypeProgram Indicate the way to program at a specified address.
|
||||
* This parameter can be a value of @ref FLASH_Type_Program
|
||||
* @param Address specifies the address to be programmed.
|
||||
* @param Data specifies the data to be programmed
|
||||
*
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
|
||||
|
||||
/* Enable End of FLASH Operation interrupt */
|
||||
__HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
|
||||
|
||||
/* Enable Error source interrupt */
|
||||
__HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
|
||||
|
||||
/* Clear pending flags (if any) */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\
|
||||
FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_ERSERR);
|
||||
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;
|
||||
pFlash.Address = Address;
|
||||
|
||||
switch(TypeProgram)
|
||||
{
|
||||
case FLASH_TYPEPROGRAM_BYTE :
|
||||
{
|
||||
/*Program byte (8-bit) at a specified address.*/
|
||||
FLASH_Program_Byte(Address, (uint8_t) Data);
|
||||
break;
|
||||
}
|
||||
|
||||
case FLASH_TYPEPROGRAM_HALFWORD :
|
||||
{
|
||||
/*Program halfword (16-bit) at a specified address.*/
|
||||
FLASH_Program_HalfWord(Address, (uint16_t) Data);
|
||||
break;
|
||||
}
|
||||
|
||||
case FLASH_TYPEPROGRAM_WORD :
|
||||
{
|
||||
/*Program word (32-bit) at a specified address.*/
|
||||
FLASH_Program_Word(Address, (uint32_t) Data);
|
||||
break;
|
||||
}
|
||||
|
||||
case FLASH_TYPEPROGRAM_DOUBLEWORD :
|
||||
{
|
||||
/*Program double word (64-bit) at a specified address.*/
|
||||
FLASH_Program_DoubleWord(Address, Data);
|
||||
break;
|
||||
}
|
||||
default :
|
||||
break;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles FLASH interrupt request.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASH_IRQHandler(void)
|
||||
{
|
||||
uint32_t temp = 0;
|
||||
|
||||
/* If the program operation is completed, disable the PG Bit */
|
||||
FLASH->CR &= (~FLASH_CR_PG);
|
||||
|
||||
/* If the erase operation is completed, disable the SER Bit */
|
||||
FLASH->CR &= (~FLASH_CR_SER);
|
||||
FLASH->CR &= SECTOR_MASK;
|
||||
|
||||
/* if the erase operation is completed, disable the MER Bit */
|
||||
FLASH->CR &= (~FLASH_MER_BIT);
|
||||
|
||||
/* Check FLASH End of Operation flag */
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)
|
||||
{
|
||||
/* Clear FLASH End of Operation pending bit */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
|
||||
|
||||
switch (pFlash.ProcedureOnGoing)
|
||||
{
|
||||
case FLASH_PROC_SECTERASE :
|
||||
{
|
||||
/* Nb of sector to erased can be decreased */
|
||||
pFlash.NbSectorsToErase--;
|
||||
|
||||
/* Check if there are still sectors to erase */
|
||||
if(pFlash.NbSectorsToErase != 0)
|
||||
{
|
||||
temp = pFlash.Sector;
|
||||
/* Indicate user which sector has been erased */
|
||||
HAL_FLASH_EndOfOperationCallback(temp);
|
||||
|
||||
/* Increment sector number */
|
||||
temp = ++pFlash.Sector;
|
||||
FLASH_Erase_Sector(temp, pFlash.VoltageForErase);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* No more sectors to Erase, user callback can be called.*/
|
||||
/* Reset Sector and stop Erase sectors procedure */
|
||||
pFlash.Sector = temp = 0xFFFFFFFFU;
|
||||
/* FLASH EOP interrupt user callback */
|
||||
HAL_FLASH_EndOfOperationCallback(temp);
|
||||
/* Sector Erase procedure is completed */
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
case FLASH_PROC_MASSERASE :
|
||||
{
|
||||
/* MassErase ended. Return the selected bank : in this product we don't have Banks */
|
||||
/* FLASH EOP interrupt user callback */
|
||||
HAL_FLASH_EndOfOperationCallback(0);
|
||||
/* MAss Erase procedure is completed */
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
|
||||
break;
|
||||
}
|
||||
|
||||
case FLASH_PROC_PROGRAM :
|
||||
{
|
||||
/*Program ended. Return the selected address*/
|
||||
/* FLASH EOP interrupt user callback */
|
||||
HAL_FLASH_EndOfOperationCallback(pFlash.Address);
|
||||
/* Programming procedure is completed */
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
|
||||
break;
|
||||
}
|
||||
default :
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Check FLASH operation error flags */
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ALL_ERRORS) != RESET)
|
||||
{
|
||||
switch (pFlash.ProcedureOnGoing)
|
||||
{
|
||||
case FLASH_PROC_SECTERASE :
|
||||
{
|
||||
/* return the faulty sector */
|
||||
temp = pFlash.Sector;
|
||||
pFlash.Sector = 0xFFFFFFFFU;
|
||||
break;
|
||||
}
|
||||
case FLASH_PROC_MASSERASE :
|
||||
{
|
||||
/* No return in case of Mass Erase */
|
||||
temp = 0;
|
||||
break;
|
||||
}
|
||||
case FLASH_PROC_PROGRAM :
|
||||
{
|
||||
/*return the faulty address*/
|
||||
temp = pFlash.Address;
|
||||
break;
|
||||
}
|
||||
default :
|
||||
break;
|
||||
}
|
||||
/*Save the Error code*/
|
||||
FLASH_SetErrorCode();
|
||||
|
||||
/* FLASH error interrupt user callback */
|
||||
HAL_FLASH_OperationErrorCallback(temp);
|
||||
|
||||
/*Stop the procedure ongoing */
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
|
||||
}
|
||||
|
||||
if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
|
||||
{
|
||||
/* Disable End of FLASH Operation interrupt */
|
||||
__HAL_FLASH_DISABLE_IT(FLASH_IT_EOP);
|
||||
|
||||
/* Disable Error source interrupt */
|
||||
__HAL_FLASH_DISABLE_IT(FLASH_IT_ERR);
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief FLASH end of operation interrupt callback
|
||||
* @param ReturnValue The value saved in this parameter depends on the ongoing procedure
|
||||
* - Sectors Erase: Sector which has been erased (if 0xFFFFFFFF, it means that
|
||||
* all the selected sectors have been erased)
|
||||
* - Program : Address which was selected for data program
|
||||
* - Mass Erase : No return value expected
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(ReturnValue);
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief FLASH operation error interrupt callback
|
||||
* @param ReturnValue The value saved in this parameter depends on the ongoing procedure
|
||||
* - Sectors Erase: Sector which has been erased (if 0xFFFFFFFF, it means that
|
||||
* all the selected sectors have been erased)
|
||||
* - Program : Address which was selected for data program
|
||||
* - Mass Erase : No return value expected
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(ReturnValue);
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_FLASH_OperationErrorCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control the FLASH
|
||||
memory operations.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Unlock the FLASH control register access
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Unlock(void)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
|
||||
{
|
||||
/* Authorize the FLASH Registers access */
|
||||
WRITE_REG(FLASH->KEYR, FLASH_KEY1);
|
||||
WRITE_REG(FLASH->KEYR, FLASH_KEY2);
|
||||
|
||||
/* Verify Flash is unlocked */
|
||||
if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Locks the FLASH control register access
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Lock(void)
|
||||
{
|
||||
/* Set the LOCK Bit to lock the FLASH Registers access */
|
||||
FLASH->CR |= FLASH_CR_LOCK;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Unlock the FLASH Option Control Registers access.
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
|
||||
{
|
||||
if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET)
|
||||
{
|
||||
/* Authorizes the Option Byte register programming */
|
||||
FLASH->OPTKEYR = FLASH_OPT_KEY1;
|
||||
FLASH->OPTKEYR = FLASH_OPT_KEY2;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Lock the FLASH Option Control Registers access.
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
|
||||
{
|
||||
/* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
|
||||
FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Launch the option byte loading.
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
|
||||
{
|
||||
/* Set the OPTSTRT bit in OPTCR register */
|
||||
FLASH->OPTCR |= FLASH_OPTCR_OPTSTRT;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions
|
||||
* @brief Peripheral Errors functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Errors functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection permits to get in run-time Errors of the FLASH peripheral.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get the specific FLASH error flag.
|
||||
* @retval FLASH_ErrorCode: The returned value can be:
|
||||
* @arg FLASH_ERROR_ERS: FLASH Erasing Sequence error flag
|
||||
* @arg FLASH_ERROR_PGP: FLASH Programming Parallelism error flag
|
||||
* @arg FLASH_ERROR_PGA: FLASH Programming Alignment error flag
|
||||
* @arg FLASH_ERROR_WRP: FLASH Write protected error flag
|
||||
* @arg FLASH_ERROR_OPERATION: FLASH operation Error flag
|
||||
*/
|
||||
uint32_t HAL_FLASH_GetError(void)
|
||||
{
|
||||
return pFlash.ErrorCode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Wait for a FLASH operation to complete.
|
||||
* @param Timeout maximum flash operationtimeout
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
|
||||
{
|
||||
uint32_t tickstart = 0;
|
||||
|
||||
/* Clear Error Code */
|
||||
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
||||
|
||||
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
|
||||
Even if the FLASH operation fails, the BUSY flag will be reset and an error
|
||||
flag will be set */
|
||||
/* Get tick */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET)
|
||||
{
|
||||
if(Timeout != HAL_MAX_DELAY)
|
||||
{
|
||||
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ALL_ERRORS) != RESET)
|
||||
{
|
||||
/*Save the error code*/
|
||||
FLASH_SetErrorCode();
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check FLASH End of Operation flag */
|
||||
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)
|
||||
{
|
||||
/* Clear FLASH End of Operation pending bit */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
|
||||
}
|
||||
|
||||
/* If there is an error flag set */
|
||||
return HAL_OK;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Program a double word (64-bit) at a specified address.
|
||||
* @note This function must be used when the device voltage range is from
|
||||
* 2.7V to 3.6V and an External Vpp is present.
|
||||
*
|
||||
* @note If an erase and a program operations are requested simultaneously,
|
||||
* the erase operation is performed before the program one.
|
||||
*
|
||||
* @param Address specifies the address to be programmed.
|
||||
* @param Data specifies the data to be programmed.
|
||||
* @retval None
|
||||
*/
|
||||
static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_ADDRESS(Address));
|
||||
|
||||
/* If the previous operation is completed, proceed to program the new data */
|
||||
FLASH->CR &= CR_PSIZE_MASK;
|
||||
FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;
|
||||
FLASH->CR |= FLASH_CR_PG;
|
||||
|
||||
/* Program first word */
|
||||
*(__IO uint32_t*)Address = (uint32_t)Data;
|
||||
/* Barrier to ensure programming is performed in 2 steps, in right order
|
||||
(independently of compiler optimization behavior) */
|
||||
__ISB();
|
||||
|
||||
/* Program second word */
|
||||
*(__IO uint32_t*)(Address+4) = (uint32_t)(Data >> 32);
|
||||
|
||||
/* Data synchronous Barrier (DSB) Just after the write operation
|
||||
This will force the CPU to respect the sequence of instruction (no optimization).*/
|
||||
__DSB();
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Program word (32-bit) at a specified address.
|
||||
* @note This function must be used when the device voltage range is from
|
||||
* 2.7V to 3.3V.
|
||||
*
|
||||
* @note If an erase and a program operations are requested simultaneously,
|
||||
* the erase operation is performed before the program one.
|
||||
*
|
||||
* @param Address specifies the address to be programmed.
|
||||
* @param Data specifies the data to be programmed.
|
||||
* @retval None
|
||||
*/
|
||||
static void FLASH_Program_Word(uint32_t Address, uint32_t Data)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_ADDRESS(Address));
|
||||
|
||||
/* If the previous operation is completed, proceed to program the new data */
|
||||
FLASH->CR &= CR_PSIZE_MASK;
|
||||
FLASH->CR |= FLASH_PSIZE_WORD;
|
||||
FLASH->CR |= FLASH_CR_PG;
|
||||
|
||||
*(__IO uint32_t*)Address = Data;
|
||||
|
||||
/* Data synchronous Barrier (DSB) Just after the write operation
|
||||
This will force the CPU to respect the sequence of instruction (no optimization).*/
|
||||
__DSB();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Program a half-word (16-bit) at a specified address.
|
||||
* @note This function must be used when the device voltage range is from
|
||||
* 2.1V to 3.6V.
|
||||
*
|
||||
* @note If an erase and a program operations are requested simultaneously,
|
||||
* the erase operation is performed before the program one.
|
||||
*
|
||||
* @param Address specifies the address to be programmed.
|
||||
* @param Data specifies the data to be programmed.
|
||||
* @retval None
|
||||
*/
|
||||
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_ADDRESS(Address));
|
||||
|
||||
/* If the previous operation is completed, proceed to program the new data */
|
||||
FLASH->CR &= CR_PSIZE_MASK;
|
||||
FLASH->CR |= FLASH_PSIZE_HALF_WORD;
|
||||
FLASH->CR |= FLASH_CR_PG;
|
||||
|
||||
*(__IO uint16_t*)Address = Data;
|
||||
|
||||
/* Data synchronous Barrier (DSB) Just after the write operation
|
||||
This will force the CPU to respect the sequence of instruction (no optimization).*/
|
||||
__DSB();
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Program byte (8-bit) at a specified address.
|
||||
* @note This function must be used when the device voltage range is from
|
||||
* 1.7V to 3.6V.
|
||||
*
|
||||
* @note If an erase and a program operations are requested simultaneously,
|
||||
* the erase operation is performed before the program one.
|
||||
*
|
||||
* @param Address specifies the address to be programmed.
|
||||
* @param Data specifies the data to be programmed.
|
||||
* @retval None
|
||||
*/
|
||||
static void FLASH_Program_Byte(uint32_t Address, uint8_t Data)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_ADDRESS(Address));
|
||||
|
||||
/* If the previous operation is completed, proceed to program the new data */
|
||||
FLASH->CR &= CR_PSIZE_MASK;
|
||||
FLASH->CR |= FLASH_PSIZE_BYTE;
|
||||
FLASH->CR |= FLASH_CR_PG;
|
||||
|
||||
*(__IO uint8_t*)Address = Data;
|
||||
|
||||
/* Data synchronous Barrier (DSB) Just after the write operation
|
||||
This will force the CPU to respect the sequence of instruction (no optimization).*/
|
||||
__DSB();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the specific FLASH error flag.
|
||||
* @retval None
|
||||
*/
|
||||
static void FLASH_SetErrorCode(void)
|
||||
{
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET)
|
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION;
|
||||
}
|
||||
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET)
|
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
|
||||
}
|
||||
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET)
|
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;
|
||||
}
|
||||
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGPERR) != RESET)
|
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_PGP;
|
||||
}
|
||||
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ERSERR) != RESET)
|
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_ERS;
|
||||
}
|
||||
|
||||
#if defined (FLASH_OPTCR2_PCROP)
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET)
|
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_RD;
|
||||
}
|
||||
#endif /* FLASH_OPTCR2_PCROP */
|
||||
|
||||
/* Clear error programming flags */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,527 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_gpio.c
|
||||
* @author MCD Application Team
|
||||
* @brief GPIO HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + IO operation functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### GPIO Peripheral features #####
|
||||
==============================================================================
|
||||
[..]
|
||||
Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
|
||||
port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
|
||||
in several modes:
|
||||
(+) Input mode
|
||||
(+) Analog mode
|
||||
(+) Output mode
|
||||
(+) Alternate function mode
|
||||
(+) External interrupt/event lines
|
||||
|
||||
[..]
|
||||
During and just after reset, the alternate functions and external interrupt
|
||||
lines are not active and the I/O ports are configured in input floating mode.
|
||||
|
||||
[..]
|
||||
All GPIO pins have weak internal pull-up and pull-down resistors, which can be
|
||||
activated or not.
|
||||
|
||||
[..]
|
||||
In Output or Alternate mode, each IO can be configured on open-drain or push-pull
|
||||
type and the IO speed can be selected depending on the VDD value.
|
||||
|
||||
[..]
|
||||
All ports have external interrupt/event capability. To use external interrupt
|
||||
lines, the port must be configured in input mode. All available GPIO pins are
|
||||
connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
|
||||
|
||||
[..]
|
||||
The external interrupt/event controller consists of up to 23 edge detectors
|
||||
(16 lines are connected to GPIO) for generating event/interrupt requests (each
|
||||
input line can be independently configured to select the type (interrupt or event)
|
||||
and the corresponding trigger event (rising or falling or both). Each line can
|
||||
also be masked independently.
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
|
||||
|
||||
(#) Configure the GPIO pin(s) using HAL_GPIO_Init().
|
||||
(++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
|
||||
(++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
|
||||
structure.
|
||||
(++) In case of Output or alternate function mode selection: the speed is
|
||||
configured through "Speed" member from GPIO_InitTypeDef structure.
|
||||
(++) In alternate mode is selection, the alternate function connected to the IO
|
||||
is configured through "Alternate" member from GPIO_InitTypeDef structure.
|
||||
(++) Analog mode is required when a pin is to be used as ADC channel
|
||||
or DAC output.
|
||||
(++) In case of external interrupt/event selection the "Mode" member from
|
||||
GPIO_InitTypeDef structure select the type (interrupt or event) and
|
||||
the corresponding trigger event (rising or falling or both).
|
||||
|
||||
(#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
|
||||
mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
|
||||
HAL_NVIC_EnableIRQ().
|
||||
|
||||
(#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
|
||||
|
||||
(#) To set/reset the level of a pin configured in output mode use
|
||||
HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
|
||||
|
||||
(#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
|
||||
|
||||
|
||||
(#) During and just after reset, the alternate functions are not
|
||||
active and the GPIO pins are configured in input floating mode (except JTAG
|
||||
pins).
|
||||
|
||||
(#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
|
||||
(PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
|
||||
priority over the GPIO function.
|
||||
|
||||
(#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
|
||||
general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
|
||||
The HSE has priority over the GPIO function.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO GPIO
|
||||
* @brief GPIO HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_GPIO_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @addtogroup GPIO_Private_Constants GPIO Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GPIO_NUMBER ((uint32_t)16U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This section provides functions allowing to initialize and de-initialize the GPIOs
|
||||
to be ready for use.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
|
||||
* @param GPIOx where x can be (A..K) to select the GPIO peripheral.
|
||||
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
|
||||
* the configuration information for the specified GPIO peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
||||
{
|
||||
uint32_t position = 0x00;
|
||||
uint32_t ioposition = 0x00;
|
||||
uint32_t iocurrent = 0x00;
|
||||
uint32_t temp = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
||||
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
||||
|
||||
/* Configure the port pins */
|
||||
for(position = 0; position < GPIO_NUMBER; position++)
|
||||
{
|
||||
/* Get the IO position */
|
||||
ioposition = ((uint32_t)0x01) << position;
|
||||
/* Get the current IO position */
|
||||
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
|
||||
|
||||
if(iocurrent == ioposition)
|
||||
{
|
||||
/*--------------------- GPIO Mode Configuration ------------------------*/
|
||||
/* In case of Output or Alternate function mode selection */
|
||||
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
|
||||
{
|
||||
/* Check the Speed parameter */
|
||||
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
|
||||
/* Configure the IO Speed */
|
||||
temp = GPIOx->OSPEEDR;
|
||||
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
|
||||
temp |= (GPIO_Init->Speed << (position * 2));
|
||||
GPIOx->OSPEEDR = temp;
|
||||
|
||||
/* Configure the IO Output Type */
|
||||
temp = GPIOx->OTYPER;
|
||||
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
|
||||
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
|
||||
GPIOx->OTYPER = temp;
|
||||
}
|
||||
|
||||
if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
|
||||
{
|
||||
/* Check the Pull parameter */
|
||||
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
||||
|
||||
/* Activate the Pull-up or Pull down resistor for the current IO */
|
||||
temp = GPIOx->PUPDR;
|
||||
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
|
||||
temp |= ((GPIO_Init->Pull) << (position * 2));
|
||||
GPIOx->PUPDR = temp;
|
||||
}
|
||||
|
||||
/* In case of Alternate function mode selection */
|
||||
if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
|
||||
{
|
||||
/* Check the Alternate function parameter */
|
||||
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
|
||||
|
||||
/* Configure Alternate function mapped with the current IO */
|
||||
temp = GPIOx->AFR[position >> 3];
|
||||
temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
|
||||
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
|
||||
GPIOx->AFR[position >> 3] = temp;
|
||||
}
|
||||
|
||||
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
|
||||
temp = GPIOx->MODER;
|
||||
temp &= ~(GPIO_MODER_MODER0 << (position * 2));
|
||||
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
|
||||
GPIOx->MODER = temp;
|
||||
|
||||
/*--------------------- EXTI Mode Configuration ------------------------*/
|
||||
/* Configure the External Interrupt or event for the current IO */
|
||||
if((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
|
||||
{
|
||||
/* Enable SYSCFG Clock */
|
||||
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
||||
|
||||
temp = SYSCFG->EXTICR[position >> 2];
|
||||
temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
|
||||
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
|
||||
SYSCFG->EXTICR[position >> 2] = temp;
|
||||
|
||||
/* Clear Rising Falling edge configuration */
|
||||
temp = EXTI->RTSR;
|
||||
temp &= ~((uint32_t)iocurrent);
|
||||
if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI->RTSR = temp;
|
||||
|
||||
temp = EXTI->FTSR;
|
||||
temp &= ~((uint32_t)iocurrent);
|
||||
if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI->FTSR = temp;
|
||||
|
||||
temp = EXTI->EMR;
|
||||
temp &= ~((uint32_t)iocurrent);
|
||||
if((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI->EMR = temp;
|
||||
|
||||
/* Clear EXTI line configuration */
|
||||
temp = EXTI->IMR;
|
||||
temp &= ~((uint32_t)iocurrent);
|
||||
if((GPIO_Init->Mode & EXTI_IT) != 0x00u)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI->IMR = temp;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief De-initializes the GPIOx peripheral registers to their default reset values.
|
||||
* @param GPIOx where x can be (A..K) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin specifies the port bit to be written.
|
||||
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
|
||||
{
|
||||
uint32_t position;
|
||||
uint32_t ioposition = 0x00;
|
||||
uint32_t iocurrent = 0x00;
|
||||
uint32_t tmp = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
||||
|
||||
/* Configure the port pins */
|
||||
for(position = 0; position < GPIO_NUMBER; position++)
|
||||
{
|
||||
/* Get the IO position */
|
||||
ioposition = ((uint32_t)0x01) << position;
|
||||
/* Get the current IO position */
|
||||
iocurrent = (GPIO_Pin) & ioposition;
|
||||
|
||||
if(iocurrent == ioposition)
|
||||
{
|
||||
/*------------------------- EXTI Mode Configuration --------------------*/
|
||||
tmp = SYSCFG->EXTICR[position >> 2];
|
||||
tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
|
||||
if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))))
|
||||
{
|
||||
/* Clear EXTI line configuration */
|
||||
EXTI->IMR &= ~((uint32_t)iocurrent);
|
||||
EXTI->EMR &= ~((uint32_t)iocurrent);
|
||||
|
||||
/* Clear Rising Falling edge configuration */
|
||||
EXTI->FTSR &= ~((uint32_t)iocurrent);
|
||||
EXTI->RTSR &= ~((uint32_t)iocurrent);
|
||||
|
||||
/* Configure the External Interrupt or event for the current IO */
|
||||
tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
|
||||
SYSCFG->EXTICR[position >> 2] &= ~tmp;
|
||||
}
|
||||
/*------------------------- GPIO Mode Configuration --------------------*/
|
||||
/* Configure IO Direction in Input Floating Mode */
|
||||
GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2));
|
||||
|
||||
/* Configure the default Alternate Function in current IO */
|
||||
GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
|
||||
|
||||
/* Deactivate the Pull-up and Pull-down resistor for the current IO */
|
||||
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
|
||||
|
||||
/* Configure the default value IO Output Type */
|
||||
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;
|
||||
|
||||
/* Configure the default value for IO Speed */
|
||||
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
|
||||
* @brief GPIO Read and Write
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Reads the specified input port pin.
|
||||
* @param GPIOx where x can be (A..K) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin specifies the port bit to read.
|
||||
* This parameter can be GPIO_PIN_x where x can be (0..15).
|
||||
* @retval The input port pin value.
|
||||
*/
|
||||
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
GPIO_PinState bitstatus;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
|
||||
{
|
||||
bitstatus = GPIO_PIN_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = GPIO_PIN_RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets or clears the selected data port bit.
|
||||
*
|
||||
* @note This function uses GPIOx_BSRR register to allow atomic read/modify
|
||||
* accesses. In this way, there is no risk of an IRQ occurring between
|
||||
* the read and the modify access.
|
||||
*
|
||||
* @param GPIOx where x can be (A..K) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin specifies the port bit to be written.
|
||||
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
|
||||
* @param PinState specifies the value to be written to the selected bit.
|
||||
* This parameter can be one of the GPIO_PinState enum values:
|
||||
* @arg GPIO_PIN_RESET: to clear the port pin
|
||||
* @arg GPIO_PIN_SET: to set the port pin
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
assert_param(IS_GPIO_PIN_ACTION(PinState));
|
||||
|
||||
if(PinState != GPIO_PIN_RESET)
|
||||
{
|
||||
GPIOx->BSRR = GPIO_Pin;
|
||||
}
|
||||
else
|
||||
{
|
||||
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Toggles the specified GPIO pins.
|
||||
* @param GPIOx Where x can be (A..I) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin Specifies the pins to be toggled.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
uint32_t odr;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
/* get current Output Data Register value */
|
||||
odr = GPIOx->ODR;
|
||||
|
||||
/* Set selected pins that were at low level, and reset ones that were high */
|
||||
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Locks GPIO Pins configuration registers.
|
||||
* @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
|
||||
* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
|
||||
* @note The configuration of the locked GPIO pins can no longer be modified
|
||||
* until the next reset.
|
||||
* @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F7 family
|
||||
* @param GPIO_Pin specifies the port bit to be locked.
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
__IO uint32_t tmp = GPIO_LCKR_LCKK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
/* Apply lock key write sequence */
|
||||
tmp |= GPIO_Pin;
|
||||
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
|
||||
GPIOx->LCKR = tmp;
|
||||
/* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
|
||||
GPIOx->LCKR = GPIO_Pin;
|
||||
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
|
||||
GPIOx->LCKR = tmp;
|
||||
/* Read LCKR register. This read is mandatory to complete key lock sequence */
|
||||
tmp = GPIOx->LCKR;
|
||||
|
||||
/* Read again in order to confirm lock is active */
|
||||
if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
|
||||
{
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles EXTI interrupt request.
|
||||
* @param GPIO_Pin Specifies the pins connected EXTI line
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
|
||||
{
|
||||
/* EXTI line interrupt detected */
|
||||
if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
|
||||
{
|
||||
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
|
||||
HAL_GPIO_EXTI_Callback(GPIO_Pin);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief EXTI line detection callbacks.
|
||||
* @param GPIO_Pin Specifies the pins connected EXTI line
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(GPIO_Pin);
|
||||
|
||||
/* NOTE: This function Should not be modified, when the callback is needed,
|
||||
the HAL_GPIO_EXTI_Callback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_GPIO_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,270 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_i2c_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief I2C Extended HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of I2C Extended peripheral:
|
||||
* + Filter Mode Functions
|
||||
* + FastModePlus Functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### I2C peripheral Extended features #####
|
||||
==============================================================================
|
||||
|
||||
[..] Comparing to other previous devices, the I2C interface for STM32F7xx
|
||||
devices contains the following additional features
|
||||
|
||||
(+) Possibility to disable or enable Analog Noise Filter
|
||||
(+) Use of a configured Digital Noise Filter
|
||||
(+) Disable or enable Fast Mode Plus
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..] This driver provides functions to:
|
||||
(#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
|
||||
(#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
|
||||
(#) Configure the enable or disable of fast mode plus driving capability using the functions :
|
||||
(++) HAL_I2CEx_EnableFastModePlus()
|
||||
(++) HAL_I2CEx_DisableFastModePlus()
|
||||
@endverbatim
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx I2CEx
|
||||
* @brief I2C Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_I2C_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
|
||||
* @brief Filter Mode Functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Filter Mode Functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure Noise Filters
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configure I2C Analog noise filter.
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2Cx peripheral.
|
||||
* @param AnalogFilter New state of the Analog filter.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
||||
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
|
||||
|
||||
if (hi2c->State == HAL_I2C_STATE_READY)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_BUSY;
|
||||
|
||||
/* Disable the selected I2C peripheral */
|
||||
__HAL_I2C_DISABLE(hi2c);
|
||||
|
||||
/* Reset I2Cx ANOFF bit */
|
||||
hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
|
||||
|
||||
/* Set analog filter bit*/
|
||||
hi2c->Instance->CR1 |= AnalogFilter;
|
||||
|
||||
__HAL_I2C_ENABLE(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure I2C Digital noise filter.
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2Cx peripheral.
|
||||
* @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
|
||||
{
|
||||
uint32_t tmpreg;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
||||
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
|
||||
|
||||
if (hi2c->State == HAL_I2C_STATE_READY)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_BUSY;
|
||||
|
||||
/* Disable the selected I2C peripheral */
|
||||
__HAL_I2C_DISABLE(hi2c);
|
||||
|
||||
/* Get the old register value */
|
||||
tmpreg = hi2c->Instance->CR1;
|
||||
|
||||
/* Reset I2Cx DNF bits [11:8] */
|
||||
tmpreg &= ~(I2C_CR1_DNF);
|
||||
|
||||
/* Set I2Cx DNF coefficient */
|
||||
tmpreg |= DigitalFilter << 8U;
|
||||
|
||||
/* Store the new register value */
|
||||
hi2c->Instance->CR1 = tmpreg;
|
||||
|
||||
__HAL_I2C_ENABLE(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#if (defined(SYSCFG_PMC_I2C_PB6_FMP) || defined(SYSCFG_PMC_I2C_PB7_FMP)) || (defined(SYSCFG_PMC_I2C_PB8_FMP) || defined(SYSCFG_PMC_I2C_PB9_FMP)) || (defined(SYSCFG_PMC_I2C1_FMP)) || (defined(SYSCFG_PMC_I2C2_FMP)) || defined(SYSCFG_PMC_I2C3_FMP) || defined(SYSCFG_PMC_I2C4_FMP)
|
||||
|
||||
/** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
|
||||
* @brief Fast Mode Plus Functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Fast Mode Plus Functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure Fast Mode Plus
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the I2C fast mode plus driving capability.
|
||||
* @param ConfigFastModePlus Selects the pin.
|
||||
* This parameter can be one of the @ref I2CEx_FastModePlus values
|
||||
* @note For I2C1, fast mode plus driving capability can be enabled on all selected
|
||||
* I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
|
||||
* on each one of the following pins PB6, PB7, PB8 and PB9.
|
||||
* @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
|
||||
* can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
|
||||
* @note For all I2C2 pins fast mode plus driving capability can be enabled
|
||||
* only by using I2C_FASTMODEPLUS_I2C2 parameter.
|
||||
* @note For all I2C3 pins fast mode plus driving capability can be enabled
|
||||
* only by using I2C_FASTMODEPLUS_I2C3 parameter.
|
||||
* @note For all I2C4 pins fast mode plus driving capability can be enabled
|
||||
* only by using I2C_FASTMODEPLUS_I2C4 parameter.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
|
||||
|
||||
/* Enable SYSCFG clock */
|
||||
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
||||
|
||||
/* Enable fast mode plus driving capability for selected pin */
|
||||
SET_BIT(SYSCFG->PMC, (uint32_t)ConfigFastModePlus);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the I2C fast mode plus driving capability.
|
||||
* @param ConfigFastModePlus Selects the pin.
|
||||
* This parameter can be one of the @ref I2CEx_FastModePlus values
|
||||
* @note For I2C1, fast mode plus driving capability can be disabled on all selected
|
||||
* I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
|
||||
* on each one of the following pins PB6, PB7, PB8 and PB9.
|
||||
* @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
|
||||
* can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
|
||||
* @note For all I2C2 pins fast mode plus driving capability can be disabled
|
||||
* only by using I2C_FASTMODEPLUS_I2C2 parameter.
|
||||
* @note For all I2C3 pins fast mode plus driving capability can be disabled
|
||||
* only by using I2C_FASTMODEPLUS_I2C3 parameter.
|
||||
* @note For all I2C4 pins fast mode plus driving capability can be disabled
|
||||
* only by using I2C_FASTMODEPLUS_I2C4 parameter.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
|
||||
|
||||
/* Enable SYSCFG clock */
|
||||
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
||||
|
||||
/* Disable fast mode plus driving capability for selected pin */
|
||||
CLEAR_BIT(SYSCFG->PMC, (uint32_t)ConfigFastModePlus);
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* Fast Mode Plus Availability */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_I2C_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -0,0 +1,597 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_pwr.c
|
||||
* @author MCD Application Team
|
||||
* @brief PWR HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Power Controller (PWR) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + Peripheral Control functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR PWR
|
||||
* @brief PWR HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @addtogroup PWR_Private_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
|
||||
* @{
|
||||
*/
|
||||
#define PVD_MODE_IT ((uint32_t)0x00010000U)
|
||||
#define PVD_MODE_EVT ((uint32_t)0x00020000U)
|
||||
#define PVD_RISING_EDGE ((uint32_t)0x00000001U)
|
||||
#define PVD_FALLING_EDGE ((uint32_t)0x00000002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask
|
||||
* @{
|
||||
*/
|
||||
#define PWR_EWUP_MASK ((uint32_t)0x00003F00)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWR_Exported_Functions PWR Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and de-initialization functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
After reset, the backup domain (RTC registers, RTC backup data
|
||||
registers and backup SRAM) is protected against possible unwanted
|
||||
write accesses.
|
||||
To enable access to the RTC Domain and RTC registers, proceed as follows:
|
||||
(+) Enable the Power Controller (PWR) APB1 interface clock using the
|
||||
__HAL_RCC_PWR_CLK_ENABLE() macro.
|
||||
(+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the HAL PWR peripheral registers to their default reset values.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DeInit(void)
|
||||
{
|
||||
__HAL_RCC_PWR_FORCE_RESET();
|
||||
__HAL_RCC_PWR_RELEASE_RESET();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables access to the backup domain (RTC registers, RTC
|
||||
* backup data registers and backup SRAM).
|
||||
* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
|
||||
* Backup Domain Access should be kept enabled.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnableBkUpAccess(void)
|
||||
{
|
||||
/* Enable access to RTC and backup registers */
|
||||
SET_BIT(PWR->CR1, PWR_CR1_DBP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables access to the backup domain (RTC registers, RTC
|
||||
* backup data registers and backup SRAM).
|
||||
* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
|
||||
* Backup Domain Access should be kept enabled.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisableBkUpAccess(void)
|
||||
{
|
||||
/* Disable access to RTC and backup registers */
|
||||
CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief Low Power modes configuration functions
|
||||
*
|
||||
@verbatim
|
||||
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
|
||||
*** PVD configuration ***
|
||||
=========================
|
||||
[..]
|
||||
(+) The PVD is used to monitor the VDD power supply by comparing it to a
|
||||
threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
|
||||
(+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
|
||||
than the PVD threshold. This event is internally connected to the EXTI
|
||||
line16 and can generate an interrupt if enabled. This is done through
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
|
||||
(+) The PVD is stopped in Standby mode.
|
||||
|
||||
*** Wake-up pin configuration ***
|
||||
================================
|
||||
[..]
|
||||
(+) Wake-up pin is used to wake up the system from Standby mode. This pin is
|
||||
forced in input pull-down configuration and is active on rising edges.
|
||||
(+) There are up to 6 Wake-up pin in the STM32F7 devices family
|
||||
|
||||
*** Low Power modes configuration ***
|
||||
=====================================
|
||||
[..]
|
||||
The devices feature 3 low-power modes:
|
||||
(+) Sleep mode: Cortex-M7 core stopped, peripherals kept running.
|
||||
(+) Stop mode: all clocks are stopped, regulator running, regulator
|
||||
in low power mode
|
||||
(+) Standby mode: 1.2V domain powered off.
|
||||
|
||||
*** Sleep mode ***
|
||||
==================
|
||||
[..]
|
||||
(+) Entry:
|
||||
The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI)
|
||||
functions with
|
||||
(++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
|
||||
(++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
|
||||
|
||||
-@@- The Regulator parameter is not used for the STM32F7 family
|
||||
and is kept as parameter just to maintain compatibility with the
|
||||
lower power families (STM32L).
|
||||
(+) Exit:
|
||||
Any peripheral interrupt acknowledged by the nested vectored interrupt
|
||||
controller (NVIC) can wake up the device from Sleep mode.
|
||||
|
||||
*** Stop mode ***
|
||||
=================
|
||||
[..]
|
||||
In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
|
||||
and the HSE RC oscillators are disabled. Internal SRAM and register contents
|
||||
are preserved.
|
||||
The voltage regulator can be configured either in normal or low-power mode.
|
||||
To minimize the consumption In Stop mode, FLASH can be powered off before
|
||||
entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function.
|
||||
It can be switched on again by software after exiting the Stop mode using
|
||||
the HAL_PWREx_DisableFlashPowerDown() function.
|
||||
|
||||
(+) Entry:
|
||||
The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON)
|
||||
function with:
|
||||
(++) Main regulator ON.
|
||||
(++) Low Power regulator ON.
|
||||
(+) Exit:
|
||||
Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
|
||||
|
||||
*** Standby mode ***
|
||||
====================
|
||||
[..]
|
||||
(+)
|
||||
The Standby mode allows to achieve the lowest power consumption. It is based
|
||||
on the Cortex-M7 deep sleep mode, with the voltage regulator disabled.
|
||||
The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and
|
||||
the HSE oscillator are also switched off. SRAM and register contents are lost
|
||||
except for the RTC registers, RTC backup registers, backup SRAM and Standby
|
||||
circuitry.
|
||||
|
||||
The voltage regulator is OFF.
|
||||
|
||||
(++) Entry:
|
||||
(+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
|
||||
(++) Exit:
|
||||
(+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC
|
||||
wakeup, tamper event, time stamp event, external reset in NRST pin, IWDG reset.
|
||||
|
||||
*** Auto-wakeup (AWU) from low-power mode ***
|
||||
=============================================
|
||||
[..]
|
||||
|
||||
(+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
|
||||
Wakeup event, a tamper event or a time-stamp event, without depending on
|
||||
an external interrupt (Auto-wakeup mode).
|
||||
|
||||
(+) RTC auto-wakeup (AWU) from the Stop and Standby modes
|
||||
|
||||
(++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
|
||||
configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
|
||||
|
||||
(++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
|
||||
is necessary to configure the RTC to detect the tamper or time stamp event using the
|
||||
HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
|
||||
|
||||
(++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
|
||||
configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
|
||||
* @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration
|
||||
* information for the PVD.
|
||||
* @note Refer to the electrical characteristics of your device datasheet for
|
||||
* more details about the voltage threshold corresponding to each
|
||||
* detection level.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
|
||||
assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
|
||||
|
||||
/* Set PLS[7:5] bits according to PVDLevel value */
|
||||
MODIFY_REG(PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel);
|
||||
|
||||
/* Clear any previous config. Keep it clear if no event or IT mode is selected */
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_EVENT();
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_IT();
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
|
||||
|
||||
/* Configure interrupt mode */
|
||||
if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
|
||||
{
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_IT();
|
||||
}
|
||||
|
||||
/* Configure event mode */
|
||||
if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
|
||||
{
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_EVENT();
|
||||
}
|
||||
|
||||
/* Configure the edge */
|
||||
if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
|
||||
{
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
|
||||
}
|
||||
|
||||
if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
|
||||
{
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the Power Voltage Detector(PVD).
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnablePVD(void)
|
||||
{
|
||||
/* Enable the power voltage detector */
|
||||
SET_BIT(PWR->CR1, PWR_CR1_PVDE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the Power Voltage Detector(PVD).
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisablePVD(void)
|
||||
{
|
||||
/* Disable the power voltage detector */
|
||||
CLEAR_BIT(PWR->CR1, PWR_CR1_PVDE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the WakeUp PINx functionality.
|
||||
* @param WakeUpPinPolarity Specifies which Wake-Up pin to enable.
|
||||
* This parameter can be one of the following legacy values, which sets the default polarity:
|
||||
* detection on high level (rising edge):
|
||||
* @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6
|
||||
* or one of the following value where the user can explicitly states the enabled pin and
|
||||
* the chosen polarity
|
||||
* @arg PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
|
||||
* @arg PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
|
||||
* @arg PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
|
||||
* @arg PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
|
||||
* @arg PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
|
||||
* @arg PWR_WAKEUP_PIN6_HIGH or PWR_WAKEUP_PIN6_LOW
|
||||
* @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
|
||||
{
|
||||
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
|
||||
|
||||
/* Enable wake-up pin */
|
||||
SET_BIT(PWR->CSR2, (PWR_EWUP_MASK & WakeUpPinPolarity));
|
||||
|
||||
/* Specifies the Wake-Up pin polarity for the event detection
|
||||
(rising or falling edge) */
|
||||
MODIFY_REG(PWR->CR2, (PWR_EWUP_MASK & WakeUpPinPolarity), (WakeUpPinPolarity >> 0x06));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the WakeUp PINx functionality.
|
||||
* @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_WAKEUP_PIN1
|
||||
* @arg PWR_WAKEUP_PIN2
|
||||
* @arg PWR_WAKEUP_PIN3
|
||||
* @arg PWR_WAKEUP_PIN4
|
||||
* @arg PWR_WAKEUP_PIN5
|
||||
* @arg PWR_WAKEUP_PIN6
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
|
||||
{
|
||||
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
|
||||
|
||||
CLEAR_BIT(PWR->CSR2, WakeUpPinx);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters Sleep mode.
|
||||
*
|
||||
* @note In Sleep mode, all I/O pins keep the same state as in Run mode.
|
||||
*
|
||||
* @note In Sleep mode, the systick is stopped to avoid exit from this mode with
|
||||
* systick interrupt when used as time base for Timeout
|
||||
*
|
||||
* @param Regulator Specifies the regulator state in SLEEP mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
|
||||
* @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
|
||||
* @note This parameter is not used for the STM32F7 family and is kept as parameter
|
||||
* just to maintain compatibility with the lower power families.
|
||||
* @param SLEEPEntry Specifies if SLEEP mode in entered with WFI or WFE instruction.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
|
||||
* @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_REGULATOR(Regulator));
|
||||
assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
|
||||
|
||||
/* Clear SLEEPDEEP bit of Cortex System Control Register */
|
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||||
|
||||
/* Ensure that all instructions done before entering SLEEP mode */
|
||||
__DSB();
|
||||
__ISB();
|
||||
|
||||
/* Select SLEEP mode entry -------------------------------------------------*/
|
||||
if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
|
||||
{
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Request Wait For Event */
|
||||
__SEV();
|
||||
__WFE();
|
||||
__WFE();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters Stop mode.
|
||||
* @note In Stop mode, all I/O pins keep the same state as in Run mode.
|
||||
* @note When exiting Stop mode by issuing an interrupt or a wakeup event,
|
||||
* the HSI RC oscillator is selected as system clock.
|
||||
* @note When the voltage regulator operates in low power mode, an additional
|
||||
* startup delay is incurred when waking up from Stop mode.
|
||||
* By keeping the internal regulator ON during Stop mode, the consumption
|
||||
* is higher although the startup time is reduced.
|
||||
* @param Regulator Specifies the regulator state in Stop mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
|
||||
* @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
|
||||
* @param STOPEntry Specifies if Stop mode in entered with WFI or WFE instruction.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
|
||||
* @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_REGULATOR(Regulator));
|
||||
assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
|
||||
|
||||
/* Select the regulator state in Stop mode ---------------------------------*/
|
||||
tmpreg = PWR->CR1;
|
||||
/* Clear PDDS and LPDS bits */
|
||||
tmpreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS);
|
||||
|
||||
/* Set LPDS, MRLVDS and LPLVDS bits according to Regulator value */
|
||||
tmpreg |= Regulator;
|
||||
|
||||
/* Store the new value */
|
||||
PWR->CR1 = tmpreg;
|
||||
|
||||
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
||||
|
||||
/* Ensure that all instructions done before entering STOP mode */
|
||||
__DSB();
|
||||
__ISB();
|
||||
|
||||
/* Select Stop mode entry --------------------------------------------------*/
|
||||
if(STOPEntry == PWR_STOPENTRY_WFI)
|
||||
{
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Request Wait For Event */
|
||||
__SEV();
|
||||
__WFE();
|
||||
__WFE();
|
||||
}
|
||||
/* Reset SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters Standby mode.
|
||||
* @note In Standby mode, all I/O pins are high impedance except for:
|
||||
* - Reset pad (still available)
|
||||
* - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC
|
||||
* Alarm out, or RTC clock calibration out.
|
||||
* - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.
|
||||
* - WKUP pins if enabled.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnterSTANDBYMode(void)
|
||||
{
|
||||
/* Select Standby mode */
|
||||
PWR->CR1 |= PWR_CR1_PDDS;
|
||||
|
||||
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
||||
|
||||
/* This option is used to ensure that store operations are completed */
|
||||
#if defined ( __CC_ARM)
|
||||
__force_stores();
|
||||
#endif
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles the PWR PVD interrupt request.
|
||||
* @note This API should be called under the PVD_IRQHandler().
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_PVD_IRQHandler(void)
|
||||
{
|
||||
/* Check PWR Exti flag */
|
||||
if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
|
||||
{
|
||||
/* PWR PVD interrupt user callback */
|
||||
HAL_PWR_PVDCallback();
|
||||
|
||||
/* Clear PWR Exti pending bit */
|
||||
__HAL_PWR_PVD_EXTI_CLEAR_FLAG();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief PWR PVD interrupt callback
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_PWR_PVDCallback(void)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_PWR_PVDCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
|
||||
* @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
|
||||
* re-enters SLEEP mode when an interruption handling is over.
|
||||
* Setting this bit is useful when the processor is expected to run only on
|
||||
* interruptions handling.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnableSleepOnExit(void)
|
||||
{
|
||||
/* Set SLEEPONEXIT bit of Cortex System Control Register */
|
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
|
||||
* @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
|
||||
* re-enters SLEEP mode when an interruption handling is over.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisableSleepOnExit(void)
|
||||
{
|
||||
/* Clear SLEEPONEXIT bit of Cortex System Control Register */
|
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables CORTEX M4 SEVONPEND bit.
|
||||
* @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
|
||||
* WFE to wake up when an interrupt moves from inactive to pended.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnableSEVOnPend(void)
|
||||
{
|
||||
/* Set SEVONPEND bit of Cortex System Control Register */
|
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables CORTEX M4 SEVONPEND bit.
|
||||
* @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
|
||||
* WFE to wake up when an interrupt moves from inactive to pended.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisableSEVOnPend(void)
|
||||
{
|
||||
/* Clear SEVONPEND bit of Cortex System Control Register */
|
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@ -0,0 +1,552 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_pwr_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief Extended PWR HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of PWR extension peripheral:
|
||||
* + Peripheral Extended features functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx PWREx
|
||||
* @brief PWR HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @addtogroup PWREx_Private_Constants
|
||||
* @{
|
||||
*/
|
||||
#define PWR_OVERDRIVE_TIMEOUT_VALUE 1000
|
||||
#define PWR_UDERDRIVE_TIMEOUT_VALUE 1000
|
||||
#define PWR_BKPREG_TIMEOUT_VALUE 1000
|
||||
#define PWR_VOSRDY_TIMEOUT_VALUE 1000
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup PWREx_Exported_Functions PWREx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions
|
||||
* @brief Peripheral Extended features functions
|
||||
*
|
||||
@verbatim
|
||||
|
||||
===============================================================================
|
||||
##### Peripheral extended features functions #####
|
||||
===============================================================================
|
||||
|
||||
*** Main and Backup Regulators configuration ***
|
||||
================================================
|
||||
[..]
|
||||
(+) The backup domain includes 4 Kbytes of backup SRAM accessible only from
|
||||
the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is
|
||||
retained even in Standby or VBAT mode when the low power backup regulator
|
||||
is enabled. It can be considered as an internal EEPROM when VBAT is
|
||||
always present. You can use the HAL_PWREx_EnableBkUpReg() function to
|
||||
enable the low power backup regulator.
|
||||
|
||||
(+) When the backup domain is supplied by VDD (analog switch connected to VDD)
|
||||
the backup SRAM is powered from VDD which replaces the VBAT power supply to
|
||||
save battery life.
|
||||
|
||||
(+) The backup SRAM is not mass erased by a tamper event. It is read
|
||||
protected to prevent confidential data, such as cryptographic private
|
||||
key, from being accessed. The backup SRAM can be erased only through
|
||||
the Flash interface when a protection level change from level 1 to
|
||||
level 0 is requested.
|
||||
-@- Refer to the description of Read protection (RDP) in the Flash
|
||||
programming manual.
|
||||
|
||||
(+) The main internal regulator can be configured to have a tradeoff between
|
||||
performance and power consumption when the device does not operate at
|
||||
the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG()
|
||||
macro which configure VOS bit in PWR_CR register
|
||||
|
||||
Refer to the product datasheets for more details.
|
||||
|
||||
*** FLASH Power Down configuration ****
|
||||
=======================================
|
||||
[..]
|
||||
(+) By setting the FPDS bit in the PWR_CR register by using the
|
||||
HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power
|
||||
down mode when the device enters Stop mode. When the Flash memory
|
||||
is in power down mode, an additional startup delay is incurred when
|
||||
waking up from Stop mode.
|
||||
|
||||
*** Over-Drive and Under-Drive configuration ****
|
||||
=================================================
|
||||
[..]
|
||||
(+) In Run mode: the main regulator has 2 operating modes available:
|
||||
(++) Normal mode: The CPU and core logic operate at maximum frequency at a given
|
||||
voltage scaling (scale 1, scale 2 or scale 3)
|
||||
(++) Over-drive mode: This mode allows the CPU and the core logic to operate at a
|
||||
higher frequency than the normal mode for a given voltage scaling (scale 1,
|
||||
scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and
|
||||
disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow
|
||||
the sequence described in Reference manual.
|
||||
|
||||
(+) In Stop mode: the main regulator or low power regulator supplies a low power
|
||||
voltage to the 1.2V domain, thus preserving the content of registers
|
||||
and internal SRAM. 2 operating modes are available:
|
||||
(++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only
|
||||
available when the main regulator or the low power regulator is used in Scale 3 or
|
||||
low voltage mode.
|
||||
(++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only
|
||||
available when the main regulator or the low power regulator is in low voltage mode.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables the Backup Regulator.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)
|
||||
{
|
||||
uint32_t tickstart = 0;
|
||||
|
||||
/* Enable Backup regulator */
|
||||
PWR->CSR1 |= PWR_CSR1_BRE;
|
||||
|
||||
/* Workaround for the following hardware bug: */
|
||||
/* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */
|
||||
PWR->CSR1 |= PWR_CSR1_EIWUP;
|
||||
|
||||
/* Get tick */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait till Backup regulator ready flag is set */
|
||||
while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET)
|
||||
{
|
||||
if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the Backup Regulator.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)
|
||||
{
|
||||
uint32_t tickstart = 0;
|
||||
|
||||
/* Disable Backup regulator */
|
||||
PWR->CSR1 &= (uint32_t)~((uint32_t)PWR_CSR1_BRE);
|
||||
|
||||
/* Workaround for the following hardware bug: */
|
||||
/* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */
|
||||
PWR->CSR1 |= PWR_CSR1_EIWUP;
|
||||
|
||||
/* Get tick */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait till Backup regulator ready flag is set */
|
||||
while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET)
|
||||
{
|
||||
if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the Flash Power Down in Stop mode.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWREx_EnableFlashPowerDown(void)
|
||||
{
|
||||
/* Enable the Flash Power Down */
|
||||
PWR->CR1 |= PWR_CR1_FPDS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the Flash Power Down in Stop mode.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWREx_DisableFlashPowerDown(void)
|
||||
{
|
||||
/* Disable the Flash Power Down */
|
||||
PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_FPDS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables Main Regulator low voltage mode.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWREx_EnableMainRegulatorLowVoltage(void)
|
||||
{
|
||||
/* Enable Main regulator low voltage */
|
||||
PWR->CR1 |= PWR_CR1_MRUDS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables Main Regulator low voltage mode.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWREx_DisableMainRegulatorLowVoltage(void)
|
||||
{
|
||||
/* Disable Main regulator low voltage */
|
||||
PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_MRUDS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables Low Power Regulator low voltage mode.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWREx_EnableLowRegulatorLowVoltage(void)
|
||||
{
|
||||
/* Enable low power regulator */
|
||||
PWR->CR1 |= PWR_CR1_LPUDS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables Low Power Regulator low voltage mode.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWREx_DisableLowRegulatorLowVoltage(void)
|
||||
{
|
||||
/* Disable low power regulator */
|
||||
PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_LPUDS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Activates the Over-Drive mode.
|
||||
* @note This mode allows the CPU and the core logic to operate at a higher frequency
|
||||
* than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
|
||||
* @note It is recommended to enter or exit Over-drive mode when the application is not running
|
||||
* critical tasks and when the system clock source is either HSI or HSE.
|
||||
* During the Over-drive switch activation, no peripheral clocks should be enabled.
|
||||
* The peripheral clocks must be enabled once the Over-drive mode is activated.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void)
|
||||
{
|
||||
uint32_t tickstart = 0;
|
||||
|
||||
__HAL_RCC_PWR_CLK_ENABLE();
|
||||
|
||||
/* Enable the Over-drive to extend the clock frequency to 216 MHz */
|
||||
__HAL_PWR_OVERDRIVE_ENABLE();
|
||||
|
||||
/* Get tick */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
|
||||
{
|
||||
if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
/* Enable the Over-drive switch */
|
||||
__HAL_PWR_OVERDRIVESWITCHING_ENABLE();
|
||||
|
||||
/* Get tick */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
|
||||
{
|
||||
if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Deactivates the Over-Drive mode.
|
||||
* @note This mode allows the CPU and the core logic to operate at a higher frequency
|
||||
* than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
|
||||
* @note It is recommended to enter or exit Over-drive mode when the application is not running
|
||||
* critical tasks and when the system clock source is either HSI or HSE.
|
||||
* During the Over-drive switch activation, no peripheral clocks should be enabled.
|
||||
* The peripheral clocks must be enabled once the Over-drive mode is activated.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void)
|
||||
{
|
||||
uint32_t tickstart = 0;
|
||||
|
||||
__HAL_RCC_PWR_CLK_ENABLE();
|
||||
|
||||
/* Disable the Over-drive switch */
|
||||
__HAL_PWR_OVERDRIVESWITCHING_DISABLE();
|
||||
|
||||
/* Get tick */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
|
||||
{
|
||||
if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
/* Disable the Over-drive */
|
||||
__HAL_PWR_OVERDRIVE_DISABLE();
|
||||
|
||||
/* Get tick */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
|
||||
{
|
||||
if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters in Under-Drive STOP mode.
|
||||
*
|
||||
* @note This mode can be selected only when the Under-Drive is already active
|
||||
*
|
||||
* @note This mode is enabled only with STOP low power mode.
|
||||
* In this mode, the 1.2V domain is preserved in reduced leakage mode. This
|
||||
* mode is only available when the main regulator or the low power regulator
|
||||
* is in low voltage mode
|
||||
*
|
||||
* @note If the Under-drive mode was enabled, it is automatically disabled after
|
||||
* exiting Stop mode.
|
||||
* When the voltage regulator operates in Under-drive mode, an additional
|
||||
* startup delay is induced when waking up from Stop mode.
|
||||
*
|
||||
* @note In Stop mode, all I/O pins keep the same state as in Run mode.
|
||||
*
|
||||
* @note When exiting Stop mode by issuing an interrupt or a wakeup event,
|
||||
* the HSI RC oscillator is selected as system clock.
|
||||
*
|
||||
* @note When the voltage regulator operates in low power mode, an additional
|
||||
* startup delay is incurred when waking up from Stop mode.
|
||||
* By keeping the internal regulator ON during Stop mode, the consumption
|
||||
* is higher although the startup time is reduced.
|
||||
*
|
||||
* @param Regulator specifies the regulator state in STOP mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_MAINREGULATOR_UNDERDRIVE_ON: Main Regulator in under-drive mode
|
||||
* and Flash memory in power-down when the device is in Stop under-drive mode
|
||||
* @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON: Low Power Regulator in under-drive mode
|
||||
* and Flash memory in power-down when the device is in Stop under-drive mode
|
||||
* @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction
|
||||
* @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction
|
||||
* @retval None
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
|
||||
{
|
||||
uint32_t tempreg = 0;
|
||||
uint32_t tickstart = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator));
|
||||
assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
|
||||
|
||||
/* Enable Power ctrl clock */
|
||||
__HAL_RCC_PWR_CLK_ENABLE();
|
||||
/* Enable the Under-drive Mode ---------------------------------------------*/
|
||||
/* Clear Under-drive flag */
|
||||
__HAL_PWR_CLEAR_ODRUDR_FLAG();
|
||||
|
||||
/* Enable the Under-drive */
|
||||
__HAL_PWR_UNDERDRIVE_ENABLE();
|
||||
|
||||
/* Get tick */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait for UnderDrive mode is ready */
|
||||
while(__HAL_PWR_GET_FLAG(PWR_FLAG_UDRDY))
|
||||
{
|
||||
if((HAL_GetTick() - tickstart ) > PWR_UDERDRIVE_TIMEOUT_VALUE)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
/* Select the regulator state in STOP mode ---------------------------------*/
|
||||
tempreg = PWR->CR1;
|
||||
/* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */
|
||||
tempreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS | PWR_CR1_LPUDS | PWR_CR1_MRUDS);
|
||||
|
||||
/* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */
|
||||
tempreg |= Regulator;
|
||||
|
||||
/* Store the new value */
|
||||
PWR->CR1 = tempreg;
|
||||
|
||||
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
||||
|
||||
/* Select STOP mode entry --------------------------------------------------*/
|
||||
if(STOPEntry == PWR_SLEEPENTRY_WFI)
|
||||
{
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Request Wait For Event */
|
||||
__WFE();
|
||||
}
|
||||
/* Reset SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns Voltage Scaling Range.
|
||||
* @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1, PWR_REGULATOR_VOLTAGE_SCALE2 or
|
||||
* PWR_REGULATOR_VOLTAGE_SCALE3)PWR_REGULATOR_VOLTAGE_SCALE1
|
||||
*/
|
||||
uint32_t HAL_PWREx_GetVoltageRange(void)
|
||||
{
|
||||
return (PWR->CR1 & PWR_CR1_VOS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the main internal regulator output voltage.
|
||||
* @param VoltageScaling specifies the regulator output voltage to achieve
|
||||
* a tradeoff between performance and power consumption.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
|
||||
* typical output voltage at 1.4 V,
|
||||
* system frequency up to 216 MHz.
|
||||
* @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,
|
||||
* typical output voltage at 1.2 V,
|
||||
* system frequency up to 180 MHz.
|
||||
* @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 2 mode,
|
||||
* typical output voltage at 1.00 V,
|
||||
* system frequency up to 151 MHz.
|
||||
* @note To update the system clock frequency(SYSCLK):
|
||||
* - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig().
|
||||
* - Call the HAL_RCC_OscConfig() to configure the PLL.
|
||||
* - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale.
|
||||
* - Set the new system clock frequency using the HAL_RCC_ClockConfig().
|
||||
* @note The scale can be modified only when the HSI or HSE clock source is selected
|
||||
* as system clock source, otherwise the API returns HAL_ERROR.
|
||||
* @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits
|
||||
* value in the PWR_CR1 register are not taken in account.
|
||||
* @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2.
|
||||
* @note The new voltage scale is active only when the PLL is ON.
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
|
||||
{
|
||||
uint32_t tickstart = 0;
|
||||
|
||||
assert_param(IS_PWR_REGULATOR_VOLTAGE(VoltageScaling));
|
||||
|
||||
/* Enable Power ctrl clock */
|
||||
__HAL_RCC_PWR_CLK_ENABLE();
|
||||
|
||||
/* Check if the PLL is used as system clock or not */
|
||||
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
|
||||
{
|
||||
/* Disable the main PLL */
|
||||
__HAL_RCC_PLL_DISABLE();
|
||||
|
||||
/* Get Start Tick */
|
||||
tickstart = HAL_GetTick();
|
||||
/* Wait till PLL is disabled */
|
||||
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
||||
{
|
||||
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
/* Set Range */
|
||||
__HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);
|
||||
|
||||
/* Enable the main PLL */
|
||||
__HAL_RCC_PLL_ENABLE();
|
||||
|
||||
/* Get Start Tick */
|
||||
tickstart = HAL_GetTick();
|
||||
/* Wait till PLL is ready */
|
||||
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
||||
{
|
||||
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
/* Get Start Tick */
|
||||
tickstart = HAL_GetTick();
|
||||
while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))
|
||||
{
|
||||
if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,770 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx_hal_uart_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief Extended UART HAL module driver.
|
||||
* This file provides firmware functions to manage the following extended
|
||||
* functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
|
||||
* + Initialization and de-initialization functions
|
||||
* + Peripheral Control functions
|
||||
*
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### UART peripheral extended features #####
|
||||
==============================================================================
|
||||
|
||||
(#) Declare a UART_HandleTypeDef handle structure.
|
||||
|
||||
(#) For the UART RS485 Driver Enable mode, initialize the UART registers
|
||||
by calling the HAL_RS485Ex_Init() API.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f7xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32F7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup UARTEx UARTEx
|
||||
* @brief UART Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_UART_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/** @defgroup UARTEx_Private_Functions UARTEx Private Functions
|
||||
* @{
|
||||
*/
|
||||
#if defined(USART_CR1_UESM)
|
||||
static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
|
||||
#endif /* USART_CR1_UESM */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Extended Initialization and Configuration Functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and Configuration functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
|
||||
in asynchronous mode.
|
||||
(+) For the asynchronous mode the parameters below can be configured:
|
||||
(++) Baud Rate
|
||||
(++) Word Length
|
||||
(++) Stop Bit
|
||||
(++) Parity: If the parity is enabled, then the MSB bit of the data written
|
||||
in the data register is transmitted but is changed by the parity bit.
|
||||
(++) Hardware flow control
|
||||
(++) Receiver/transmitter modes
|
||||
(++) Over Sampling Method
|
||||
(++) One-Bit Sampling Method
|
||||
(+) For the asynchronous mode, the following advanced features can be configured as well:
|
||||
(++) TX and/or RX pin level inversion
|
||||
(++) data logical level inversion
|
||||
(++) RX and TX pins swap
|
||||
(++) RX overrun detection disabling
|
||||
(++) DMA disabling on RX error
|
||||
(++) MSB first on communication line
|
||||
(++) auto Baud rate detection
|
||||
[..]
|
||||
The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration
|
||||
procedures (details for the procedures are available in reference manual).
|
||||
|
||||
@endverbatim
|
||||
|
||||
Depending on the frame length defined by the M1 and M0 bits (7-bit,
|
||||
8-bit or 9-bit), the possible UART formats are listed in the
|
||||
following table.
|
||||
|
||||
Table 1. UART frame format.
|
||||
+-----------------------------------------------------------------------+
|
||||
| M1 bit | M0 bit | PCE bit | UART frame |
|
||||
|---------|---------|-----------|---------------------------------------|
|
||||
| 0 | 0 | 0 | | SB | 8 bit data | STB | |
|
||||
|---------|---------|-----------|---------------------------------------|
|
||||
| 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
|
||||
|---------|---------|-----------|---------------------------------------|
|
||||
| 0 | 1 | 0 | | SB | 9 bit data | STB | |
|
||||
|---------|---------|-----------|---------------------------------------|
|
||||
| 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
|
||||
|---------|---------|-----------|---------------------------------------|
|
||||
| 1 | 0 | 0 | | SB | 7 bit data | STB | |
|
||||
|---------|---------|-----------|---------------------------------------|
|
||||
| 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
|
||||
+-----------------------------------------------------------------------+
|
||||
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initialize the RS485 Driver enable feature according to the specified
|
||||
* parameters in the UART_InitTypeDef and creates the associated handle.
|
||||
* @param huart UART handle.
|
||||
* @param Polarity Select the driver enable polarity.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref UART_DE_POLARITY_HIGH DE signal is active high
|
||||
* @arg @ref UART_DE_POLARITY_LOW DE signal is active low
|
||||
* @param AssertionTime Driver Enable assertion time:
|
||||
* 5-bit value defining the time between the activation of the DE (Driver Enable)
|
||||
* signal and the beginning of the start bit. It is expressed in sample time
|
||||
* units (1/8 or 1/16 bit time, depending on the oversampling rate)
|
||||
* @param DeassertionTime Driver Enable deassertion time:
|
||||
* 5-bit value defining the time between the end of the last stop bit, in a
|
||||
* transmitted message, and the de-activation of the DE (Driver Enable) signal.
|
||||
* It is expressed in sample time units (1/8 or 1/16 bit time, depending on the
|
||||
* oversampling rate).
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
|
||||
uint32_t DeassertionTime)
|
||||
{
|
||||
uint32_t temp;
|
||||
|
||||
/* Check the UART handle allocation */
|
||||
if (huart == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
/* Check the Driver Enable UART instance */
|
||||
assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));
|
||||
|
||||
/* Check the Driver Enable polarity */
|
||||
assert_param(IS_UART_DE_POLARITY(Polarity));
|
||||
|
||||
/* Check the Driver Enable assertion time */
|
||||
assert_param(IS_UART_ASSERTIONTIME(AssertionTime));
|
||||
|
||||
/* Check the Driver Enable deassertion time */
|
||||
assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));
|
||||
|
||||
if (huart->gState == HAL_UART_STATE_RESET)
|
||||
{
|
||||
/* Allocate lock resource and initialize it */
|
||||
huart->Lock = HAL_UNLOCKED;
|
||||
|
||||
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
||||
UART_InitCallbacksToDefault(huart);
|
||||
|
||||
if (huart->MspInitCallback == NULL)
|
||||
{
|
||||
huart->MspInitCallback = HAL_UART_MspInit;
|
||||
}
|
||||
|
||||
/* Init the low level hardware */
|
||||
huart->MspInitCallback(huart);
|
||||
#else
|
||||
/* Init the low level hardware : GPIO, CLOCK, CORTEX */
|
||||
HAL_UART_MspInit(huart);
|
||||
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
||||
}
|
||||
|
||||
huart->gState = HAL_UART_STATE_BUSY;
|
||||
|
||||
/* Disable the Peripheral */
|
||||
__HAL_UART_DISABLE(huart);
|
||||
|
||||
/* Set the UART Communication parameters */
|
||||
if (UART_SetConfig(huart) == HAL_ERROR)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
|
||||
{
|
||||
UART_AdvFeatureConfig(huart);
|
||||
}
|
||||
|
||||
/* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
|
||||
SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
|
||||
|
||||
/* Set the Driver Enable polarity */
|
||||
MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
|
||||
|
||||
/* Set the Driver Enable assertion and deassertion times */
|
||||
temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
|
||||
temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
|
||||
MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp);
|
||||
|
||||
/* Enable the Peripheral */
|
||||
__HAL_UART_ENABLE(huart);
|
||||
|
||||
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
|
||||
return (UART_CheckIdleState(huart));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @brief Extended Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..] This section provides the following functions:
|
||||
(+) HAL_UARTEx_EnableClockStopMode() API enables the UART clock (HSI or LSE only) during stop mode
|
||||
(+) HAL_UARTEx_DisableClockStopMode() API disables the above functionality
|
||||
(+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
|
||||
detection length to more than 4 bits for multiprocessor address mark wake up.
|
||||
#if defined(USART_CR1_UESM)
|
||||
(+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode
|
||||
trigger: address match, Start Bit detection or RXNE bit status.
|
||||
(+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode
|
||||
(+) HAL_UARTEx_DisableStopMode() API disables the above functionality
|
||||
#endif
|
||||
|
||||
[..] This subsection also provides a set of additional functions providing enhanced reception
|
||||
services to user. (For example, these functions allow application to handle use cases
|
||||
where number of data to be received is unknown).
|
||||
|
||||
(#) Compared to standard reception services which only consider number of received
|
||||
data elements as reception completion criteria, these functions also consider additional events
|
||||
as triggers for updating reception status to caller :
|
||||
(+) Detection of inactivity period (RX line has not been active for a given period).
|
||||
(++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state)
|
||||
for 1 frame time, after last received byte.
|
||||
(++) RX inactivity detected by RTO, i.e. line has been in idle state
|
||||
for a programmable time, after last received byte.
|
||||
(+) Detection that a specific character has been received.
|
||||
|
||||
(#) There are two mode of transfer:
|
||||
(+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received,
|
||||
or till IDLE event occurs. Reception is handled only during function execution.
|
||||
When function exits, no data reception could occur. HAL status and number of actually received data elements,
|
||||
are returned by function after finishing transfer.
|
||||
(+) Non-Blocking mode: The reception is performed using Interrupts or DMA.
|
||||
These API's return the HAL status.
|
||||
The end of the data processing will be indicated through the
|
||||
dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode.
|
||||
The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process
|
||||
The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected.
|
||||
|
||||
(#) Blocking mode API:
|
||||
(+) HAL_UARTEx_ReceiveToIdle()
|
||||
|
||||
(#) Non-Blocking mode API with Interrupt:
|
||||
(+) HAL_UARTEx_ReceiveToIdle_IT()
|
||||
|
||||
(#) Non-Blocking mode API with DMA:
|
||||
(+) HAL_UARTEx_ReceiveToIdle_DMA()
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(USART_CR3_UCESM)
|
||||
/**
|
||||
* @brief Keep UART Clock enabled when in Stop Mode.
|
||||
* @note When the USART clock source is configured to be LSE or HSI, it is possible to keep enabled
|
||||
* this clock during STOP mode by setting the UCESM bit in USART_CR3 control register.
|
||||
* @note When LPUART is used to wakeup from stop with LSE is selected as LPUART clock source,
|
||||
* and desired baud rate is 9600 baud, the bit UCESM bit in LPUART_CR3 control register must be set.
|
||||
* @param huart UART handle.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_UARTEx_EnableClockStopMode(UART_HandleTypeDef *huart)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(huart);
|
||||
|
||||
/* Set UCESM bit */
|
||||
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_UCESM);
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(huart);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable UART Clock when in Stop Mode.
|
||||
* @param huart UART handle.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_UARTEx_DisableClockStopMode(UART_HandleTypeDef *huart)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(huart);
|
||||
|
||||
/* Clear UCESM bit */
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_UCESM);
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(huart);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
#endif /* USART_CR3_UCESM */
|
||||
/**
|
||||
* @brief By default in multiprocessor mode, when the wake up method is set
|
||||
* to address mark, the UART handles only 4-bit long addresses detection;
|
||||
* this API allows to enable longer addresses detection (6-, 7- or 8-bit
|
||||
* long).
|
||||
* @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode,
|
||||
* 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
|
||||
* @param huart UART handle.
|
||||
* @param AddressLength This parameter can be one of the following values:
|
||||
* @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address
|
||||
* @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)
|
||||
{
|
||||
/* Check the UART handle allocation */
|
||||
if (huart == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the address length parameter */
|
||||
assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));
|
||||
|
||||
huart->gState = HAL_UART_STATE_BUSY;
|
||||
|
||||
/* Disable the Peripheral */
|
||||
__HAL_UART_DISABLE(huart);
|
||||
|
||||
/* Set the address length */
|
||||
MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);
|
||||
|
||||
/* Enable the Peripheral */
|
||||
__HAL_UART_ENABLE(huart);
|
||||
|
||||
/* TEACK and/or REACK to check before moving huart->gState to Ready */
|
||||
return (UART_CheckIdleState(huart));
|
||||
}
|
||||
|
||||
#if defined(USART_CR1_UESM)
|
||||
/**
|
||||
* @brief Set Wakeup from Stop mode interrupt flag selection.
|
||||
* @note It is the application responsibility to enable the interrupt used as
|
||||
* usart_wkup interrupt source before entering low-power mode.
|
||||
* @param huart UART handle.
|
||||
* @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref UART_WAKEUP_ON_ADDRESS
|
||||
* @arg @ref UART_WAKEUP_ON_STARTBIT
|
||||
* @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint32_t tickstart;
|
||||
|
||||
/* check the wake-up from stop mode UART instance */
|
||||
assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
|
||||
/* check the wake-up selection parameter */
|
||||
assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent));
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(huart);
|
||||
|
||||
huart->gState = HAL_UART_STATE_BUSY;
|
||||
|
||||
/* Disable the Peripheral */
|
||||
__HAL_UART_DISABLE(huart);
|
||||
|
||||
#if defined(USART_CR3_WUS)
|
||||
/* Set the wake-up selection scheme */
|
||||
MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent);
|
||||
#endif /* USART_CR3_WUS */
|
||||
|
||||
if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS)
|
||||
{
|
||||
UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection);
|
||||
}
|
||||
|
||||
/* Enable the Peripheral */
|
||||
__HAL_UART_ENABLE(huart);
|
||||
|
||||
/* Init tickstart for timeout management */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait until REACK flag is set */
|
||||
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
|
||||
{
|
||||
status = HAL_TIMEOUT;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Initialize the UART State */
|
||||
huart->gState = HAL_UART_STATE_READY;
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(huart);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable UART Stop Mode.
|
||||
* @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE.
|
||||
* @param huart UART handle.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(huart);
|
||||
|
||||
/* Set UESM bit */
|
||||
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(huart);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable UART Stop Mode.
|
||||
* @param huart UART handle.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(huart);
|
||||
|
||||
/* Clear UESM bit */
|
||||
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(huart);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
#endif /* USART_CR1_UESM */
|
||||
/**
|
||||
* @brief Receive an amount of data in blocking mode till either the expected number of data
|
||||
* is received or an IDLE event occurs.
|
||||
* @note HAL_OK is returned if reception is completed (expected number of data has been received)
|
||||
* or if reception is stopped after IDLE event (less than the expected number of data has been received)
|
||||
* In this case, RxLen output parameter indicates number of data available in reception buffer.
|
||||
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* the received data is handled as a set of uint16_t. In this case, Size must indicate the number
|
||||
* of uint16_t available through pData.
|
||||
* @param huart UART handle.
|
||||
* @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
|
||||
* @param Size Amount of data elements (uint8_t or uint16_t) to be received.
|
||||
* @param RxLen Number of data elements finally received
|
||||
* (could be lower than Size, in case reception ends on IDLE event)
|
||||
* @param Timeout Timeout duration expressed in ms (covers the whole reception sequence).
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
|
||||
uint32_t Timeout)
|
||||
{
|
||||
uint8_t *pdata8bits;
|
||||
uint16_t *pdata16bits;
|
||||
uint16_t uhMask;
|
||||
uint32_t tickstart;
|
||||
|
||||
/* Check that a Rx process is not already ongoing */
|
||||
if (huart->RxState == HAL_UART_STATE_READY)
|
||||
{
|
||||
if ((pData == NULL) || (Size == 0U))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
__HAL_LOCK(huart);
|
||||
|
||||
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
||||
huart->RxState = HAL_UART_STATE_BUSY_RX;
|
||||
huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
|
||||
|
||||
/* Init tickstart for timeout management */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
huart->RxXferSize = Size;
|
||||
huart->RxXferCount = Size;
|
||||
|
||||
/* Computation of UART mask to apply to RDR register */
|
||||
UART_MASK_COMPUTATION(huart);
|
||||
uhMask = huart->Mask;
|
||||
|
||||
/* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
|
||||
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
||||
{
|
||||
pdata8bits = NULL;
|
||||
pdata16bits = (uint16_t *) pData;
|
||||
}
|
||||
else
|
||||
{
|
||||
pdata8bits = pData;
|
||||
pdata16bits = NULL;
|
||||
}
|
||||
|
||||
__HAL_UNLOCK(huart);
|
||||
|
||||
/* Initialize output number of received elements */
|
||||
*RxLen = 0U;
|
||||
|
||||
/* as long as data have to be received */
|
||||
while (huart->RxXferCount > 0U)
|
||||
{
|
||||
/* Check if IDLE flag is set */
|
||||
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE))
|
||||
{
|
||||
/* Clear IDLE flag in ISR */
|
||||
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
||||
|
||||
/* If Set, but no data ever received, clear flag without exiting loop */
|
||||
/* If Set, and data has already been received, this means Idle Event is valid : End reception */
|
||||
if (*RxLen > 0U)
|
||||
{
|
||||
huart->RxState = HAL_UART_STATE_READY;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
}
|
||||
|
||||
/* Check if RXNE flag is set */
|
||||
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE))
|
||||
{
|
||||
if (pdata8bits == NULL)
|
||||
{
|
||||
*pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);
|
||||
pdata16bits++;
|
||||
}
|
||||
else
|
||||
{
|
||||
*pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
|
||||
pdata8bits++;
|
||||
}
|
||||
/* Increment number of received elements */
|
||||
*RxLen += 1U;
|
||||
huart->RxXferCount--;
|
||||
}
|
||||
|
||||
/* Check for the Timeout */
|
||||
if (Timeout != HAL_MAX_DELAY)
|
||||
{
|
||||
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
|
||||
{
|
||||
huart->RxState = HAL_UART_STATE_READY;
|
||||
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Set number of received elements in output parameter : RxLen */
|
||||
*RxLen = huart->RxXferSize - huart->RxXferCount;
|
||||
/* At end of Rx process, restore huart->RxState to Ready */
|
||||
huart->RxState = HAL_UART_STATE_READY;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Receive an amount of data in interrupt mode till either the expected number of data
|
||||
* is received or an IDLE event occurs.
|
||||
* @note Reception is initiated by this function call. Further progress of reception is achieved thanks
|
||||
* to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating
|
||||
* number of received data elements.
|
||||
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* the received data is handled as a set of uint16_t. In this case, Size must indicate the number
|
||||
* of uint16_t available through pData.
|
||||
* @param huart UART handle.
|
||||
* @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
|
||||
* @param Size Amount of data elements (uint8_t or uint16_t) to be received.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
|
||||
{
|
||||
HAL_StatusTypeDef status;
|
||||
|
||||
/* Check that a Rx process is not already ongoing */
|
||||
if (huart->RxState == HAL_UART_STATE_READY)
|
||||
{
|
||||
if ((pData == NULL) || (Size == 0U))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
__HAL_LOCK(huart);
|
||||
|
||||
/* Set Reception type to reception till IDLE Event*/
|
||||
huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
|
||||
|
||||
status = UART_Start_Receive_IT(huart, pData, Size);
|
||||
|
||||
/* Check Rx process has been successfully started */
|
||||
if (status == HAL_OK)
|
||||
{
|
||||
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
||||
{
|
||||
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
||||
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* In case of errors already pending when reception is started,
|
||||
Interrupts may have already been raised and lead to reception abortion.
|
||||
(Overrun error for instance).
|
||||
In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Receive an amount of data in DMA mode till either the expected number
|
||||
* of data is received or an IDLE event occurs.
|
||||
* @note Reception is initiated by this function call. Further progress of reception is achieved thanks
|
||||
* to DMA services, transferring automatically received data elements in user reception buffer and
|
||||
* calling registered callbacks at half/end of reception. UART IDLE events are also used to consider
|
||||
* reception phase as ended. In all cases, callback execution will indicate number of received data elements.
|
||||
* @note When the UART parity is enabled (PCE = 1), the received data contain
|
||||
* the parity bit (MSB position).
|
||||
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
|
||||
* the received data is handled as a set of uint16_t. In this case, Size must indicate the number
|
||||
* of uint16_t available through pData.
|
||||
* @param huart UART handle.
|
||||
* @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
|
||||
* @param Size Amount of data elements (uint8_t or uint16_t) to be received.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
|
||||
{
|
||||
HAL_StatusTypeDef status;
|
||||
|
||||
/* Check that a Rx process is not already ongoing */
|
||||
if (huart->RxState == HAL_UART_STATE_READY)
|
||||
{
|
||||
if ((pData == NULL) || (Size == 0U))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
__HAL_LOCK(huart);
|
||||
|
||||
/* Set Reception type to reception till IDLE Event*/
|
||||
huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
|
||||
|
||||
status = UART_Start_Receive_DMA(huart, pData, Size);
|
||||
|
||||
/* Check Rx process has been successfully started */
|
||||
if (status == HAL_OK)
|
||||
{
|
||||
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
||||
{
|
||||
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
||||
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* In case of errors already pending when reception is started,
|
||||
Interrupts may have already been raised and lead to reception abortion.
|
||||
(Overrun error for instance).
|
||||
In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup UARTEx_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
#if defined(USART_CR1_UESM)
|
||||
|
||||
/**
|
||||
* @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection.
|
||||
* @param huart UART handle.
|
||||
* @param WakeUpSelection UART wake up from stop mode parameters.
|
||||
* @retval None
|
||||
*/
|
||||
static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
|
||||
{
|
||||
assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength));
|
||||
|
||||
/* Set the USART address length */
|
||||
MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength);
|
||||
|
||||
/* Set the USART address node */
|
||||
MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS));
|
||||
}
|
||||
#endif /* USART_CR1_UESM */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_UART_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
Reference in New Issue
Block a user