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improve iec-gate

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This commit is contained in:
juanbono
2025-06-28 12:10:00 -03:00
parent 8c91ccdd54
commit c5e4f8039a
1 changed files with 7 additions and 10 deletions
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17
src/elements/logic/iec_gate.typ
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@@ -94,18 +94,15 @@
let space = 100% / inputs let space = 100% / inputs
for i in range(inputs) { for i in range(inputs) {
let pct = (i + 0.5) * space let pct = (i + 0.5) * space
let a = (tl, pct, bl) let port-pos = (tl, pct, bl)
let b = (tr, pct, br)
let int-name = id + "i" + str(i)
draw.intersections(
int-name,
func,
draw.hide(draw.line(a, b))
)
let port-name = "in" + str(i) let port-name = "in" + str(i)
let port-pos = int-name + ".0"
if inverted == "all" or port-name in inverted { if inverted == "all" or port-name in inverted {
draw.circle(port-pos, radius: inverted-radius, anchor: "east", stroke: stroke) draw.circle(
port-pos,
radius: inverted-radius,
anchor: "east",
stroke: stroke
)
port-pos = (rel: (-2 * inverted-radius, 0), to: port-pos) port-pos = (rel: (-2 * inverted-radius, 0), to: port-pos)
} }
add-port( add-port(