gallery/test5.typ

@@ -1,435 +0,0 @@
-#import "@preview/cetz:0.2.2": draw
-#import "../src/lib.typ": *
-
-#set page(flipped: true, paper: "a3")
-
-#circuit({
-  element.multiplexer(
-    x: 0, y: 0, w: .5, h: 1.5, id: "PCMux",
-    entries: 2,
-    fill: util.colors.blue,
-    h-ratio: 80%
-  )
-  element.block(
-    x: (rel: 2, to: "PCMux.east"),
-    y: (from: "PCMux-port-out", to: "in"),
-    w: 1, h: 1.5, id: "PCBuf",
-    ports: (
-      north: ((id: "clk", clock: true),),
-      west: ((id: "in"),),
-      east: ((id: "out"),)
-    ),
-    fill: util.colors.green
-  )
-
-  element.block(
-    x: (rel: 2, to: "PCBuf.east"),
-    y: (from: "PCBuf-port-out", to: "A"),
-    w: 3, h: 4, id: "IMem",
-    ports: (
-      west: (
-        (id: "A", name: "A"),
-      ),
-      east: (
-        (id: "RD", name: "RD"),
-      )
-    ),
-    ports-margins: (
-      west: (0%, 50%),
-      east: (0%, 50%)
-    ),
-    fill: util.colors.green,
-    name: "Instruction\nMemory"
-  )
-  element.block(
-    x: (rel: 3, to: "IMem.east"),
-    y: (from: "IMem-port-RD", to: "A1"),
-    w: 4.5, h: 4, id: "RegFile",
-    ports: (
-      north: (
-        (id: "clk", clock: true, small: true),
-        (id: "WE3", name: "WE3"),
-        (id: "dummy1")
-      ),
-      west: (
-        (id: "dummy2"),
-        (id: "A1", name: "A1"),
-        (id: "dummy3"),
-        (id: "A2", name: "A2"),
-        (id: "A3", name: "A3"),
-        (id: "dummy4"),
-        (id: "WD3", name: "WD3"),
-      ),
-      east: (
-        (id: "RD1", name: "RD1"),
-        (id: "RD2", name: "RD2"),
-      )
-    ),
-    ports-margins: (
-      north: (-20%, -20%),
-      east: (0%, 10%)
-    ),
-    fill: util.colors.green,
-    name: "Register\nFile"
-  )
-
-  element.alu(
-    x: (rel: -.7, to: "IMem.center"),
-    y: -7,
-    w: 1.4, h: 2.8, id: "PCAdd",
-    name: text("+", size: 1.5em),
-    name-anchor: "name",
-    fill: util.colors.pink
-  )
-  element.extender(
-    x: (rel: 0, to: "RegFile.west"),
-    y: (from: "PCAdd-port-out", to: "in"),
-    w: 4, h: 1.5, id: "Ext",
-    h-ratio: 50%,
-    name: "Extend",
-    name-anchor: "south",
-    align-out: false,
-    fill: util.colors.green
-  )
-
-  element.multiplexer(
-    x: (rel: 3, to: "RegFile.east"),
-    y: (from: "RegFile-port-RD2", to: "in0"),
-    w: .5, h: 1.5, id: "SrcBMux",
-    fill: util.colors.blue,
-    h-ratio: 80%
-  )
-
-  element.alu(
-    x: (rel: 2, to: "SrcBMux.east"),
-    y: (from: "SrcBMux-port-out", to: "in2"),
-    w: 1.4, h: 2.8, id: "ALU",
-    name: rotate("ALU", -90deg),
-    name-anchor: "name",
-    fill: util.colors.pink
-  )
-  element.alu(
-    x: (rel: 2, to: "SrcBMux.east"),
-    y: (from: "Ext-port-out", to: "in2"),
-    w: 1.4, h: 2.8, id: "JumpAdd",
-    name: text("+", size: 1.5em),
-    name-anchor: "name",
-    fill: util.colors.pink
-  )
-
-  element.block(
-    x: (rel: 4, to: "ALU.east"),
-    y: (from: "ALU-port-out", to: "A"),
-    w: 3, h: 4, id: "DMem",
-    name: "Data\nMemory",
-    ports: (
-      north: (
-        (id: "clk", clock: true, small: true),
-        (id: "dummy1"),
-        (id: "WE", name: "WE")
-      ),
-      west: (
-        (id: "A", name: "A"),
-        (id: "WD", name: "WD")
-      ),
-      east: (
-        (id: "RD", name: "RD"),
-        (id: "dummy2")
-      )
-    ),
-    ports-margins: (
-      north: (-10%, -10%),
-      west: (-20%, -30%),
-      east: (-10%, -20%)
-    ),
-    fill: util.colors.green
-  )
-
-  element.multiplexer(
-    x: (rel: 3, to: "DMem.east"),
-    y: (from: "DMem-port-RD", to: "in1"),
-    w: .5, h: 1.5, id: "ResMux",
-    entries: 2,
-    fill: util.colors.blue,
-    h-ratio: 80%
-  )
-
-  element.block(
-    x: (rel: 0, to: "RegFile.west"),
-    y: 3.5, w: 2.5, h: 5, id: "Ctrl",
-    name: "Control\nUnit",
-    name-anchor: "north",
-    ports: (
-      west: (
-        (id: "op", name: "op"),
-        (id: "funct3", name: "funct3"),
-        (id: "funct7", name: [funct7#sub("[5]")]),
-        (id: "zero", name: "Zero"),
-      ),
-      east: (
-        (id: "PCSrc"),
-        (id: "ResSrc"),
-        (id: "MemWrite"),
-        (id: "ALUCtrl"),
-        (id: "ALUSrc"),
-        (id: "ImmSrc"),
-        (id: "RegWrite"),
-      )
-    ),
-    ports-margins: (
-      west: (40%, 0%)
-    ),
-    fill: util.colors.orange
-  )
-
-  // Wires
-  wire.wire(
-    "wPCNext", ("PCMux-port-out", "PCBuf-port-in"),
-    name: "PCNext"
-  )
-  wire.stub("PCBuf-port-clk", "north", name: "clk", length: 0.25)
-  wire.wire(
-    "wPC1", ("PCBuf-port-out", "IMem-port-A"),
-    name: "PC"
-  )
-  wire.wire(
-    "wPC2", ("PCBuf-port-out", "JumpAdd-port-in1"),
-    style: "zigzag",
-    zigzag-ratio: 1
-  )
-  wire.wire(
-    "wPC3", ("PCBuf-port-out", "PCAdd-port-in1"),
-    style: "zigzag",
-    zigzag-ratio: 1
-  )
-  wire.intersection("wPC2.zig", radius: 2pt)
-  wire.intersection("wPC2.zag", radius: 2pt)
-  wire.stub("PCAdd-port-in2", "west", name: "4", length: 1.5)
-  wire.wire(
-    "wPC+4", ("PCAdd-port-out", "PCMux-port-in0"),
-    style: "dodge",
-    dodge-sides: ("east", "west"),
-    dodge-y: -7.5,
-    dodge-margins: (1.2, .5),
-    name: "PC+4",
-    name-pos: "start"
-  )
-  
-  let mid = ("IMem-port-RD", 50%, "RegFile-port-A1")
-  wire.wire(
-    "wInstr", ("IMem-port-RD", mid),
-    bus: true,
-    name: "Instr",
-    name-pos: "start"
-  )
-  draw.hide({
-    draw.line(name: "bus-top",
-      mid,
-      (horizontal: (), vertical: "Ctrl-port-op")
-    )
-    draw.line(name: "bus-bot",
-      mid,
-      (horizontal: (), vertical: "Ext-port-in")
-    )
-  })
-  wire.wire(
-    "wInstrBus", ("bus-top.end", "bus-bot.end"),
-    bus: true
-  )
-  wire.wire(
-    "wOp", ("Ctrl-port-op", (horizontal: mid, vertical: ())),
-    bus: true,
-    reverse: true,
-    slice: (6, 0)
-  )
-  wire.wire(
-    "wF3", ("Ctrl-port-funct3", (horizontal: mid, vertical: ())),
-    bus: true,
-    reverse: true,
-    slice: (14, 12)
-  )
-  wire.wire(
-    "wF7", ("Ctrl-port-funct7", (horizontal: mid, vertical: ())),
-    bus: true,
-    reverse: true,
-    slice: (30,)
-  )
-  wire.wire(
-    "wA1", ("RegFile-port-A1", (horizontal: mid, vertical: ())),
-    bus: true,
-    reverse: true,
-    slice: (19, 15)
-  )
-  wire.wire(
-    "wA2", ("RegFile-port-A2", (horizontal: mid, vertical: ())),
-    bus: true,
-    reverse: true,
-    slice: (24, 20)
-  )
-  wire.wire(
-    "wA3", ("RegFile-port-A3", (horizontal: mid, vertical: ())),
-    bus: true,
-    reverse: true,
-    slice: (11, 7)
-  )
-  wire.wire(
-    "wExt", ("Ext-port-in", (horizontal: mid, vertical: ())),
-    bus: true,
-    reverse: true,
-    slice: (31, 7)
-  )
-  wire.intersection("wF3.end", radius: 2pt)
-  wire.intersection("wF7.end", radius: 2pt)
-  wire.intersection("wA1.end", radius: 2pt)
-  wire.intersection("wA2.end", radius: 2pt)
-  wire.intersection("wA3.end", radius: 2pt)
-
-  wire.stub("RegFile-port-clk", "north", name: "clk", length: 0.25)
-  wire.wire("wRD2", ("RegFile-port-RD2", "SrcBMux-port-in0"))
-  wire.wire(
-    "wWD", ("RegFile-port-RD2", "DMem-port-WD"),
-    style: "zigzag",
-    zigzag-ratio: 1.5,
-    name: "WriteData",
-    name-pos: "end"
-  )
-  wire.intersection("wWD.zig", radius: 2pt)
-
-  wire.wire(
-    "wImmALU", ("Ext-port-out", "SrcBMux-port-in1"),
-    style: "zigzag",
-    zigzag-ratio: 2.5,
-    name: "ImmExt",
-    name-pos: "start"
-  )
-  wire.wire(
-    "wImmJump", ("Ext-port-out", "JumpAdd-port-in2")
-  )
-  wire.intersection("wImmALU.zig", radius: 2pt)
-  wire.wire(
-    "wJumpPC", ("JumpAdd-port-out", "PCMux-port-in1"),
-    style: "dodge",
-    dodge-sides: ("east", "west"),
-    dodge-y: -8,
-    dodge-margins: (1, 1),
-    name: "PCTarget",
-    name-pos: "start"
-  )
-
-  wire.wire(
-    "wSrcA", ("RegFile-port-RD1", "ALU-port-in1"),
-    name: "SrcA",
-    name-pos: "end"
-  )
-  wire.wire(
-    "wSrcB", ("SrcBMux-port-out", "ALU-port-in2"),
-    name: "SrcB",
-    name-pos: "end"
-  )
-
-  wire.wire(
-    "wZero", (
-      ("ALU.north-east", 50%, "ALU-port-out"),
-      "Ctrl-port-zero"
-    ),
-    style: "dodge",
-    dodge-sides: ("east", "west"),
-    dodge-y: 3,
-    dodge-margins: (1.5, 1),
-    name: "Zero",
-    name-pos: "start"
-  )
-  wire.wire(
-    "wALURes1", ("ALU-port-out", "DMem-port-A"),
-    name: "ALUResult",
-    name-pos: "start"
-  )
-  wire.wire(
-    "wALURes2", ("ALU-port-out", "ResMux-port-in0"),
-    style: "dodge",
-    dodge-sides: ("east", "west"),
-    dodge-y: 2,
-    dodge-margins: (3, 2)
-  )
-  wire.intersection("wALURes2.start2", radius: 2pt)
-
-  wire.stub("DMem-port-clk", "north", name: "clk", length: 0.25)
-  wire.wire(
-    "wRD", ("DMem-port-RD", "ResMux-port-in1"),
-    name: "ReadData",
-    name-pos: "start"
-  )
-
-  wire.wire(
-    "wRes", ("ResMux-port-out", "RegFile-port-WD3"),
-    style: "dodge",
-    dodge-sides: ("east", "west"),
-    dodge-y: -7.5,
-    dodge-margins: (1, 2)
-  )
-  draw.content(
-    "wRes.dodge-start",
-    "Result",
-    anchor: "south-east",
-    padding: 5pt
-  )
-
-  // Other wires
-  draw.group({
-    draw.stroke(util.colors.blue)
-    draw.line(name: "wPCSrc", 
-      "Ctrl-port-PCSrc",
-      (horizontal: "RegFile.east", vertical: ()),
-      (horizontal: (), vertical: (rel: (0, 0.5), to: "Ctrl.north")),
-      (horizontal: "PCMux.north", vertical: ()),
-      "PCMux.north"
-    )
-    draw.line(name: "wResSrc",
-      "Ctrl-port-ResSrc",
-      (horizontal: "ResMux.north", vertical: ()),
-      "ResMux.north"
-    )
-    draw.line(name: "wMemWrite",
-      "Ctrl-port-MemWrite",
-      (horizontal: "DMem-port-WE", vertical: ()),
-      "DMem-port-WE"
-    )
-    draw.line(name: "wALUCtrl",
-      "Ctrl-port-ALUCtrl",
-      (horizontal: "ALU.north", vertical: ()),
-      "ALU.north"
-    )
-    draw.line(name: "wALUSrc",
-      "Ctrl-port-ALUSrc",
-      (horizontal: "SrcBMux.north", vertical: ()),
-      "SrcBMux.north"
-    )
-    draw.line(name: "wImmSrc",
-      "Ctrl-port-ImmSrc",
-      (rel: (1, 0), to: (horizontal: "RegFile.east", vertical: ())),
-      (horizontal: (), vertical: (rel: (0, -.5), to: "RegFile.south")),
-      (horizontal: "Ext.north", vertical: ()),
-      "Ext.north"
-    )
-    draw.line(name: "wRegWrite",
-      "Ctrl-port-RegWrite",
-      (rel: (.5, 0), to: (horizontal: "RegFile.east", vertical: ())),
-      (horizontal: (), vertical: ("Ctrl.south", 50%, "RegFile.north")),
-      (horizontal: "RegFile-port-WE3", vertical: ()),
-      "RegFile-port-WE3"
-    )
-
-    let names = (
-      "PCSrc": "PCSrc",
-      "ResSrc": "ResultSrc",
-      "MemWrite": "MemWrite",
-      "ALUCtrl": [ALUControl#sub("[2:0]")],
-      "ALUSrc": "ALUSrc",
-      "ImmSrc": [ImmSrc#sub("[1:0]")],
-      "RegWrite": "RegWrite"
-    )
-    for (port, name) in names {
-      draw.content("Ctrl-port-"+port, name, anchor: "south-west", padding: 3pt)
-    }
-  })
-})

src/elements/alu.typ

@@ -24,11 +24,6 @@
     draw.anchor("south", (p2, 50%, p3))
     draw.anchor("west", (p0, 50%, p3))
     draw.anchor("east", (p1, 50%, p2))
-    draw.anchor("north-west", p0)
-    draw.anchor("north-east", p1)
-    draw.anchor("south-east", p2)
-    draw.anchor("south-west", p3)
-    draw.anchor("name", (p5, 50%, (p1, 50%, p2)))
   })
 
   let f2 = add-port(id, "west", (id: "in1"), (p0, 50%, p6))

src/elements/element.typ

@@ -1,6 +1,5 @@
 #import "@preview/cetz:0.2.2": draw, coordinate
 #import "ports.typ": add-ports, add-port
-#import "../util.typ"
 
 #let find-port(ports, id) = {
   for (side, side-ports) in ports {
@@ -116,7 +115,7 @@
   if (name != none) {
     draw.content(
       (name: id, anchor: name-anchor),
-      anchor: if name-anchor in util.valid-anchors {name-anchor} else {"center"},
+      anchor: name-anchor,
       padding: 0.5em,
       align(center)[*#name*]
     )

src/elements/extender.typ

@@ -1,23 +1,14 @@
 #import "@preview/cetz:0.2.2": draw
 #import "element.typ"
-#import "ports.typ": add-port
 
-#let draw-shape(id, tl, tr, br, bl, fill, stroke, h-ratio: 75%, align-out: true) = {
+#let draw-shape(id, tl, tr, br, bl, fill, stroke) = {
   let (x, y) = bl
   let (width, height) = (tr.at(0) - x, tr.at(1) - y)
 
-  let ratio = h-ratio / 100%
+  tl = (x, y + height * 0.75)
-
+  let tr2 = (x + width, y + height * 0.75)
-  tl = (x, y + height * ratio)
-  let tr2 = (x + width, y + height * ratio)
   let br = (x + width, y)
-  
-  if align-out {
   (tr, tr2) = (tr2, tr)
-  } else {
-    (tr, tr2) = (tr, tr)
-  }
-
   let f = draw.group(name: id, {
     draw.merge-path(
       inset: 0.5em,
@@ -30,10 +21,6 @@
     draw.anchor("south", (bl, 50%, br))
     draw.anchor("west", (tl, 50%, bl))
     draw.anchor("east", (tr2, 50%, br))
-    draw.anchor("north-west", tl)
-    draw.anchor("north-east", tr2)
-    draw.anchor("south-east", br)
-    draw.anchor("south-west", bl)
   })
   return (f, tl, tr, br, bl)
 }
@@ -41,9 +28,7 @@
 /// Draws a bit extender
 ///
 /// #examples.extender
-/// For other parameters description, see #doc-ref("element.elmt")
+/// For parameters description, see #doc-ref("element.elmt")
-/// - h-ratio (ratio): The height ratio of the left side relative to the full height
-/// - align-out (bool): If true, the output and input ports are aligned, otherwise, the output port is centered on the right side
 #let extender(
   x: none,
   y: none,
@@ -54,8 +39,6 @@
   fill: none,
   stroke: black + 1pt,
   id: "",
-  h-ratio: 75%,
-  align-out: true,
   debug: (
     ports: false
   )
@@ -68,14 +51,9 @@
       (id: "out"),
     )
   )
-  let out-pct = if align-out {h-ratio / 2} else {50%}
-  let ports-y = (
-    "in": (h) => {h - h * (h-ratio / 200%)},
-    "out": (h) => {h * (out-pct / 100%)}
-  )
   
   element.elmt(
-    draw-shape: draw-shape.with(h-ratio: h-ratio, align-out: align-out),
+    draw-shape: draw-shape,
     x: x,
     y: y,
     w: w,
@@ -83,16 +61,9 @@
     name: name,
     name-anchor: name-anchor,
     ports: ports,
-    auto-ports: false,
-    ports-y: ports-y,
     fill: fill,
     stroke: stroke,
     id: id,
     debug: debug
   )
-
-  let in-pos = (rel: (0, h * (h-ratio / 200%)), to: id+".south-west")
-  let out-pos = (id+".south-east", out-pct, id+".north-east")
-  add-port(id, "west", ports.west.first(), in-pos)
-  add-port(id, "east", ports.east.first(), out-pos)
 }

src/elements/multiplexer.typ

@@ -1,12 +1,10 @@
 #import "@preview/cetz:0.2.2": draw
 #import "../util.typ"
 #import "element.typ"
-#import "ports.typ": add-port
 
-#let draw-shape(id, tl, tr, br, bl, fill, stroke, h-ratio: 60%) = {
+#let draw-shape(id, tl, tr, br, bl, fill, stroke) = {
-  let margin = (100% - h-ratio) / 2
+  let tr2 = (tr, 20%, br)
-  let tr2 = (tr, margin, br)
+  let br2 = (tr, 80%, br)
-  let br2 = (br, margin, tr)
   let f = draw.group(name: id, {
     draw.merge-path(
       inset: 0.5em,
@@ -19,12 +17,7 @@
     draw.anchor("south", (bl, 50%, br2))
     draw.anchor("west", (tl, 50%, bl))
     draw.anchor("east", (tr2, 50%, br2))
-    draw.anchor("north-west", tl)
-    draw.anchor("north-east", tr2)
-    draw.anchor("south-east", br2)
-    draw.anchor("south-west", bl)
   })
-
   return (f, tl, tr, br, bl)
 }
 
@@ -33,7 +26,6 @@
 /// #examples.multiplexer
 /// For other parameters description, see #doc-ref("element.elmt")
 /// - entries (int, array): If it is an integer, it defines the number of input ports (automatically named with their binary index). If it is an array of strings, it defines the name of each input.
-/// - h-ratio (ratio): The height ratio of the right side relative to the full height
 #let multiplexer(
   x: none,
   y: none,
@@ -42,7 +34,6 @@
   name: none,
   name-anchor: "center",
   entries: 2,
-  h-ratio: 60%,
   fill: none,
   stroke: black + 1pt,
   id: "",
@@ -51,9 +42,6 @@
   )
 ) = {
   let ports = ()
-  let ports-y = (
-    out: (h) => {h * 0.5}
-  )
 
   if (type(entries) == int) {
     let nbits = calc.ceil(calc.log(entries, base: 2))
@@ -67,14 +55,8 @@
     }
   }
   
-  let space = 100% / ports.len()
-  let l = ports.len()
-  for (i, port) in ports.enumerate() {
-    ports-y.insert(port.id, (h) => {h * (i + 0.5) / l})
-  }
-  
   element.elmt(
-    draw-shape: draw-shape.with(h-ratio: h-ratio),
+    draw-shape: draw-shape,
     x: x,
     y: y,
     w: w,
@@ -85,14 +67,6 @@
     fill: fill,
     stroke: stroke,
     id: id,
-    ports-y: ports-y,
-    auto-ports: false,
     debug: debug
   )
-
-  for (i, port) in ports.enumerate() {
-    let pct = (i + 0.5) * space
-    add-port(id, "west", port, (id+".north-west", pct, id+".south-west"))
-  }
-  add-port(id, "east", (id: "out"), (id+".north-east", 50%, id+".south-east"))
 }

src/elements/ports.typ

@@ -15,12 +15,11 @@
       panic("Clock port must have previous and next positions")
     }
     
-    let size = if port.at("small", default: false) {8pt} else {1em}
     let offset
-    if      (side == "north") { offset = (    0, -size) }
+    if      (side == "north") { offset = (   0, -1em) }
-    else if (side == "east")  { offset = (-size,     0) }
+    else if (side == "east")  { offset = (-1em,    0) }
-    else if (side == "south") { offset = (    0,  size) }
+    else if (side == "south") { offset = (   0,  1em) }
-    else if (side == "west")  { offset = ( size,     0) }
+    else if (side == "west")  { offset = ( 1em,    0) }
 
     let pos1 = (rel: offset, to: pos)
 
@@ -97,11 +96,6 @@
       let pos-prev = (pt0, pct-prev, pt1)
       let pos-next = (pt0, pct-next, pt1)
 
-      if port.at("small", default: false) {
-        pos-prev = (pos, 4pt, pt0)
-        pos-next = (pos, 4pt, pt1)
-      }
-
       add-port(
         elmt-id,
         side,

src/util.typ

@@ -69,8 +69,3 @@
     south-west: "north-west"
   ).at(anchor)
 }
-
-#let valid-anchors = (
-  "center", "north", "east", "west", "south",
-  "north-east", "north-west", "south-east", "south-west"
-)

src/wire.typ

@@ -22,11 +22,7 @@
 #let get-zigzag-wire(pts, ratio, dir) = {
   let start = pts.first()
   let end = pts.last()
-  let mid = if dir == "vertical" {
+  let mid = (start, ratio, end)
-    (start, ratio, (horizontal: end, vertical: ()))
-  } else {
-    (start, ratio, (horizontal: (), vertical: end))
-  }
 
   let points = if dir == "vertical" {
     (
@@ -239,7 +235,8 @@
   }
 
   if slice != none {
-    let slice-txt = "[" + slice.map(b => str(b)).join(":") + "]"
+    let (start, end) = slice
+    let slice-txt = "[" + str(start) + ":" + str(end) + "]"
     
     draw.content(
       first-pt,