Add Verilog parsing and rendering support

- Introduced `verilog.typ` for parsing Verilog/SystemVerilog source code, supporting both ANSI and non-ANSI port styles.
- Implemented functions to analyze modules, infer AXI4, AXI4-Lite, and AXI4-Stream buses, as well as clock and reset signals.
- Added rendering capabilities for Verilog modules, allowing for visual representation of ports and buses.
- Created a new `gallery/verilog.typ` file to facilitate the drawing of Verilog blocks in diagrams.

Signed-off-by: Stavros Avramidis <stavros9899@gmail.com>

gallery/verilog.typ

@@ -6,7 +6,7 @@
   verilog.block(
     read("axi_demo.v"),
     x: 0, y: 0,
-    fill: util.colors.blue,
+    // fill: util.colors.yellow,
     // radius: 0.05em
   )
 })