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1a0a659ace
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1a0a659ace |
@@ -115,46 +115,6 @@ gates.gate-xnor(x: 0, y: 0, w: 1.5, h: 1.5)
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gates.gate-xnor(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
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gates.gate-xnor(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
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```, vertical: true)
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```, vertical: true)
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#let iec-gate-and = example(```
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gates.iec-gate-and(x: 0, y: 0, w: 1.5, h: 1.5)
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gates.iec-gate-and(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
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```, vertical: true)
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#let iec-gate-nand = example(```
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gates.iec-gate-nand(x: 0, y: 0, w: 1.5, h: 1.5)
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gates.iec-gate-nand(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
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```, vertical: true)
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#let iec-gate-or = example(```
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gates.iec-gate-or(x: 0, y: 0, w: 1.5, h: 1.5)
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gates.iec-gate-or(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
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```, vertical: true)
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#let iec-gate-nor = example(```
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gates.iec-gate-nor(x: 0, y: 0, w: 1.5, h: 1.5)
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gates.iec-gate-nor(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
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```, vertical: true)
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#let iec-gate-xor = example(```
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gates.iec-gate-xor(x: 0, y: 0, w: 1.5, h: 1.5)
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gates.iec-gate-xor(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
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```, vertical: true)
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#let iec-gate-xnor = example(```
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gates.iec-gate-xnor(x: 0, y: 0, w: 1.5, h: 1.5)
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gates.iec-gate-xnor(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
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```, vertical: true)
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#let iec-gate-buf = example(```
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gates.iec-gate-buf(x: 0, y: 0, w: 1.5, h: 1.5)
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gates.iec-gate-buf(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
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```, vertical: true)
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#let iec-gate-not = example(```
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gates.iec-gate-not(x: 0, y: 0, w: 1.5, h: 1.5)
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gates.iec-gate-not(x: 3, y: 0, w: 1.5, h: 1.5, inverted: "all")
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```, vertical: true)
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#let group = example(```
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#let group = example(```
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element.group(
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element.group(
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id: "g1", name: "Group 1", stroke: (dash: "dashed"),
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id: "g1", name: "Group 1", stroke: (dash: "dashed"),
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Binary file not shown.
Binary file not shown.
Before Width: | Height: | Size: 34 KiB |
@@ -1,98 +0,0 @@
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#import "@preview/cetz:0.3.2": draw
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#import "../src/lib.typ": circuit, element, util, wire
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#set page(width: auto, height: auto, margin: .5cm)
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#circuit({
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element.iec-gate-buf(
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x: 0,
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y: 0,
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w: 2,
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h: 2,
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id: "iec-buf",
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inputs: 1,
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)
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wire.stub("iec-buf-port-in0", "west")
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element.iec-gate-not(
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x: 3,
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y: 0,
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w: 2,
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h: 2,
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id: "iec-not",
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inputs: 1,
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)
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wire.stub("iec-not-port-in0", "west")
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element.iec-gate-and(
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id: "iec-and",
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x: 0,
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y: -3,
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w: 2,
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h: 2,
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inputs: 2,
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)
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for i in range(2) {
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wire.stub("iec-and-port-in" + str(i), "west")
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}
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element.iec-gate-nand(
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id: "iec-nand",
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x: 3,
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y: -3,
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w: 2,
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h: 2,
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inputs: 2,
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)
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for i in range(2) {
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wire.stub("iec-nand-port-in" + str(i), "west")
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}
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element.iec-gate-or(
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id: "iec-or",
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x: 0,
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y: -6,
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w: 2,
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h: 2,
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inputs: 2,
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)
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for i in range(2) {
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wire.stub("iec-or-port-in" + str(i), "west")
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}
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element.iec-gate-nor(
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id: "iec-nor",
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x: 3,
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y: -6,
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w: 2,
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h: 2,
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inputs: 2,
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)
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for i in range(2) {
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wire.stub("iec-nor-port-in" + str(i), "west")
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}
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element.iec-gate-xor(
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id: "iec-xor",
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x: 0,
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y: -9,
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w: 2,
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h: 2,
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inputs: 2,
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)
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for i in range(2) {
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wire.stub("iec-xor-port-in" + str(i), "west")
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}
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element.iec-gate-xnor(
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id: "iec-nxor",
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x: 3,
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y: -9,
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w: 2,
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h: 2,
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inputs: 2,
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)
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for i in range(2) {
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wire.stub("iec-nxor-port-in" + str(i), "west")
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}
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})
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BIN
manual.pdf
BIN
manual.pdf
Binary file not shown.
@@ -195,12 +195,7 @@ If you have installed Circuiteria directly in your project, import #link("src/li
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read("src/elements/logic/and.typ") + "\n" +
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read("src/elements/logic/and.typ") + "\n" +
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read("src/elements/logic/buf.typ") + "\n" +
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read("src/elements/logic/buf.typ") + "\n" +
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read("src/elements/logic/or.typ") + "\n" +
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read("src/elements/logic/or.typ") + "\n" +
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read("src/elements/logic/xor.typ") + "\n" +
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read("src/elements/logic/xor.typ"),
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read("src/elements/logic/iec_gate.typ") + "\n" +
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read("src/elements/logic/iec_and.typ") + "\n" +
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read("src/elements/logic/iec_buf.typ") + "\n" +
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read("src/elements/logic/iec_or.typ") + "\n" +
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read("src/elements/logic/iec_xor.typ"),
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name: "gates",
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name: "gates",
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old-syntax: true,
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old-syntax: true,
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scope: (
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scope: (
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@@ -8,7 +8,6 @@
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/// - body (none, array, element): A code block in which draw functions have been called
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/// - body (none, array, element): A code block in which draw functions have been called
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/// - length (length, ratio): Optional base unit
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/// - length (length, ratio): Optional base unit
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/// -> none
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/// -> none
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#let circuit(body, length: 2em, font: "Source Sans 3") = {
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#let circuit(body, length: 2em) = {
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set text(font: font)
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canvas(length: length, body)
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canvas(length: length, body)
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}
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}
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@@ -11,10 +11,5 @@
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#import "elements/logic/or.typ": gate-or, gate-nor
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#import "elements/logic/or.typ": gate-or, gate-nor
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#import "elements/logic/xor.typ": gate-xor, gate-xnor
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#import "elements/logic/xor.typ": gate-xor, gate-xnor
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#import "elements/logic/buf.typ": gate-buf, gate-not
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#import "elements/logic/buf.typ": gate-buf, gate-not
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#import "elements/logic/iec_gate.typ": iec-gate
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#import "elements/logic/iec_and.typ": iec-gate-and, iec-gate-nand
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#import "elements/logic/iec_buf.typ": iec-gate-buf, iec-gate-not
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#import "elements/logic/iec_or.typ": iec-gate-or, iec-gate-nor
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#import "elements/logic/iec_xor.typ": iec-gate-xor, iec-gate-xnor
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#import "elements/group.typ": group
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#import "elements/group.typ": group
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@@ -1,70 +0,0 @@
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#import "@preview/cetz:0.3.2": draw
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// #import "iec_gate.typ" as iec-gate
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#import "iec_gate.typ" as iec-gate
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/// Draws an IEC-AND gate. This function is also available as `element.iec-gate-and()`
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///
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/// For parameters, see #doc-ref("gates.iec-gate")
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/// #examples.iec-gate-and
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#let iec-gate-and(
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x: none,
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y: none,
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w: none,
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h: none,
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inputs: 2,
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fill: none,
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stroke: black + 1pt,
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id: "",
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inverted: (),
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debug: (
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ports: false
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),
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) = {
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iec-gate.iec-gate(
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x: x,
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y: y,
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w: w,
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h: h,
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inputs: inputs,
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fill: fill,
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stroke: stroke,
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id: id,
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inverted: inverted,
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debug: debug,
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symbol: $amp$,
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)
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}
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/// Draws an IEC-NAND gate. This function is also available as `element.iec-gate-nand()`
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///
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/// For parameters, see #doc-ref("gates.iec-gate")
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/// #examples.iec-gate-nand
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#let iec-gate-nand(
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x: none,
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y: none,
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w: none,
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h: none,
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inputs: 2,
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fill: none,
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stroke: black + 1pt,
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id: "",
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inverted: (),
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debug: (
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ports: false
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),
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) = {
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iec-gate-and(
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x: x,
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y: y,
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w: w,
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h: h,
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inputs: inputs,
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fill: fill,
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stroke: stroke,
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id: id,
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inverted: if inverted != "all" {inverted + ("out",)} else {inverted},
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debug: debug,
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)
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}
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@@ -1,68 +0,0 @@
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#import "@preview/cetz:0.3.2": draw
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#import "iec_gate.typ" as iec-gate
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/// Draws an IEC buffer gate. This function is also available as `element.iec-gate-buf()`
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///
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/// For parameters, see #doc-ref("gates.iec-gate")
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/// #examples.iec-gate-buf
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#let iec-gate-buf(
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x: none,
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y: none,
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w: none,
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h: none,
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inputs: 2,
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fill: none,
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stroke: black + 1pt,
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id: "",
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inverted: (),
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debug: (
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ports: false,
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),
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) = {
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iec-gate.iec-gate(
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x: x,
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y: y,
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w: w,
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h: h,
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inputs: inputs,
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fill: fill,
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stroke: stroke,
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id: id,
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inverted: inverted,
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debug: debug,
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symbol: "1",
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)
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}
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/// Draws an IEC NOT gate. This function is also available as `element.iec-gate-not()`
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///
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/// For parameters, see #doc-ref("gates.iec-gate")
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/// #examples.iec-gate-not
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#let iec-gate-not(
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x: none,
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y: none,
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w: none,
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h: none,
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inputs: 2,
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fill: none,
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stroke: black + 1pt,
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id: "",
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inverted: (),
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debug: (
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ports: false,
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),
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) = {
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iec-gate-buf(
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x: x,
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y: y,
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w: w,
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h: h,
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|
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inputs: inputs,
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fill: fill,
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stroke: stroke,
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id: id,
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inverted: if inverted != "all" { inverted + ("out",) } else { inverted },
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debug: debug,
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)
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}
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|
@@ -1,125 +0,0 @@
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#import "@preview/cetz:0.3.2": draw, coordinate
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#import "../ports.typ": add-ports, add-port
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#import "../element.typ"
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|
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#let default-draw-shape(id, tl, tr, br, bl, fill, stroke, symbol) = {
|
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let shapes = draw.rect(
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inset: 0.5em,
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fill: fill,
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|
||||||
stroke: stroke,
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|
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name: id,
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bl, tr
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)
|
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shapes += draw.content(
|
|
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id + ".center",
|
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[*$ symbol $*]
|
|
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)
|
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return (shapes, tl, tr, br, bl)
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|
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}
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|
||||||
|
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||||||
/// Draws a logic gate. This function is also available as `element.iec-gate()`
|
|
||||||
///
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/// - draw-shape (function): see #doc-ref("element.elmt")
|
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/// - x (number, dictionary): see #doc-ref("element.elmt")
|
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/// - y (number, dictionary): see #doc-ref("element.elmt")
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|
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/// - w (number): see #doc-ref("element.elmt")
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|
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/// - h (number): see #doc-ref("element.elmt")
|
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/// - inputs (int): The number of inputs
|
|
||||||
/// - fill (none, color): see #doc-ref("element.elmt")
|
|
||||||
/// - stroke (stroke): see #doc-ref("element.elmt")
|
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||||||
/// - id (str): see #doc-ref("element.elmt")
|
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||||||
/// - inverted (str, array): Either "all" or an array of port ids to display as inverted
|
|
||||||
/// - inverted-radius (number): The radius of inverted ports dot
|
|
||||||
/// - debug (dictionary): see #doc-ref("element.elmt")
|
|
||||||
/// - symbol (str): The symbol to display at the center of the gate
|
|
||||||
#let iec-gate(
|
|
||||||
draw-shape: default-draw-shape,
|
|
||||||
x: none,
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|
||||||
y: none,
|
|
||||||
w: none,
|
|
||||||
h: none,
|
|
||||||
inputs: 2,
|
|
||||||
fill: none,
|
|
||||||
stroke: black + 1pt,
|
|
||||||
id: "",
|
|
||||||
inverted: (),
|
|
||||||
inverted-radius: 0.1,
|
|
||||||
debug: (
|
|
||||||
ports: false
|
|
||||||
),
|
|
||||||
symbol: "",
|
|
||||||
) = draw.get-ctx(ctx => {
|
|
||||||
let width = w
|
|
||||||
let height = h
|
|
||||||
|
|
||||||
let x = x
|
|
||||||
let y = y
|
|
||||||
if x == none { panic("Parameter x must be set") }
|
|
||||||
if y == none { panic("Parameter y must be set") }
|
|
||||||
if w == none { panic("Parameter w must be set") }
|
|
||||||
if h == none { panic("Parameter h must be set") }
|
|
||||||
|
|
||||||
if (type(x) == dictionary) {
|
|
||||||
let offset = x.rel
|
|
||||||
let to = x.to
|
|
||||||
let (ctx, to-pos) = coordinate.resolve(ctx, (rel: (offset, 0), to: to))
|
|
||||||
x = to-pos.at(0)
|
|
||||||
}
|
|
||||||
|
|
||||||
if (type(y) == dictionary) {
|
|
||||||
let from = y.from
|
|
||||||
let to = y.to
|
|
||||||
|
|
||||||
let dy
|
|
||||||
if to == "out" {
|
|
||||||
dy = height / 2
|
|
||||||
} else {
|
|
||||||
dy = height * (i + 0.5) / inputs
|
|
||||||
}
|
|
||||||
|
|
||||||
let (ctx, from-pos) = coordinate.resolve(ctx, from)
|
|
||||||
y = from-pos.at(1) + dy - height
|
|
||||||
}
|
|
||||||
|
|
||||||
let tl = (x, y + height)
|
|
||||||
let tr = (x + width, y + height)
|
|
||||||
let br = (x + width, y)
|
|
||||||
let bl = (x, y)
|
|
||||||
|
|
||||||
// Workaround because CeTZ needs to have all draw functions in the body
|
|
||||||
let func = {}
|
|
||||||
(func, tl, tr, br, bl) = draw-shape(id, tl, tr, br, bl, fill, stroke, symbol)
|
|
||||||
func
|
|
||||||
|
|
||||||
let space = 100% / inputs
|
|
||||||
for i in range(inputs) {
|
|
||||||
let pct = (i + 0.5) * space
|
|
||||||
let port-pos = (tl, pct, bl)
|
|
||||||
let port-name = "in" + str(i)
|
|
||||||
if inverted == "all" or port-name in inverted {
|
|
||||||
draw.circle(
|
|
||||||
port-pos,
|
|
||||||
radius: inverted-radius,
|
|
||||||
anchor: "east",
|
|
||||||
stroke: stroke
|
|
||||||
)
|
|
||||||
port-pos = (rel: (-2 * inverted-radius, 0), to: port-pos)
|
|
||||||
}
|
|
||||||
add-port(
|
|
||||||
id, "west",
|
|
||||||
(id: port-name), port-pos,
|
|
||||||
debug: debug.ports
|
|
||||||
)
|
|
||||||
}
|
|
||||||
|
|
||||||
let out-pos = id + ".east"
|
|
||||||
if inverted == "all" or "out" in inverted {
|
|
||||||
draw.circle(out-pos, radius: inverted-radius, anchor: "west", stroke: stroke)
|
|
||||||
out-pos = (rel: (2 * inverted-radius, 0), to: out-pos)
|
|
||||||
}
|
|
||||||
add-port(
|
|
||||||
id, "east",
|
|
||||||
(id: "out"), out-pos,
|
|
||||||
debug: debug.ports
|
|
||||||
)
|
|
||||||
})
|
|
@@ -1,67 +0,0 @@
|
|||||||
#import "@preview/cetz:0.3.2": draw
|
|
||||||
#import "iec_gate.typ" as iec-gate
|
|
||||||
|
|
||||||
/// Draws an IEC-OR gate. This function is also available as `element.iec-gate-or()`
|
|
||||||
///
|
|
||||||
/// For parameters, see #doc-ref("gates.iec-gate")
|
|
||||||
/// #examples.iec-gate-or
|
|
||||||
#let iec-gate-or(
|
|
||||||
x: none,
|
|
||||||
y: none,
|
|
||||||
w: none,
|
|
||||||
h: none,
|
|
||||||
inputs: 2,
|
|
||||||
fill: none,
|
|
||||||
stroke: black + 1pt,
|
|
||||||
id: "",
|
|
||||||
inverted: (),
|
|
||||||
debug: (
|
|
||||||
ports: false
|
|
||||||
)
|
|
||||||
) = {
|
|
||||||
iec-gate.iec-gate(
|
|
||||||
x: x,
|
|
||||||
y: y,
|
|
||||||
w: w,
|
|
||||||
h: h,
|
|
||||||
inputs: inputs,
|
|
||||||
fill: fill,
|
|
||||||
stroke: stroke,
|
|
||||||
id: id,
|
|
||||||
inverted: inverted,
|
|
||||||
debug: debug,
|
|
||||||
symbol: $>= 1$,
|
|
||||||
)
|
|
||||||
}
|
|
||||||
|
|
||||||
/// Draws an IEC-NOR gate. This function is also available as `element.iec-gate-nor()`
|
|
||||||
///
|
|
||||||
/// For parameters, see #doc-ref("gates.iec-gate")
|
|
||||||
/// #examples.iec-gate-nor
|
|
||||||
#let iec-gate-nor(
|
|
||||||
x: none,
|
|
||||||
y: none,
|
|
||||||
w: none,
|
|
||||||
h: none,
|
|
||||||
inputs: 2,
|
|
||||||
fill: none,
|
|
||||||
stroke: black + 1pt,
|
|
||||||
id: "",
|
|
||||||
inverted: (),
|
|
||||||
debug: (
|
|
||||||
ports: false
|
|
||||||
)
|
|
||||||
) = {
|
|
||||||
iec-gate-or(
|
|
||||||
x: x,
|
|
||||||
y: y,
|
|
||||||
w: w,
|
|
||||||
h: h,
|
|
||||||
inputs: inputs,
|
|
||||||
fill: fill,
|
|
||||||
stroke: stroke,
|
|
||||||
id: id,
|
|
||||||
inverted: if inverted != "all" {inverted + ("out",)} else {inverted},
|
|
||||||
debug: debug
|
|
||||||
)
|
|
||||||
}
|
|
@@ -1,67 +0,0 @@
|
|||||||
#import "@preview/cetz:0.3.2": draw
|
|
||||||
#import "iec_gate.typ" as iec-gate
|
|
||||||
|
|
||||||
/// Draws an IEC-XOR gate. This function is also available as `element.iec-gate-xor()`
|
|
||||||
///
|
|
||||||
/// For parameters, see #doc-ref("gates.iec-gate")
|
|
||||||
/// #examples.iec-gate-xor
|
|
||||||
#let iec-gate-xor(
|
|
||||||
x: none,
|
|
||||||
y: none,
|
|
||||||
w: none,
|
|
||||||
h: none,
|
|
||||||
inputs: 2,
|
|
||||||
fill: none,
|
|
||||||
stroke: black + 1pt,
|
|
||||||
id: "",
|
|
||||||
inverted: (),
|
|
||||||
debug: (
|
|
||||||
ports: false
|
|
||||||
)
|
|
||||||
) = {
|
|
||||||
iec-gate.iec-gate(
|
|
||||||
x: x,
|
|
||||||
y: y,
|
|
||||||
w: w,
|
|
||||||
h: h,
|
|
||||||
inputs: inputs,
|
|
||||||
fill: fill,
|
|
||||||
stroke: stroke,
|
|
||||||
id: id,
|
|
||||||
inverted: inverted,
|
|
||||||
debug: debug,
|
|
||||||
symbol: $= 1$,
|
|
||||||
)
|
|
||||||
}
|
|
||||||
|
|
||||||
/// Draws an IEC-XNOR gate. This function is also available as `element.iec-gate-xnor()`
|
|
||||||
///
|
|
||||||
/// For parameters, see #doc-ref("gates.iec-gate")
|
|
||||||
/// #examples.iec-gate-xnor
|
|
||||||
#let iec-gate-xnor(
|
|
||||||
x: none,
|
|
||||||
y: none,
|
|
||||||
w: none,
|
|
||||||
h: none,
|
|
||||||
inputs: 2,
|
|
||||||
fill: none,
|
|
||||||
stroke: black + 1pt,
|
|
||||||
id: "",
|
|
||||||
inverted: (),
|
|
||||||
debug: (
|
|
||||||
ports: false
|
|
||||||
)
|
|
||||||
) = {
|
|
||||||
iec-gate-xor(
|
|
||||||
x: x,
|
|
||||||
y: y,
|
|
||||||
w: w,
|
|
||||||
h: h,
|
|
||||||
inputs: inputs,
|
|
||||||
fill: fill,
|
|
||||||
stroke: stroke,
|
|
||||||
id: id,
|
|
||||||
inverted: if inverted != "all" {inverted + ("out",)} else {inverted},
|
|
||||||
debug: debug
|
|
||||||
)
|
|
||||||
}
|
|
@@ -2,9 +2,4 @@
|
|||||||
#import "elements/logic/and.typ": gate-and, gate-nand
|
#import "elements/logic/and.typ": gate-and, gate-nand
|
||||||
#import "elements/logic/or.typ": gate-or, gate-nor
|
#import "elements/logic/or.typ": gate-or, gate-nor
|
||||||
#import "elements/logic/xor.typ": gate-xor, gate-xnor
|
#import "elements/logic/xor.typ": gate-xor, gate-xnor
|
||||||
#import "elements/logic/buf.typ": gate-buf, gate-not
|
#import "elements/logic/buf.typ": gate-buf, gate-not
|
||||||
#import "elements/logic/iec_gate.typ": iec-gate
|
|
||||||
#import "elements/logic/iec_and.typ": iec-gate-and, iec-gate-nand
|
|
||||||
#import "elements/logic/iec_or.typ": iec-gate-or, iec-gate-nor
|
|
||||||
#import "elements/logic/iec_buf.typ": iec-gate-buf, iec-gate-not
|
|
||||||
#import "elements/logic/iec_xor.typ": iec-gate-xor, iec-gate-xnor
|
|
Reference in New Issue
Block a user