doc/examples.typ

@@ -140,11 +140,4 @@ element.block(id: "b3", w: 2, h: 3,
 wire.wire("w1", ("b1-port-out", "b3-port-in1"))
 wire.wire("w2", ("b2-port-out", "b3-port-in2"),
           style: "zigzag")
-```)
-
-#let intersection = example(```
-wire.wire("w1", ((0, 0), (1, 1)), style: "zigzag")
-wire.wire("w2", ((0, 0), (1, -.5)),
-          style: "zigzag", zigzag-ratio: 80%)
-wire.intersection("w1.zig")
 ```)

gallery/test.typ

@@ -294,6 +294,6 @@
     bus: true
   )
 
-  wire.intersection("wResMP-RegFile.dodge-end", radius: .2)
+  wire.intersection("wResMP-RegFile.dodge-end")
-  wire.intersection("wResMP-AdrSrc.dodge-end", radius: .2)
+  wire.intersection("wResMP-AdrSrc.dodge-end")
 })

gallery/test2.typ

@@ -307,6 +307,6 @@
     bus: true
   )
   
-  wire.intersection("wResMP-RegFile.dodge-end", radius: .2)
+  wire.intersection("wResMP-RegFile.dodge-end")
-  wire.intersection("wResMP-AdrSrc.dodge-end", radius: .2)
+  wire.intersection("wResMP-AdrSrc.dodge-end")
 })

gallery/test5.typ

@@ -202,8 +202,8 @@
     style: "zigzag",
     zigzag-ratio: 1
   )
-  wire.intersection("wPC2.zig")
+  wire.intersection("wPC2.zig", radius: 2pt)
-  wire.intersection("wPC2.zag")
+  wire.intersection("wPC2.zag", radius: 2pt)
   wire.stub("PCAdd-port-in2", "west", name: "4", length: 1.5)
   wire.wire(
     "wPC+4", ("PCAdd-port-out", "PCMux-port-in0"),
@@ -278,11 +278,11 @@
     reverse: true,
     slice: (31, 7)
   )
-  wire.intersection("wF3.end")
+  wire.intersection("wF3.end", radius: 2pt)
-  wire.intersection("wF7.end")
+  wire.intersection("wF7.end", radius: 2pt)
-  wire.intersection("wA1.end")
+  wire.intersection("wA1.end", radius: 2pt)
-  wire.intersection("wA2.end")
+  wire.intersection("wA2.end", radius: 2pt)
-  wire.intersection("wA3.end")
+  wire.intersection("wA3.end", radius: 2pt)
 
   wire.stub("RegFile-port-clk", "north", name: "clk", length: 0.25)
   wire.wire("wRD2", ("RegFile-port-RD2", "SrcBMux-port-in0"))
@@ -293,7 +293,7 @@
     name: "WriteData",
     name-pos: "end"
   )
-  wire.intersection("wWD.zig")
+  wire.intersection("wWD.zig", radius: 2pt)
 
   wire.wire(
     "wImmALU", ("Ext-port-out", "SrcBMux-port-in1"),
@@ -305,7 +305,7 @@
   wire.wire(
     "wImmJump", ("Ext-port-out", "JumpAdd-port-in2")
   )
-  wire.intersection("wImmALU.zig")
+  wire.intersection("wImmALU.zig", radius: 2pt)
   wire.wire(
     "wJumpPC", ("JumpAdd-port-out", "PCMux-port-in1"),
     style: "dodge",
@@ -351,7 +351,7 @@
     dodge-y: 2,
     dodge-margins: (3, 2)
   )
-  wire.intersection("wALURes2.start2")
+  wire.intersection("wALURes2.start2", radius: 2pt)
 
   wire.stub("DMem-port-clk", "north", name: "clk", length: 0.25)
   wire.wire(

src/elements/alu.typ

@@ -86,7 +86,6 @@
     ports-y: (
       in1: (h) => {h * 0.225},
       in2: (h) => {h * 0.775},
-      out: (h) => {h * 0.5}
     ),
     debug: debug
   )

src/elements/extender.typ

@@ -71,7 +71,7 @@
   let out-pct = if align-out {h-ratio / 2} else {50%}
   let ports-y = (
     "in": (h) => {h - h * (h-ratio / 200%)},
-    "out": (h) => {h - h * (out-pct / 100%)}
+    "out": (h) => {h * (out-pct / 100%)}
   )
   
   element.elmt(

src/elements/logic/buf.typ

@@ -33,7 +33,7 @@
   y: none,
   w: none,
   h: none,
-  inputs: 1,
+  inputs: 2,
   fill: none,
   stroke: black + 1pt,
   id: "",
@@ -65,7 +65,7 @@
   y: none,
   w: none,
   h: none,
-  inputs: 1,
+  inputs: 2,
   fill: none,
   stroke: black + 1pt,
   id: "",

src/elements/logic/gate.typ

@@ -33,7 +33,7 @@
   stroke: black + 1pt,
   id: "",
   inverted: (),
-  inverted-radius: 0.1,
+  inverted-radius: 0.2,
   debug: (
     ports: false
   )
@@ -58,16 +58,19 @@
   if (type(y) == dictionary) {
     let from = y.from
     let to = y.to
-    
+    let (to-side, i) = find-port(ports, to)
-    let dy
+    let margins = (0%, 0%)
-    if to == "out" {
+    if to-side in ports-margins {
-      dy = height / 2
+      margins = ports-margins.at(to-side)
-    } else {
-      dy = height * (i + 0.5) / inputs
     }
+    let used-pct = 100% - margins.at(0) - margins.at(1)
+    let used-height = height * used-pct / 100%
+    let top-margin = height * margins.at(0) / 100%
+    
+    let dy = used-height * (i + 1) / (ports.at(to-side).len() + 1)
     
     let (ctx, from-pos) = coordinate.resolve(ctx, from)
-    y = from-pos.at(1) + dy - height
+    y = from-pos.at(1) + dy - height + top-margin
   }
 
   let tl = (x, y + height)

src/wire.typ

@@ -7,12 +7,7 @@
 #let signal-width = 1pt
 #let bus-width = 1.5pt
 
-/// Draws a wire intersection at the given anchor
+#let intersection(pt, radius: .2, fill: black) = {
-/// #examples.intersection
-/// - pt (point): A CeTZ compatible point / anchor
-/// - radius (number): The radius of the intersection
-/// - fill (color): The fill color
-#let intersection(pt, radius: .1, fill: black) = {
   draw.circle(pt, radius: radius, stroke: none, fill: fill)
 }