1
0
mirror of https://github.com/Klagarge/Cursor.git synced 2025-06-25 20:02:31 +00:00

work with 2 small bugs

sometimes won't go back to pos2, and problem if many push in same button
This commit is contained in:
2022-01-20 22:02:29 +01:00
parent e8427259ac
commit 042f09e0f1
97 changed files with 73520 additions and 9649 deletions

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@ -0,0 +1,29 @@
--
-- VHDL Architecture Cursor_test.pulseWidthModulator_tester.arch_name
--
-- Created:
-- by - Simon.UNKNOWN (PC-SDM)
-- at - 08:54:14 14.01.2022
--
-- using Mentor Graphics HDL Designer(TM) 2019.2 (Build 5)
--
ARCHITECTURE arch_name OF pulseWidthModulator_tester IS
constant clockFrequency: real := 66.0E6;
constant clockPeriod: time := 1.0/clockFrequency * 1 sec;
signal clock_int: std_ulogic := '0';
BEGIN
-----------------------------------------------------------------------------
-- clock and reset
reset <= '1', '0' after 4*clockPeriod;
clock_int <= not clock_int after clockPeriod/2;
clock <= transport clock_int after 9*clockPeriod/10;
------------------------------------------------------------------------------
END ARCHITECTURE arch_name;

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@ -1 +1 @@
DIALECT atom VHDL_ANY
DIALECT atom VHDL_2008

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@ -1,4 +1,4 @@
DIALECT atom VHDL_2008
INCLUDE list {
DEFAULT atom 1
}
DIALECT atom VHDL_2008

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@ -0,0 +1,4 @@
DIALECT atom VHDL_2008
INCLUDE list {
DEFAULT atom 1
}

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@ -0,0 +1 @@
DIALECT atom VHDL_2008

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@ -0,0 +1 @@
DIALECT atom VHDL_ANY

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@ -0,0 +1,2 @@
DEFAULT_ARCHITECTURE atom struct
DEFAULT_FILE atom pulse@width@modulator_tb/struct.bd

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@ -0,0 +1,2 @@
DEFAULT_ARCHITECTURE atom fsm
DEFAULT_FILE atom pwmtest/fsm.sm

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@ -59,7 +59,7 @@ value "1"
)
]
mwi 0
uid 5729,0
uid 6511,0
)
]
libraryRefs [
@ -78,23 +78,23 @@ value " "
)
(vvPair
variable "HDLDir"
value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor_test\\hdl"
value "U:\\Cursor\\Prefs\\..\\Cursor_test\\hdl"
)
(vvPair
variable "HDSDir"
value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor_test\\hds"
value "U:\\Cursor\\Prefs\\..\\Cursor_test\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tb\\struct.bd.info"
value "U:\\Cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tb\\struct.bd.info"
)
(vvPair
variable "SideDataUserDir"
value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tb\\struct.bd.user"
value "U:\\Cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tb\\struct.bd.user"
)
(vvPair
variable "SourceDir"
value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor_test\\hds"
value "U:\\Cursor\\Prefs\\..\\Cursor_test\\hds"
)
(vvPair
variable "appl"
@ -114,27 +114,27 @@ value "%(unit)_%(view)_config"
)
(vvPair
variable "d"
value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tb"
value "U:\\Cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tb"
)
(vvPair
variable "d_logical"
value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tb"
value "U:\\Cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tb"
)
(vvPair
variable "date"
value "21.12.2021"
value "20.01.2022"
)
(vvPair
variable "day"
value "mar."
value "jeu."
)
(vvPair
variable "day_long"
value "mardi"
value "jeudi"
)
(vvPair
variable "dd"
value "21"
value "20"
)
(vvPair
variable "designName"
@ -162,11 +162,11 @@ value "struct"
)
(vvPair
variable "graphical_source_author"
value "remi"
value "remi.heredero"
)
(vvPair
variable "graphical_source_date"
value "21.12.2021"
value "20.01.2022"
)
(vvPair
variable "graphical_source_group"
@ -174,11 +174,11 @@ value "UNKNOWN"
)
(vvPair
variable "graphical_source_host"
value "MARVIN"
value "WE2332001"
)
(vvPair
variable "graphical_source_time"
value "16:00:15"
value "16:53:37"
)
(vvPair
variable "group"
@ -186,7 +186,7 @@ value "UNKNOWN"
)
(vvPair
variable "host"
value "MARVIN"
value "WE2332001"
)
(vvPair
variable "language"
@ -206,7 +206,7 @@ value "$SCRATCH_DIR/Cursor_test/work"
)
(vvPair
variable "mm"
value "12"
value "01"
)
(vvPair
variable "module_name"
@ -214,19 +214,19 @@ value "cursor_tb"
)
(vvPair
variable "month"
value "d<EFBFBD>c."
value "janv."
)
(vvPair
variable "month_long"
value "d<EFBFBD>cembre"
value "janvier"
)
(vvPair
variable "p"
value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tb\\struct.bd"
value "U:\\Cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tb\\struct.bd"
)
(vvPair
variable "p_logical"
value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tb\\struct.bd"
value "U:\\Cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tb\\struct.bd"
)
(vvPair
variable "package_name"
@ -302,7 +302,7 @@ value "struct"
)
(vvPair
variable "time"
value "16:00:15"
value "16:53:37"
)
(vvPair
variable "unit"
@ -310,7 +310,7 @@ value "cursor_tb"
)
(vvPair
variable "user"
value "remi"
value "remi.heredero"
)
(vvPair
variable "version"
@ -322,11 +322,11 @@ value "struct"
)
(vvPair
variable "year"
value "2021"
value "2022"
)
(vvPair
variable "yy"
value "21"
value "22"
)
]
)
@ -449,7 +449,7 @@ va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "56200,91400,70700,92600"
xt "56200,91400,75700,92600"
st "
by %user on %dd %month %year
"
@ -706,9 +706,9 @@ uid 1777,0
va (VaSet
font "Verdana,12,1"
)
xt "13600,82900,22000,84200"
xt "14600,76900,23000,78200"
st "Cursor_test"
blo "13600,83900"
blo "14600,77900"
tm "BdLibraryNameMgr"
)
*16 (Text
@ -716,9 +716,9 @@ uid 1778,0
va (VaSet
font "Verdana,12,1"
)
xt "13600,84300,23400,85600"
xt "14600,78300,24400,79600"
st "cursor_tester"
blo "13600,85300"
blo "14600,79300"
tm "BlkNameMgr"
)
*17 (Text
@ -726,9 +726,9 @@ uid 1779,0
va (VaSet
font "Verdana,12,1"
)
xt "13600,85700,19200,87000"
xt "14600,79700,20200,81000"
st "I_tester"
blo "13600,86700"
blo "14600,80700"
tm "InstanceNameMgr"
)
]
@ -985,13 +985,13 @@ st "SIGNAL button4 : std_uLogic"
)
)
*31 (SaComponent
uid 5729,0
uid 6511,0
optionalChildren [
*32 (CptPort
uid 5624,0
uid 6427,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5625,0
uid 6428,0
ro 90
va (VaSet
vasetType 1
@ -1000,11 +1000,11 @@ fg "0,65535,0"
xt "38250,62625,39000,63375"
)
tg (CPTG
uid 5626,0
uid 6429,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5627,0
uid 6430,0
va (VaSet
font "Verdana,12,0"
)
@ -1023,10 +1023,10 @@ suid 1,0
)
)
*33 (CptPort
uid 5629,0
uid 6431,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5630,0
uid 6432,0
ro 90
va (VaSet
vasetType 1
@ -1035,11 +1035,11 @@ fg "0,65535,0"
xt "38250,64625,39000,65375"
)
tg (CPTG
uid 5631,0
uid 6433,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5632,0
uid 6434,0
va (VaSet
font "Verdana,12,0"
)
@ -1058,10 +1058,10 @@ suid 2,0
)
)
*34 (CptPort
uid 5634,0
uid 6435,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5635,0
uid 6436,0
ro 90
va (VaSet
vasetType 1
@ -1070,11 +1070,11 @@ fg "0,65535,0"
xt "55000,40625,55750,41375"
)
tg (CPTG
uid 5636,0
uid 6437,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5637,0
uid 6438,0
va (VaSet
font "Verdana,12,0"
)
@ -1095,10 +1095,10 @@ suid 3,0
)
)
*35 (CptPort
uid 5639,0
uid 6439,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5640,0
uid 6440,0
ro 90
va (VaSet
vasetType 1
@ -1107,11 +1107,11 @@ fg "0,65535,0"
xt "38250,38625,39000,39375"
)
tg (CPTG
uid 5641,0
uid 6441,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5642,0
uid 6442,0
va (VaSet
font "Verdana,12,0"
)
@ -1130,10 +1130,10 @@ suid 4,0
)
)
*36 (CptPort
uid 5644,0
uid 6443,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5645,0
uid 6444,0
ro 90
va (VaSet
vasetType 1
@ -1142,11 +1142,11 @@ fg "0,65535,0"
xt "38250,42625,39000,43375"
)
tg (CPTG
uid 5646,0
uid 6445,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5647,0
uid 6446,0
va (VaSet
font "Verdana,12,0"
)
@ -1165,10 +1165,10 @@ suid 5,0
)
)
*37 (CptPort
uid 5649,0
uid 6447,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5650,0
uid 6448,0
ro 270
va (VaSet
vasetType 1
@ -1177,11 +1177,11 @@ fg "0,65535,0"
xt "55000,46625,55750,47375"
)
tg (CPTG
uid 5651,0
uid 6449,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5652,0
uid 6450,0
va (VaSet
font "Verdana,12,0"
)
@ -1201,10 +1201,10 @@ suid 6,0
)
)
*38 (CptPort
uid 5654,0
uid 6451,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5655,0
uid 6452,0
ro 90
va (VaSet
vasetType 1
@ -1213,11 +1213,11 @@ fg "0,65535,0"
xt "38250,60625,39000,61375"
)
tg (CPTG
uid 5656,0
uid 6453,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5657,0
uid 6454,0
va (VaSet
font "Verdana,12,0"
)
@ -1236,10 +1236,10 @@ suid 7,0
)
)
*39 (CptPort
uid 5659,0
uid 6455,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5660,0
uid 6456,0
ro 90
va (VaSet
vasetType 1
@ -1248,11 +1248,11 @@ fg "0,65535,0"
xt "38250,40625,39000,41375"
)
tg (CPTG
uid 5661,0
uid 6457,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5662,0
uid 6458,0
va (VaSet
font "Verdana,12,0"
)
@ -1271,10 +1271,10 @@ suid 9,0
)
)
*40 (CptPort
uid 5664,0
uid 6459,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5665,0
uid 6460,0
ro 90
va (VaSet
vasetType 1
@ -1283,11 +1283,11 @@ fg "0,65535,0"
xt "55000,42625,55750,43375"
)
tg (CPTG
uid 5666,0
uid 6461,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5667,0
uid 6462,0
va (VaSet
font "Verdana,12,0"
)
@ -1308,10 +1308,10 @@ suid 10,0
)
)
*41 (CptPort
uid 5669,0
uid 6463,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5670,0
uid 6464,0
ro 270
va (VaSet
vasetType 1
@ -1320,11 +1320,11 @@ fg "0,65535,0"
xt "55000,48625,55750,49375"
)
tg (CPTG
uid 5671,0
uid 6465,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5672,0
uid 6466,0
va (VaSet
font "Verdana,12,0"
)
@ -1344,10 +1344,10 @@ suid 11,0
)
)
*42 (CptPort
uid 5674,0
uid 6467,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5675,0
uid 6468,0
ro 90
va (VaSet
vasetType 1
@ -1356,11 +1356,11 @@ fg "0,65535,0"
xt "55000,38625,55750,39375"
)
tg (CPTG
uid 5676,0
uid 6469,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5677,0
uid 6470,0
va (VaSet
font "Verdana,12,0"
)
@ -1381,10 +1381,10 @@ suid 12,0
)
)
*43 (CptPort
uid 5679,0
uid 6471,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5680,0
uid 6472,0
ro 270
va (VaSet
vasetType 1
@ -1393,11 +1393,11 @@ fg "0,65535,0"
xt "55000,52625,55750,53375"
)
tg (CPTG
uid 5681,0
uid 6473,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5682,0
uid 6474,0
va (VaSet
font "Verdana,12,0"
)
@ -1417,10 +1417,10 @@ suid 13,0
)
)
*44 (CptPort
uid 5684,0
uid 6475,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5685,0
uid 6476,0
ro 270
va (VaSet
vasetType 1
@ -1429,11 +1429,11 @@ fg "0,65535,0"
xt "55000,54625,55750,55375"
)
tg (CPTG
uid 5686,0
uid 6477,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5687,0
uid 6478,0
va (VaSet
font "Verdana,12,0"
)
@ -1453,10 +1453,10 @@ suid 14,0
)
)
*45 (CptPort
uid 5689,0
uid 6479,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5690,0
uid 6480,0
ro 270
va (VaSet
vasetType 1
@ -1465,11 +1465,11 @@ fg "0,65535,0"
xt "55000,56625,55750,57375"
)
tg (CPTG
uid 5691,0
uid 6481,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5692,0
uid 6482,0
va (VaSet
font "Verdana,12,0"
)
@ -1489,10 +1489,10 @@ suid 15,0
)
)
*46 (CptPort
uid 5694,0
uid 6483,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5695,0
uid 6484,0
ro 90
va (VaSet
vasetType 1
@ -1501,11 +1501,11 @@ fg "0,65535,0"
xt "38250,44625,39000,45375"
)
tg (CPTG
uid 5696,0
uid 6485,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5697,0
uid 6486,0
va (VaSet
font "Verdana,12,0"
)
@ -1525,10 +1525,10 @@ suid 16,0
)
)
*47 (CptPort
uid 5699,0
uid 6487,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5700,0
uid 6488,0
ro 270
va (VaSet
vasetType 1
@ -1537,11 +1537,11 @@ fg "0,65535,0"
xt "38250,48625,39000,49375"
)
tg (CPTG
uid 5701,0
uid 6489,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5702,0
uid 6490,0
va (VaSet
font "Verdana,12,0"
)
@ -1561,10 +1561,10 @@ suid 2017,0
)
)
*48 (CptPort
uid 5704,0
uid 6491,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5705,0
uid 6492,0
ro 270
va (VaSet
vasetType 1
@ -1573,11 +1573,11 @@ fg "0,65535,0"
xt "38250,50625,39000,51375"
)
tg (CPTG
uid 5706,0
uid 6493,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5707,0
uid 6494,0
va (VaSet
font "Verdana,12,0"
)
@ -1597,10 +1597,10 @@ suid 2018,0
)
)
*49 (CptPort
uid 5709,0
uid 6495,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5710,0
uid 6496,0
ro 270
va (VaSet
vasetType 1
@ -1609,11 +1609,11 @@ fg "0,65535,0"
xt "38250,52625,39000,53375"
)
tg (CPTG
uid 5711,0
uid 6497,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5712,0
uid 6498,0
va (VaSet
font "Verdana,12,0"
)
@ -1633,10 +1633,10 @@ suid 2019,0
)
)
*50 (CptPort
uid 5714,0
uid 6499,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5715,0
uid 6500,0
ro 270
va (VaSet
vasetType 1
@ -1645,11 +1645,11 @@ fg "0,65535,0"
xt "38250,54625,39000,55375"
)
tg (CPTG
uid 5716,0
uid 6501,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5717,0
uid 6502,0
va (VaSet
font "Verdana,12,0"
)
@ -1669,10 +1669,10 @@ suid 2020,0
)
)
*51 (CptPort
uid 5719,0
uid 6503,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5720,0
uid 6504,0
ro 270
va (VaSet
vasetType 1
@ -1681,11 +1681,11 @@ fg "0,65535,0"
xt "38250,56625,39000,57375"
)
tg (CPTG
uid 5721,0
uid 6505,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5722,0
uid 6506,0
va (VaSet
font "Verdana,12,0"
)
@ -1705,10 +1705,10 @@ suid 2021,0
)
)
*52 (CptPort
uid 5724,0
uid 6507,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5725,0
uid 6508,0
va (VaSet
vasetType 1
fg "0,65535,0"
@ -1716,18 +1716,19 @@ fg "0,65535,0"
xt "46625,34250,47375,35000"
)
tg (CPTG
uid 5726,0
uid 6509,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5727,0
uid 6510,0
ro 270
va (VaSet
font "Verdana,12,0"
)
xt "44000,36000,49600,37400"
xt "46300,36000,47700,41600"
st "testOut"
ju 2
blo "49600,37200"
blo "47500,36000"
)
)
thePort (LogicalPort
@ -1735,7 +1736,7 @@ m 1
decl (Decl
n "testOut"
t "std_uLogic_vector"
b "(1 DOWNTO 0)"
b "(1 to 16)"
o 21
suid 2022,0
)
@ -1743,7 +1744,7 @@ suid 2022,0
)
]
shape (Rectangle
uid 5730,0
uid 6512,0
va (VaSet
vasetType 1
fg "0,65535,0"
@ -1754,12 +1755,12 @@ xt "39000,35000,55000,67000"
)
oxt "40000,2000,56000,34000"
ttg (MlTextGroup
uid 5731,0
uid 6513,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*53 (Text
uid 5732,0
uid 6514,0
va (VaSet
font "Verdana,8,1"
)
@ -1769,7 +1770,7 @@ blo "39100,67500"
tm "BdLibraryNameMgr"
)
*54 (Text
uid 5733,0
uid 6515,0
va (VaSet
font "Verdana,8,1"
)
@ -1779,7 +1780,7 @@ blo "39100,68500"
tm "CptNameMgr"
)
*55 (Text
uid 5734,0
uid 6516,0
va (VaSet
font "Verdana,8,1"
)
@ -1791,12 +1792,12 @@ tm "InstanceNameMgr"
]
)
ga (GenericAssociation
uid 5735,0
uid 6517,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 5736,0
uid 6518,0
text (MLText
uid 5737,0
uid 6519,0
va (VaSet
font "Courier New,8,0"
)
@ -2531,8 +2532,8 @@ tm "BdCompilerDirectivesTextMgr"
]
associable 1
)
windowSize "0,0,1537,960"
viewArea "-3100,25591,97693,87499"
windowSize "0,14,1921,1080"
viewArea "-3700,26953,126661,99179"
cachedDiagramExtent "-7000,-1400,102000,93000"
pageSetupInfo (PageSetupInfo
ptrCmd "\\\\ipp://ipp.hevs.ch\\PREA309_HPLJP3005DN,winspool,"
@ -2559,7 +2560,7 @@ boundaryWidth 0
)
hasePageBreakOrigin 1
pageBreakOrigin "-7000,19000"
lastUid 5843,0
lastUid 6572,0
defaultCommentText (CommentText
shape (Rectangle
layer 0

File diff suppressed because it is too large Load Diff

View File

@ -1,118 +0,0 @@
ARCHITECTURE test OF cursor_tester IS
constant clockPeriod: time := 50 ns;
signal sClock: std_uLogic := '1';
constant pulsesPerTurn: integer := 200;
constant stepPeriodNb: positive := 8;
signal stepEn: std_uLogic := '0';
signal direction: std_uLogic;
signal turning: std_uLogic;
signal stepCount: unsigned(10 downto 0) := (others => '0');
BEGIN
------------------------------------------------------------------------------
-- clock and reset
--
reset <= '1', '0' after clockPeriod/4;
sClock <= not sClock after clockPeriod/2;
clock <= sClock after clockPeriod/10;
------------------------------------------------------------------------------
-- test sequence
--
process
begin
testMode <= '1';
restart <= '0';
go1 <= '0';
go2 <= '0';
setPoint <= '0';
sensor1 <= '0';
sensor2 <= '0';
wait for 1 us;
----------------------------------------------------------------------------
-- advance to first stop point
go1 <= '1', '0' after 1 us;
wait for 4 ms;
----------------------------------------------------------------------------
-- advance to second stop point
go2 <= '1', '0' after 1 us;
wait for 4 ms;
----------------------------------------------------------------------------
-- back to start with sensor reset
restart <= '1', '0' after 1 us;
wait for 0.5 ms;
sensor1 <= '1', '0' after 1 us;
wait for 0.5 ms;
----------------------------------------------------------------------------
-- advance to second stop point
go2 <= '1', '0' after 1 us;
wait for 7 ms;
----------------------------------------------------------------------------
-- go back to first stop point
go1 <= '1', '0' after 1 us;
wait for 4 ms;
----------------------------------------------------------------------------
-- back to start with counter stop
restart <= '1', '0' after 1 us;
wait for 4 ms;
sensor1 <= '1', '0' after 1 us;
wait for 1 ms;
wait;
end process;
------------------------------------------------------------------------------
-- motor feedback
--
turning <= motorOn;
findDirection: process(side1, side2)
begin
if (side1 = '1') and (side2 = '0') then
direction <= '1';
elsif (side1 = '0') and (side2 = '1') then
direction <= '0';
end if;
end process findDirection;
stepEn <= not stepEn after (stepPeriodNb/4)*clockPeriod;
count: process (stepEn)
begin
if turning = '1' then
if direction = '1' then
if stepCount < pulsesPerTurn-1 then
stepCount <= stepCount + 1;
else
stepCount <= to_unsigned(0, stepCount'length);
end if;
else
if stepCount > 0 then
stepCount <= stepCount - 1;
else
stepCount <= to_unsigned(pulsesPerTurn-1, stepCount'length);
end if;
end if;
end if;
end process count;
encoderA <= stepCount(1);
encoderB <= not stepCount(1) xor stepCount(0);
encoderI <= '1' when stepCount = pulsesPerTurn-1 else '0';
END test;

File diff suppressed because it is too large Load Diff

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@ -10,7 +10,7 @@ appVersion "2019.2 (Build 5)"
model (Symbol
commonDM (CommonDM
ldm (LogicalDM
suid 2001,0
suid 2003,0
usingSuid 1
emptyRow *1 (LEmptyRow
)
@ -328,23 +328,23 @@ value " "
)
(vvPair
variable "HDLDir"
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hdl"
value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor_test\\hdl"
)
(vvPair
variable "HDSDir"
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds"
value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor_test\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\pulse@width@modulator_tb\\symbol.sb.info"
value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor_test\\hds\\pulse@width@modulator_tb\\symbol.sb.info"
)
(vvPair
variable "SideDataUserDir"
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\pulse@width@modulator_tb\\symbol.sb.user"
value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor_test\\hds\\pulse@width@modulator_tb\\symbol.sb.user"
)
(vvPair
variable "SourceDir"
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds"
value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor_test\\hds"
)
(vvPair
variable "appl"
@ -364,27 +364,27 @@ value "%(unit)_%(view)_config"
)
(vvPair
variable "d"
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\pulse@width@modulator_tb"
value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor_test\\hds\\pulse@width@modulator_tb"
)
(vvPair
variable "d_logical"
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\pulseWidthModulator_tb"
value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor_test\\hds\\pulseWidthModulator_tb"
)
(vvPair
variable "date"
value "11.11.2019"
value "14.01.2022"
)
(vvPair
variable "day"
value "Mon"
value "ven."
)
(vvPair
variable "day_long"
value "Monday"
value "vendredi"
)
(vvPair
variable "dd"
value "11"
value "14"
)
(vvPair
variable "entity_name"
@ -408,11 +408,11 @@ value "symbol"
)
(vvPair
variable "graphical_source_author"
value "silvan.zahno"
value "Simon"
)
(vvPair
variable "graphical_source_date"
value "11.11.2019"
value "14.01.2022"
)
(vvPair
variable "graphical_source_group"
@ -420,11 +420,11 @@ value "UNKNOWN"
)
(vvPair
variable "graphical_source_host"
value "WE6996"
value "PC-SDM"
)
(vvPair
variable "graphical_source_time"
value "08:13:21"
value "08:40:19"
)
(vvPair
variable "group"
@ -432,7 +432,7 @@ value "UNKNOWN"
)
(vvPair
variable "host"
value "WE6996"
value "PC-SDM"
)
(vvPair
variable "language"
@ -452,7 +452,7 @@ value "$SCRATCH_DIR/Cursor_test/work"
)
(vvPair
variable "mm"
value "11"
value "01"
)
(vvPair
variable "module_name"
@ -460,19 +460,19 @@ value "pulseWidthModulator_tb"
)
(vvPair
variable "month"
value "Nov"
value "janv."
)
(vvPair
variable "month_long"
value "November"
value "janvier"
)
(vvPair
variable "p"
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\pulse@width@modulator_tb\\symbol.sb"
value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor_test\\hds\\pulse@width@modulator_tb\\symbol.sb"
)
(vvPair
variable "p_logical"
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\pulseWidthModulator_tb\\symbol.sb"
value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor_test\\hds\\pulseWidthModulator_tb\\symbol.sb"
)
(vvPair
variable "package_name"
@ -500,7 +500,7 @@ value "symbol"
)
(vvPair
variable "time"
value "08:13:21"
value "08:40:19"
)
(vvPair
variable "unit"
@ -508,7 +508,7 @@ value "pulseWidthModulator_tb"
)
(vvPair
variable "user"
value "silvan.zahno"
value "Simon"
)
(vvPair
variable "version"
@ -520,11 +520,11 @@ value "symbol"
)
(vvPair
variable "year"
value "2019"
value "2022"
)
(vvPair
variable "yy"
value "19"
value "22"
)
]
)
@ -539,7 +539,7 @@ va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "29000,13000,43000,27000"
xt "29000,13000,51000,27000"
)
oxt "15000,6000,20000,26000"
biTextGroup (BiTextGroup
@ -671,7 +671,7 @@ va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "27200,47400,42300,48600"
xt "27200,47400,42900,48600"
st "
by %user on %dd %month %year
"
@ -1222,5 +1222,5 @@ xt "0,3400,0,3400"
tm "SyDeclarativeTextMgr"
)
)
lastUid 111,0
lastUid 217,0
)

View File

@ -10,9 +10,14 @@ unitName "std_logic_1164"
library "ieee"
unitName "numeric_std"
)
(DmPackageRef
library "gates"
unitName "gates"
)
]
libraryRefs [
"ieee"
"gates"
]
)
version "27.1"
@ -20,7 +25,7 @@ appVersion "2019.2 (Build 5)"
model (Symbol
commonDM (CommonDM
ldm (LogicalDM
suid 2015,0
suid 2031,0
usingSuid 1
emptyRow *1 (LEmptyRow
)
@ -63,68 +68,32 @@ tm "EolColHdrMgr"
port (LogicalPort
m 1
decl (Decl
n "amplitude"
t "unsigned"
b "(counterBitNb-1 DOWNTO 0)"
o 2
suid 2011,0
)
)
uid 280,0
)
*15 (LogPort
port (LogicalPort
m 1
decl (Decl
n "clock"
t "std_ulogic"
o 3
suid 2012,0
suid 2030,0
)
)
uid 282,0
uid 490,0
)
*16 (LogPort
port (LogicalPort
m 1
decl (Decl
n "en"
t "std_ulogic"
o 4
suid 2013,0
)
)
uid 284,0
)
*17 (LogPort
port (LogicalPort
decl (Decl
n "PWM"
t "std_ulogic"
o 1
suid 2014,0
)
)
uid 286,0
)
*18 (LogPort
*15 (LogPort
port (LogicalPort
m 1
decl (Decl
n "reset"
t "std_ulogic"
o 5
suid 2015,0
suid 2031,0
)
)
uid 288,0
uid 492,0
)
]
)
pdm (PhysicalDM
uid 193,0
optionalChildren [
*19 (Sheet
*16 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
@ -141,61 +110,43 @@ cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *20 (MRCItem
emptyMRCItem *17 (MRCItem
litem &1
pos 3
dimension 20
)
uid 128,0
optionalChildren [
*21 (MRCItem
*18 (MRCItem
litem &2
pos 0
dimension 20
uid 131,0
)
*22 (MRCItem
*19 (MRCItem
litem &3
pos 1
dimension 23
uid 133,0
)
*23 (MRCItem
*20 (MRCItem
litem &4
pos 2
hidden 1
dimension 20
uid 135,0
)
*24 (MRCItem
*21 (MRCItem
litem &14
pos 0
dimension 20
uid 281,0
uid 491,0
)
*25 (MRCItem
*22 (MRCItem
litem &15
pos 1
dimension 20
uid 283,0
)
*26 (MRCItem
litem &16
pos 2
dimension 20
uid 285,0
)
*27 (MRCItem
litem &17
pos 3
dimension 20
uid 287,0
)
*28 (MRCItem
litem &18
pos 4
dimension 20
uid 289,0
uid 493,0
)
]
)
@ -208,49 +159,49 @@ textAngle 90
)
uid 129,0
optionalChildren [
*29 (MRCItem
*23 (MRCItem
litem &5
pos 0
dimension 20
uid 137,0
)
*30 (MRCItem
*24 (MRCItem
litem &7
pos 1
dimension 50
uid 141,0
)
*31 (MRCItem
*25 (MRCItem
litem &8
pos 2
dimension 100
uid 143,0
)
*32 (MRCItem
*26 (MRCItem
litem &9
pos 3
dimension 50
uid 145,0
)
*33 (MRCItem
*27 (MRCItem
litem &10
pos 4
dimension 100
uid 147,0
)
*34 (MRCItem
*28 (MRCItem
litem &11
pos 5
dimension 100
uid 149,0
)
*35 (MRCItem
*29 (MRCItem
litem &12
pos 6
dimension 50
uid 151,0
)
*36 (MRCItem
*30 (MRCItem
litem &13
pos 7
dimension 80
@ -271,41 +222,41 @@ uid 186,0
)
genericsCommonDM (CommonDM
ldm (LogicalDM
emptyRow *37 (LEmptyRow
emptyRow *31 (LEmptyRow
)
uid 195,0
optionalChildren [
*38 (RefLabelRowHdr
*32 (RefLabelRowHdr
)
*39 (TitleRowHdr
*33 (TitleRowHdr
)
*40 (FilterRowHdr
*34 (FilterRowHdr
)
*41 (RefLabelColHdr
*35 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*42 (RowExpandColHdr
*36 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*43 (GroupColHdr
*37 (GroupColHdr
tm "GroupColHdrMgr"
)
*44 (NameColHdr
*38 (NameColHdr
tm "GenericNameColHdrMgr"
)
*45 (TypeColHdr
*39 (TypeColHdr
tm "GenericTypeColHdrMgr"
)
*46 (InitColHdr
*40 (InitColHdr
tm "GenericValueColHdrMgr"
)
*47 (PragmaColHdr
*41 (PragmaColHdr
tm "GenericPragmaColHdrMgr"
)
*48 (EolColHdr
*42 (EolColHdr
tm "GenericEolColHdrMgr"
)
*49 (LogGeneric
*43 (LogGeneric
generic (GiElement
name "counterBitNb"
type "positive"
@ -318,7 +269,7 @@ uid 184,0
pdm (PhysicalDM
uid 196,0
optionalChildren [
*50 (Sheet
*44 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
@ -335,34 +286,34 @@ cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *51 (MRCItem
litem &37
emptyMRCItem *45 (MRCItem
litem &31
pos 3
dimension 20
)
uid 160,0
optionalChildren [
*52 (MRCItem
litem &38
*46 (MRCItem
litem &32
pos 0
dimension 20
uid 163,0
)
*53 (MRCItem
litem &39
*47 (MRCItem
litem &33
pos 1
dimension 23
uid 165,0
)
*54 (MRCItem
litem &40
*48 (MRCItem
litem &34
pos 2
hidden 1
dimension 20
uid 167,0
)
*55 (MRCItem
litem &49
*49 (MRCItem
litem &43
pos 0
dimension 20
uid 185,0
@ -378,44 +329,44 @@ textAngle 90
)
uid 161,0
optionalChildren [
*56 (MRCItem
litem &41
*50 (MRCItem
litem &35
pos 0
dimension 20
uid 169,0
)
*57 (MRCItem
litem &43
*51 (MRCItem
litem &37
pos 1
dimension 50
uid 173,0
)
*58 (MRCItem
litem &44
*52 (MRCItem
litem &38
pos 2
dimension 100
uid 175,0
)
*59 (MRCItem
litem &45
*53 (MRCItem
litem &39
pos 3
dimension 100
uid 177,0
)
*60 (MRCItem
litem &46
*54 (MRCItem
litem &40
pos 4
dimension 50
uid 179,0
)
*61 (MRCItem
litem &47
*55 (MRCItem
litem &41
pos 5
dimension 50
uid 181,0
)
*62 (MRCItem
litem &48
*56 (MRCItem
litem &42
pos 6
dimension 80
uid 183,0
@ -442,23 +393,23 @@ value " "
)
(vvPair
variable "HDLDir"
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hdl"
value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor_test\\hdl"
)
(vvPair
variable "HDSDir"
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds"
value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor_test\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\pulse@width@modulator_tester\\interface.info"
value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor_test\\hds\\pulse@width@modulator_tester\\interface.info"
)
(vvPair
variable "SideDataUserDir"
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\pulse@width@modulator_tester\\interface.user"
value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor_test\\hds\\pulse@width@modulator_tester\\interface.user"
)
(vvPair
variable "SourceDir"
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds"
value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor_test\\hds"
)
(vvPair
variable "appl"
@ -478,27 +429,27 @@ value "%(unit)_%(view)_config"
)
(vvPair
variable "d"
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\pulse@width@modulator_tester"
value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor_test\\hds\\pulse@width@modulator_tester"
)
(vvPair
variable "d_logical"
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\pulseWidthModulator_tester"
value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor_test\\hds\\pulseWidthModulator_tester"
)
(vvPair
variable "date"
value "11.11.2019"
value "14.01.2022"
)
(vvPair
variable "day"
value "Mon"
value "ven."
)
(vvPair
variable "day_long"
value "Monday"
value "vendredi"
)
(vvPair
variable "dd"
value "11"
value "14"
)
(vvPair
variable "entity_name"
@ -522,11 +473,11 @@ value "interface"
)
(vvPair
variable "graphical_source_author"
value "silvan.zahno"
value "Simon"
)
(vvPair
variable "graphical_source_date"
value "11.11.2019"
value "14.01.2022"
)
(vvPair
variable "graphical_source_group"
@ -534,11 +485,11 @@ value "UNKNOWN"
)
(vvPair
variable "graphical_source_host"
value "WE6996"
value "PC-SDM"
)
(vvPair
variable "graphical_source_time"
value "08:13:22"
value "09:04:38"
)
(vvPair
variable "group"
@ -546,7 +497,7 @@ value "UNKNOWN"
)
(vvPair
variable "host"
value "WE6996"
value "PC-SDM"
)
(vvPair
variable "language"
@ -566,7 +517,7 @@ value "$SCRATCH_DIR/Cursor_test/work"
)
(vvPair
variable "mm"
value "11"
value "01"
)
(vvPair
variable "module_name"
@ -574,19 +525,19 @@ value "pulseWidthModulator_tester"
)
(vvPair
variable "month"
value "Nov"
value "janv."
)
(vvPair
variable "month_long"
value "November"
value "janvier"
)
(vvPair
variable "p"
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\pulse@width@modulator_tester\\interface"
value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor_test\\hds\\pulse@width@modulator_tester\\interface"
)
(vvPair
variable "p_logical"
value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Cursor_test\\hds\\pulseWidthModulator_tester\\interface"
value "C:\\Users\\Simon\\Desktop\\ELN\\Projet\\Cursor\\Prefs\\..\\Cursor_test\\hds\\pulseWidthModulator_tester\\interface"
)
(vvPair
variable "package_name"
@ -614,7 +565,7 @@ value "interface"
)
(vvPair
variable "time"
value "08:13:22"
value "09:04:38"
)
(vvPair
variable "unit"
@ -622,7 +573,7 @@ value "pulseWidthModulator_tester"
)
(vvPair
variable "user"
value "silvan.zahno"
value "Simon"
)
(vvPair
variable "version"
@ -634,73 +585,25 @@ value "interface"
)
(vvPair
variable "year"
value "2019"
value "2022"
)
(vvPair
variable "yy"
value "19"
value "22"
)
]
)
LanguageMgr "VhdlLangMgr"
uid 76,0
optionalChildren [
*63 (SymbolBody
*57 (SymbolBody
uid 8,0
optionalChildren [
*64 (CptPort
uid 255,0
*58 (CptPort
uid 480,0
ps "OnEdgeStrategy"
shape (Triangle
uid 256,0
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "22625,5250,23375,6000"
)
tg (CPTG
uid 257,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 258,0
ro 270
va (VaSet
font "Verdana,12,0"
)
xt "22300,7000,23700,14000"
st "amplitude"
ju 2
blo "23500,7000"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 259,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,2800,73500,3600"
st "amplitude : OUT unsigned (counterBitNb-1 DOWNTO 0) ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "amplitude"
t "unsigned"
b "(counterBitNb-1 DOWNTO 0)"
o 2
suid 2011,0
)
)
)
*65 (CptPort
uid 260,0
ps "OnEdgeStrategy"
shape (Triangle
uid 261,0
uid 481,0
va (VaSet
vasetType 1
fg "0,65535,0"
@ -708,11 +611,11 @@ fg "0,65535,0"
xt "28625,5250,29375,6000"
)
tg (CPTG
uid 262,0
uid 482,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 263,0
uid 483,0
ro 270
va (VaSet
font "Verdana,12,0"
@ -725,12 +628,12 @@ tm "CptPortNameMgr"
)
)
dt (MLText
uid 264,0
uid 484,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,3600,61500,4400"
st "clock : OUT std_ulogic ;
xt "44000,2000,59500,2800"
st "clock : OUT std_ulogic ;
"
)
thePort (LogicalPort
@ -739,109 +642,15 @@ decl (Decl
n "clock"
t "std_ulogic"
o 3
suid 2012,0
suid 2030,0
)
)
)
*66 (CptPort
uid 265,0
*59 (CptPort
uid 485,0
ps "OnEdgeStrategy"
shape (Triangle
uid 266,0
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "24625,5250,25375,6000"
)
tg (CPTG
uid 267,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 268,0
ro 270
va (VaSet
font "Verdana,12,0"
)
xt "24300,7000,25700,9400"
st "en"
ju 2
blo "25500,7000"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 269,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,4400,61500,5200"
st "en : OUT std_ulogic ;
"
)
thePort (LogicalPort
m 1
decl (Decl
n "en"
t "std_ulogic"
o 4
suid 2013,0
)
)
)
*67 (CptPort
uid 270,0
ps "OnEdgeStrategy"
shape (Triangle
uid 271,0
ro 180
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "58625,5250,59375,6000"
)
tg (CPTG
uid 272,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 273,0
ro 270
va (VaSet
font "Verdana,12,0"
)
xt "58300,7000,59700,10900"
st "PWM"
ju 2
blo "59500,7000"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 274,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,2000,61500,2800"
st "PWM : IN std_ulogic ;
"
)
thePort (LogicalPort
decl (Decl
n "PWM"
t "std_ulogic"
o 1
suid 2014,0
)
)
)
*68 (CptPort
uid 275,0
ps "OnEdgeStrategy"
shape (Triangle
uid 276,0
uid 486,0
va (VaSet
vasetType 1
fg "0,65535,0"
@ -849,11 +658,11 @@ fg "0,65535,0"
xt "30625,5250,31375,6000"
)
tg (CPTG
uid 277,0
uid 487,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 278,0
uid 488,0
ro 270
va (VaSet
font "Verdana,12,0"
@ -866,12 +675,12 @@ tm "CptPortNameMgr"
)
)
dt (MLText
uid 279,0
uid 489,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,5200,60500,6000"
st "reset : OUT std_ulogic
xt "44000,2800,58500,3600"
st "reset : OUT std_ulogic
"
)
thePort (LogicalPort
@ -880,7 +689,7 @@ decl (Decl
n "reset"
t "std_ulogic"
o 5
suid 2015,0
suid 2031,0
)
)
)
@ -918,7 +727,7 @@ st "pulseWidthModulator_tester"
blo "32900,11000"
)
)
gi *69 (GenericInterface
gi *60 (GenericInterface
uid 13,0
ps "CenterOffsetStrategy"
matrix (Matrix
@ -954,10 +763,10 @@ sTC 0
sF 0
)
)
*70 (Grouping
*61 (Grouping
uid 16,0
optionalChildren [
*71 (CommentText
*62 (CommentText
uid 18,0
shape (Rectangle
uid 19,0
@ -987,7 +796,7 @@ visibleWidth 17000
position 1
ignorePrefs 1
)
*72 (CommentText
*63 (CommentText
uid 21,0
shape (Rectangle
uid 22,0
@ -1017,7 +826,7 @@ visibleWidth 4000
position 1
ignorePrefs 1
)
*73 (CommentText
*64 (CommentText
uid 24,0
shape (Rectangle
uid 25,0
@ -1047,7 +856,7 @@ visibleWidth 17000
position 1
ignorePrefs 1
)
*74 (CommentText
*65 (CommentText
uid 27,0
shape (Rectangle
uid 28,0
@ -1077,7 +886,7 @@ visibleWidth 4000
position 1
ignorePrefs 1
)
*75 (CommentText
*66 (CommentText
uid 30,0
shape (Rectangle
uid 31,0
@ -1106,7 +915,7 @@ visibleWidth 20000
)
ignorePrefs 1
)
*76 (CommentText
*67 (CommentText
uid 33,0
shape (Rectangle
uid 34,0
@ -1136,7 +945,7 @@ visibleWidth 16000
position 1
ignorePrefs 1
)
*77 (CommentText
*68 (CommentText
uid 36,0
shape (Rectangle
uid 37,0
@ -1166,7 +975,7 @@ visibleWidth 21000
position 1
ignorePrefs 1
)
*78 (CommentText
*69 (CommentText
uid 39,0
shape (Rectangle
uid 40,0
@ -1196,7 +1005,7 @@ visibleWidth 4000
position 1
ignorePrefs 1
)
*79 (CommentText
*70 (CommentText
uid 42,0
shape (Rectangle
uid 43,0
@ -1226,7 +1035,7 @@ visibleWidth 4000
position 1
ignorePrefs 1
)
*80 (CommentText
*71 (CommentText
uid 45,0
shape (Rectangle
uid 46,0
@ -1281,11 +1090,11 @@ xShown 1
yShown 1
color "26368,26368,26368"
)
packageList *81 (PackageList
packageList *72 (PackageList
uid 48,0
stg "VerticalLayoutStrategy"
textVec [
*82 (Text
*73 (Text
uid 49,0
va (VaSet
font "arial,8,1"
@ -1294,14 +1103,16 @@ xt "0,0,5400,1000"
st "Package List"
blo "0,800"
)
*83 (MLText
*74 (MLText
uid 50,0
va (VaSet
)
xt "0,1000,17500,4600"
xt "0,1000,17500,7000"
st "LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;"
USE ieee.numeric_std.all;
LIBRARY gates;
USE gates.gates.all;"
tm "PackageList"
)
]
@ -1421,7 +1232,7 @@ st "<cell>"
blo "22600,17000"
)
)
gi *84 (GenericInterface
gi *75 (GenericInterface
ps "CenterOffsetStrategy"
matrix (Matrix
text (MLText
@ -1513,7 +1324,7 @@ o 0
)
)
)
DeclarativeBlock *85 (SymDeclBlock
DeclarativeBlock *76 (SymDeclBlock
uid 1,0
stg "SymDeclLayoutStrategy"
declLabel (Text
@ -1539,9 +1350,9 @@ uid 4,0
va (VaSet
font "Arial,8,1"
)
xt "42000,6000,44400,7000"
xt "42000,3600,44400,4600"
st "User:"
blo "42000,6800"
blo "42000,4400"
)
internalLabel (Text
uid 6,0
@ -1558,7 +1369,7 @@ uid 5,0
va (VaSet
font "Courier New,8,0"
)
xt "44000,7000,44000,7000"
xt "44000,4600,44000,4600"
tm "SyDeclarativeTextMgr"
)
internalText (MLText
@ -1571,5 +1382,5 @@ xt "42000,0,42000,0"
tm "SyDeclarativeTextMgr"
)
)
lastUid 289,0
lastUid 493,0
)

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