mirror of
https://github.com/Klagarge/Cursor.git
synced 2024-11-22 17:43:26 +00:00
test merge
This commit is contained in:
parent
ff74b8e288
commit
a3a3a39e5c
@ -383,23 +383,23 @@ value " "
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)
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(vvPair
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variable "HDLDir"
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value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Board\\hdl"
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value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Board\\hdl"
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)
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(vvPair
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variable "HDSDir"
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value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Board\\hds"
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value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Board\\hds"
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)
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(vvPair
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variable "SideDataDesignDir"
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value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Board\\hds\\@f@p@g@a_cursor\\struct.bd.info"
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value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Board\\hds\\@f@p@g@a_cursor\\struct.bd.info"
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)
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(vvPair
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variable "SideDataUserDir"
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value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Board\\hds\\@f@p@g@a_cursor\\struct.bd.user"
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value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Board\\hds\\@f@p@g@a_cursor\\struct.bd.user"
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)
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(vvPair
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variable "SourceDir"
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value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Board\\hds"
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value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Board\\hds"
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)
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(vvPair
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variable "appl"
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@ -419,27 +419,27 @@ value "%(unit)_%(view)_config"
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)
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(vvPair
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variable "d"
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value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Board\\hds\\@f@p@g@a_cursor"
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value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Board\\hds\\@f@p@g@a_cursor"
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)
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(vvPair
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variable "d_logical"
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value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Board\\hds\\FPGA_cursor"
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value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Board\\hds\\FPGA_cursor"
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)
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(vvPair
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variable "date"
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value "11.11.2019"
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value "30.11.2021"
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)
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(vvPair
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variable "day"
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value "Mon"
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value "mar."
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)
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(vvPair
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variable "day_long"
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value "Monday"
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value "mardi"
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)
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(vvPair
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variable "dd"
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value "11"
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value "30"
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)
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(vvPair
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variable "designName"
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@ -467,11 +467,11 @@ value "struct"
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)
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(vvPair
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variable "graphical_source_author"
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value "silvan.zahno"
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value "remi"
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)
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(vvPair
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variable "graphical_source_date"
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value "11.11.2019"
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value "30.11.2021"
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)
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(vvPair
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variable "graphical_source_group"
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@ -479,11 +479,11 @@ value "UNKNOWN"
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)
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(vvPair
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variable "graphical_source_host"
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value "WE6996"
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value "MARVIN"
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)
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(vvPair
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variable "graphical_source_time"
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value "08:13:01"
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value "09:50:23"
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)
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(vvPair
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variable "group"
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@ -491,7 +491,7 @@ value "UNKNOWN"
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)
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(vvPair
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variable "host"
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value "WE6996"
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value "MARVIN"
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)
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(vvPair
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variable "language"
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@ -531,19 +531,19 @@ value "FPGA_cursor"
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)
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(vvPair
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variable "month"
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value "Nov"
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value "nov."
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)
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(vvPair
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variable "month_long"
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value "November"
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value "novembre"
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)
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(vvPair
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variable "p"
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value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Board\\hds\\@f@p@g@a_cursor\\struct.bd"
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value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Board\\hds\\@f@p@g@a_cursor\\struct.bd"
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)
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(vvPair
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variable "p_logical"
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value "C:\\work\\git\\Education\\eln\\projects\\solution\\eln_cursor\\Prefs\\..\\Board\\hds\\FPGA_cursor\\struct.bd"
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value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Board\\hds\\FPGA_cursor\\struct.bd"
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)
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(vvPair
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variable "package_name"
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@ -611,7 +611,7 @@ value "struct"
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)
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(vvPair
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variable "time"
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value "08:13:01"
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value "09:50:23"
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)
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(vvPair
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variable "unit"
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@ -619,7 +619,7 @@ value "FPGA_cursor"
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)
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(vvPair
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variable "user"
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value "silvan.zahno"
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value "remi"
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)
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(vvPair
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variable "version"
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@ -631,11 +631,11 @@ value "struct"
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)
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(vvPair
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variable "year"
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value "2019"
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value "2021"
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)
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(vvPair
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variable "yy"
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value "19"
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value "21"
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)
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]
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)
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@ -656,7 +656,8 @@ va (VaSet
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isHidden 1
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)
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xt "-5000,100800,8400,102000"
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st "clock : std_ulogic"
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st "clock : std_ulogic
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"
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)
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)
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*2 (Grouping
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@ -1098,7 +1099,8 @@ isHidden 1
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font "Verdana,8,0"
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)
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xt "0,46000,11300,47000"
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st "reset_n : std_ulogic"
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st "reset_n : std_ulogic
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"
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)
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)
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*16 (Net
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@ -1116,7 +1118,8 @@ isHidden 1
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font "Verdana,8,0"
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)
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xt "0,46000,14100,47000"
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st "SIGNAL reset : std_ulogic"
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st "SIGNAL reset : std_ulogic
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"
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)
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)
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*17 (SaComponent
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@ -1315,7 +1318,8 @@ isHidden 1
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font "Verdana,8,0"
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)
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xt "0,46000,11900,47000"
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st "testMode : std_uLogic"
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st "testMode : std_uLogic
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"
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)
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)
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*25 (PortIoIn
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@ -1355,19 +1359,19 @@ va (VaSet
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isHidden 1
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font "Verdana,12,0"
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)
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xt "21500,47300,25000,48600"
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xt "20200,47300,25000,48700"
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st "go2_n"
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ju 2
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blo "25000,48300"
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blo "25000,48500"
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tm "WireNameMgr"
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)
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s (Text
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uid 2173,0
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va (VaSet
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)
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xt "21000,48700,21000,48700"
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xt "20200,48700,20200,48700"
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ju 2
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blo "21000,48700"
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blo "20200,48700"
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tm "SignalTypeMgr"
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)
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)
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@ -2856,7 +2860,8 @@ isHidden 1
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font "Verdana,8,0"
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)
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xt "0,73000,15000,74000"
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st "SIGNAL resetSynch : std_ulogic"
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st "SIGNAL resetSynch : std_ulogic
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"
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)
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)
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*78 (HdlText
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@ -2943,7 +2948,8 @@ isHidden 1
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font "Verdana,8,0"
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)
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xt "-12000,79000,2300,80000"
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st "SIGNAL logic1 : std_uLogic"
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st "SIGNAL logic1 : std_uLogic
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"
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)
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)
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*83 (SaComponent
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@ -3142,7 +3148,8 @@ isHidden 1
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font "Verdana,8,0"
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)
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xt "-12000,79000,3400,80000"
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st "SIGNAL resetSynch_n : std_ulogic"
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st "SIGNAL resetSynch_n : std_ulogic
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"
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)
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)
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*91 (SaComponent
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@ -3394,7 +3401,8 @@ isHidden 1
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font "Verdana,8,0"
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)
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xt "-12000,79000,-600,80000"
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st "LED1 : std_uLogic"
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st "LED1 : std_uLogic
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"
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)
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)
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*100 (PortIoOut
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@ -3465,7 +3473,8 @@ isHidden 1
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font "Verdana,8,0"
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)
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xt "-12000,79000,-800,80000"
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st "LED2 : std_ulogic"
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st "LED2 : std_ulogic
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"
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)
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)
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*102 (Net
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@ -3484,7 +3493,8 @@ isHidden 1
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font "Verdana,8,0"
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)
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xt "-12000,79000,13300,80000"
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||||
st "SIGNAL testOut : std_uLogic_vector(1 TO testLineNb)"
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||||
st "SIGNAL testOut : std_uLogic_vector(1 TO testLineNb)
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||||
"
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||||
)
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||||
)
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||||
*103 (HdlText
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||||
@ -4584,7 +4594,8 @@ isHidden 1
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||||
font "Verdana,8,0"
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||||
)
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||||
xt "-12000,79000,2300,80000"
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||||
st "SIGNAL restart : std_uLogic"
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||||
st "SIGNAL restart : std_uLogic
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||||
"
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||||
)
|
||||
)
|
||||
*146 (Net
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||||
@ -4602,7 +4613,8 @@ isHidden 1
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||||
font "Verdana,8,0"
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||||
)
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||||
xt "-12000,79000,-500,80000"
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||||
st "restart_n : std_uLogic"
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||||
st "restart_n : std_uLogic
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||||
"
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||||
)
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||||
)
|
||||
*147 (Net
|
||||
@ -4620,7 +4632,8 @@ isHidden 1
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||||
font "Verdana,8,0"
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||||
)
|
||||
xt "-12000,79000,3200,80000"
|
||||
st "SIGNAL restartSynch : std_uLogic"
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||||
st "SIGNAL restartSynch : std_uLogic
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||||
"
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||||
)
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||||
)
|
||||
*148 (Net
|
||||
@ -4638,7 +4651,8 @@ isHidden 1
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||||
font "Verdana,8,0"
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||||
)
|
||||
xt "-12000,79000,0,80000"
|
||||
st "sensor1_n : std_uLogic"
|
||||
st "sensor1_n : std_uLogic
|
||||
"
|
||||
)
|
||||
)
|
||||
*149 (Net
|
||||
@ -4656,7 +4670,8 @@ isHidden 1
|
||||
font "Verdana,8,0"
|
||||
)
|
||||
xt "-12000,79000,2800,80000"
|
||||
st "SIGNAL sensor1 : std_uLogic"
|
||||
st "SIGNAL sensor1 : std_uLogic
|
||||
"
|
||||
)
|
||||
)
|
||||
*150 (Net
|
||||
@ -4674,7 +4689,8 @@ isHidden 1
|
||||
font "Verdana,8,0"
|
||||
)
|
||||
xt "-12000,79000,3700,80000"
|
||||
st "SIGNAL sensor1Synch : std_uLogic"
|
||||
st "SIGNAL sensor1Synch : std_uLogic
|
||||
"
|
||||
)
|
||||
)
|
||||
*151 (SaComponent
|
||||
@ -5156,7 +5172,8 @@ isHidden 1
|
||||
font "Verdana,8,0"
|
||||
)
|
||||
xt "-12000,79000,3700,80000"
|
||||
st "SIGNAL sensor2Synch : std_uLogic"
|
||||
st "SIGNAL sensor2Synch : std_uLogic
|
||||
"
|
||||
)
|
||||
)
|
||||
*169 (Net
|
||||
@ -5174,7 +5191,8 @@ isHidden 1
|
||||
font "Verdana,8,0"
|
||||
)
|
||||
xt "-12000,79000,2800,80000"
|
||||
st "SIGNAL sensor2 : std_uLogic"
|
||||
st "SIGNAL sensor2 : std_uLogic
|
||||
"
|
||||
)
|
||||
)
|
||||
*170 (Net
|
||||
@ -5192,7 +5210,8 @@ isHidden 1
|
||||
font "Verdana,8,0"
|
||||
)
|
||||
xt "-12000,79000,0,80000"
|
||||
st "sensor2_n : std_uLogic"
|
||||
st "sensor2_n : std_uLogic
|
||||
"
|
||||
)
|
||||
)
|
||||
*171 (Net
|
||||
@ -5210,7 +5229,8 @@ isHidden 1
|
||||
font "Verdana,8,0"
|
||||
)
|
||||
xt "-12000,79000,0,80000"
|
||||
st "motorOn : std_uLogic"
|
||||
st "motorOn : std_uLogic
|
||||
"
|
||||
)
|
||||
)
|
||||
*172 (PortIoOut
|
||||
@ -5334,7 +5354,8 @@ isHidden 1
|
||||
font "Verdana,8,0"
|
||||
)
|
||||
xt "-12000,79000,-800,80000"
|
||||
st "side1 : std_uLogic"
|
||||
st "side1 : std_uLogic
|
||||
"
|
||||
)
|
||||
)
|
||||
*175 (Net
|
||||
@ -5352,7 +5373,8 @@ isHidden 1
|
||||
font "Verdana,8,0"
|
||||
)
|
||||
xt "-12000,79000,-800,80000"
|
||||
st "side2 : std_uLogic"
|
||||
st "side2 : std_uLogic
|
||||
"
|
||||
)
|
||||
)
|
||||
*176 (Net
|
||||
@ -5370,7 +5392,8 @@ isHidden 1
|
||||
font "Verdana,8,0"
|
||||
)
|
||||
xt "-53000,78600,-38400,79600"
|
||||
st "SIGNAL setPoint : std_uLogic"
|
||||
st "SIGNAL setPoint : std_uLogic
|
||||
"
|
||||
)
|
||||
)
|
||||
*177 (Net
|
||||
@ -5388,7 +5411,8 @@ isHidden 1
|
||||
font "Verdana,8,0"
|
||||
)
|
||||
xt "-53000,78600,-37700,79600"
|
||||
st "SIGNAL go2Synch : std_uLogic"
|
||||
st "SIGNAL go2Synch : std_uLogic
|
||||
"
|
||||
)
|
||||
)
|
||||
*178 (Net
|
||||
@ -5406,7 +5430,8 @@ isHidden 1
|
||||
font "Verdana,8,0"
|
||||
)
|
||||
xt "-53000,78600,-38600,79600"
|
||||
st "SIGNAL go2 : std_uLogic"
|
||||
st "SIGNAL go2 : std_uLogic
|
||||
"
|
||||
)
|
||||
)
|
||||
*179 (Net
|
||||
@ -5424,7 +5449,8 @@ isHidden 1
|
||||
font "Verdana,8,0"
|
||||
)
|
||||
xt "-53000,78600,-41400,79600"
|
||||
st "go2_n : std_uLogic"
|
||||
st "go2_n : std_uLogic
|
||||
"
|
||||
)
|
||||
)
|
||||
*180 (Net
|
||||
@ -5442,7 +5468,8 @@ isHidden 1
|
||||
font "Verdana,8,0"
|
||||
)
|
||||
xt "-53000,78600,-37700,79600"
|
||||
st "SIGNAL go1Synch : std_uLogic"
|
||||
st "SIGNAL go1Synch : std_uLogic
|
||||
"
|
||||
)
|
||||
)
|
||||
*181 (Net
|
||||
@ -5460,7 +5487,8 @@ isHidden 1
|
||||
font "Verdana,8,0"
|
||||
)
|
||||
xt "-53000,78600,-38600,79600"
|
||||
st "SIGNAL go1 : std_uLogic"
|
||||
st "SIGNAL go1 : std_uLogic
|
||||
"
|
||||
)
|
||||
)
|
||||
*182 (Net
|
||||
@ -5478,7 +5506,8 @@ isHidden 1
|
||||
font "Verdana,8,0"
|
||||
)
|
||||
xt "-53000,78600,-41400,79600"
|
||||
st "go1_n : std_uLogic"
|
||||
st "go1_n : std_uLogic
|
||||
"
|
||||
)
|
||||
)
|
||||
*183 (SaComponent
|
||||
@ -6888,7 +6917,8 @@ isHidden 1
|
||||
font "Verdana,8,0"
|
||||
)
|
||||
xt "0,74600,16000,75600"
|
||||
st "SIGNAL encoderASynch : std_uLogic"
|
||||
st "SIGNAL encoderASynch : std_uLogic
|
||||
"
|
||||
)
|
||||
)
|
||||
*235 (Net
|
||||
@ -6906,7 +6936,8 @@ isHidden 1
|
||||
font "Verdana,8,0"
|
||||
)
|
||||
xt "0,74600,16000,75600"
|
||||
st "SIGNAL encoderBSynch : std_uLogic"
|
||||
st "SIGNAL encoderBSynch : std_uLogic
|
||||
"
|
||||
)
|
||||
)
|
||||
*236 (Net
|
||||
@ -6924,7 +6955,8 @@ isHidden 1
|
||||
font "Verdana,8,0"
|
||||
)
|
||||
xt "0,74600,15100,75600"
|
||||
st "SIGNAL encoderB : std_uLogic"
|
||||
st "SIGNAL encoderB : std_uLogic
|
||||
"
|
||||
)
|
||||
)
|
||||
*237 (Net
|
||||
@ -6942,7 +6974,8 @@ isHidden 1
|
||||
font "Verdana,8,0"
|
||||
)
|
||||
xt "0,74600,15800,75600"
|
||||
st "SIGNAL encoderISynch : std_uLogic"
|
||||
st "SIGNAL encoderISynch : std_uLogic
|
||||
"
|
||||
)
|
||||
)
|
||||
*238 (Net
|
||||
@ -6960,7 +6993,8 @@ isHidden 1
|
||||
font "Verdana,8,0"
|
||||
)
|
||||
xt "0,74600,14900,75600"
|
||||
st "SIGNAL encoderI : std_uLogic"
|
||||
st "SIGNAL encoderI : std_uLogic
|
||||
"
|
||||
)
|
||||
)
|
||||
*239 (Net
|
||||
@ -6978,7 +7012,8 @@ isHidden 1
|
||||
font "Verdana,8,0"
|
||||
)
|
||||
xt "0,74600,12100,75600"
|
||||
st "encoderI_n : std_uLogic"
|
||||
st "encoderI_n : std_uLogic
|
||||
"
|
||||
)
|
||||
)
|
||||
*240 (Net
|
||||
@ -6996,7 +7031,8 @@ isHidden 1
|
||||
font "Verdana,8,0"
|
||||
)
|
||||
xt "0,74600,15100,75600"
|
||||
st "SIGNAL encoderA : std_uLogic"
|
||||
st "SIGNAL encoderA : std_uLogic
|
||||
"
|
||||
)
|
||||
)
|
||||
*241 (Net
|
||||
@ -7014,7 +7050,8 @@ isHidden 1
|
||||
font "Verdana,8,0"
|
||||
)
|
||||
xt "0,74600,12300,75600"
|
||||
st "encoderA_n : std_uLogic"
|
||||
st "encoderA_n : std_uLogic
|
||||
"
|
||||
)
|
||||
)
|
||||
*242 (Net
|
||||
@ -7032,7 +7069,8 @@ isHidden 1
|
||||
font "Verdana,8,0"
|
||||
)
|
||||
xt "0,74600,12300,75600"
|
||||
st "encoderB_n : std_uLogic"
|
||||
st "encoderB_n : std_uLogic
|
||||
"
|
||||
)
|
||||
)
|
||||
*243 (Net
|
||||
@ -7049,7 +7087,8 @@ va (VaSet
|
||||
isHidden 1
|
||||
)
|
||||
xt "0,74600,14900,75800"
|
||||
st "button4_n : std_uLogic"
|
||||
st "button4_n : std_uLogic
|
||||
"
|
||||
)
|
||||
)
|
||||
*244 (Net
|
||||
@ -7066,7 +7105,8 @@ va (VaSet
|
||||
isHidden 1
|
||||
)
|
||||
xt "0,74600,20400,75800"
|
||||
st "SIGNAL button4Synch : std_uLogic"
|
||||
st "SIGNAL button4Synch : std_uLogic
|
||||
"
|
||||
)
|
||||
)
|
||||
*245 (PortIoOut
|
||||
@ -7358,7 +7398,8 @@ va (VaSet
|
||||
isHidden 1
|
||||
)
|
||||
xt "0,74600,15700,75800"
|
||||
st "LCD_CS1_n : std_ulogic"
|
||||
st "LCD_CS1_n : std_ulogic
|
||||
"
|
||||
)
|
||||
)
|
||||
*251 (Net
|
||||
@ -7375,7 +7416,8 @@ va (VaSet
|
||||
isHidden 1
|
||||
)
|
||||
xt "0,74600,15000,75800"
|
||||
st "LCD_SCL : std_ulogic"
|
||||
st "LCD_SCL : std_ulogic
|
||||
"
|
||||
)
|
||||
)
|
||||
*252 (Net
|
||||
@ -7392,7 +7434,8 @@ va (VaSet
|
||||
isHidden 1
|
||||
)
|
||||
xt "0,74600,14400,75800"
|
||||
st "LCD_SI : std_ulogic"
|
||||
st "LCD_SI : std_ulogic
|
||||
"
|
||||
)
|
||||
)
|
||||
*253 (Net
|
||||
@ -7409,7 +7452,8 @@ va (VaSet
|
||||
isHidden 1
|
||||
)
|
||||
xt "0,74600,14700,75800"
|
||||
st "LCD_A0 : std_ulogic"
|
||||
st "LCD_A0 : std_ulogic
|
||||
"
|
||||
)
|
||||
)
|
||||
*254 (Net
|
||||
@ -7426,7 +7470,8 @@ va (VaSet
|
||||
isHidden 1
|
||||
)
|
||||
xt "0,74600,15600,75800"
|
||||
st "LCD_RST_n : std_ulogic"
|
||||
st "LCD_RST_n : std_ulogic
|
||||
"
|
||||
)
|
||||
)
|
||||
*255 (SaComponent
|
||||
@ -8308,7 +8353,8 @@ va (VaSet
|
||||
isHidden 1
|
||||
)
|
||||
xt "0,0,22900,1200"
|
||||
st "LEDs : std_uLogic_vector(1 TO 8)"
|
||||
st "LEDs : std_uLogic_vector(1 TO 8)
|
||||
"
|
||||
)
|
||||
)
|
||||
*281 (Wire
|
||||
@ -10994,8 +11040,8 @@ tm "BdCompilerDirectivesTextMgr"
|
||||
]
|
||||
associable 1
|
||||
)
|
||||
windowSize "84,44,1182,895"
|
||||
viewArea "-9157,16860,147244,120270"
|
||||
windowSize "-8,-8,1544,928"
|
||||
viewArea "18874,31564,139926,105439"
|
||||
cachedDiagramExtent "-53000,0,180750,118000"
|
||||
pageSetupInfo (PageSetupInfo
|
||||
ptrCmd "\\\\SUN\\PREA203_HPLJ2430DTN.PRINTERS.SYSTEM.SION.HEVs,winspool,"
|
||||
@ -11022,7 +11068,7 @@ boundaryWidth 0
|
||||
)
|
||||
hasePageBreakOrigin 1
|
||||
pageBreakOrigin "-7000,19000"
|
||||
lastUid 6003,0
|
||||
lastUid 6133,0
|
||||
defaultCommentText (CommentText
|
||||
shape (Rectangle
|
||||
layer 0
|
||||
|
||||
@ -6208,7 +6208,7 @@ yPos 0
|
||||
width 1552
|
||||
height 936
|
||||
activeSidePanelTab 2
|
||||
activeLibraryTab 2
|
||||
activeLibraryTab 3
|
||||
sidePanelSize 278
|
||||
showUnixHiddenFiles 0
|
||||
componentBrowserXpos 569
|
||||
@ -6216,7 +6216,11 @@ componentBrowserYpos 300
|
||||
componentBrowserWidth 300
|
||||
componentBrowserHeight 340
|
||||
componentBrowserLibraryNames [
|
||||
"ADD"
|
||||
"Board"
|
||||
"gates"
|
||||
"Common"
|
||||
"io"
|
||||
"sequential"
|
||||
]
|
||||
)
|
||||
(SmPreferences
|
||||
|
||||
Loading…
Reference in New Issue
Block a user