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SylvanArnold
2025-04-29 13:52:54 +02:00
committed by Sylvan Arnold
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commit 32618389d1
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pico-sensor/McuLib/TraceRecorder/include/trcExtensions.h Normal file
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/*******************************************************************************
* Trace Recorder Library for Tracealyzer v4.4.1
* Percepio AB, www.percepio.com
*
* trcExtensions.h
*
* The extension interface of the recorder library, allowing for tracing
* function calls to any API without modifications. All that is needed is a
* single #include line in the .c files calling the API.
*
* This can be used to provide more detailed traces, including calls to e.g.
* middleware, drivers or important APIs in your application code. This can be
* applied selectively to specified functions and may include selected
* parameters as well as the return value.
*
* Unlike the "User Event" concept, an extension is intended for systematic use
* and can benefit from all powerful features in Tracealyzer via host-side XML
* files that configure how Tracealyzer should interpret each event.
*
* Extensions are self-contained and easy to integrate, which makes them
* convenient for distribution. Software vendors can thus develop such
* extensions and provide trace support for their users.
*
* An extension consists of two files:
*
* - An extension header file (e.g. "api.tzext.h") - this defines how to
* trace the API function calls.
*
* - An XML file for the Tracealyzer application (e.g. "api-v1.0.0.xml").
* This needs to match the tracing setup in your extension header file.
*
*
* USAGE
*
* This description assumes you already have the extension files for the APIs you
* like to trace. To include them, follow these steps:
*
* 1. Update trcExtensions.h with respect to:
*
* 1.1. TRC_CFG_EXTENSION_COUNT: The number of extensions to enable (max 4).
*
* 1.2. The name(s) of the extension header file(s) to include.
*
* 1.3. The Extension Prefix, i.e., the first part of the definition names
* used in each header file.
*
* 2. Add #include "trcExtensions.h" in all .c files calling the API:
*
* #include ...
* #include "api.h" // The API you like to trace
* #include ...
* #include "trcExtensions.h"
*
* We recommend to put this as the LAST #include statement.
*
* HOWEVER, don't include "trcExtensions.h" in the .c files containing the
* functions you intend to trace. The compiler will then complain about
* multiple definitions of the trace wrapper function.
*
* 3. Copy the extension XML file to the "Tracealyzer 4/cfg" folder.
* On Windows this is typically
*
* C:\Program Files\Percepio\Tracealyzer 4\cfg
*
*
* HOW IT WORKS
*
* By including "trcExtensions.h" in your .c files, the preprocessor will
* redefine all calls of the functions specified in the extension header file.
* Calls to those functions will now instead call the "trace wrapper functions"
* defined in the extension header. The trace wrapper functions then call the
* original function as well as the trace recorder library.
*
* call foo(a) ----> foo__trace(a) -----> foo(a)
* -----> trace recorder library
*
* Note that the trace wrapper function should have the same declaration as the
* original function (apart from the name) and also returns any return value
* back to the original caller. So functionally this is completely transparent.
*
* This works also for calls via function pointers, as the assignments of the
* function pointers will be affected, so the function pointers will point to
* the trace wrapper function.
*
* It even works when calling binary libraries, since only the calling code
* is modified, not the API itself.
*
* Extensions include a version code (Major.Minor.Patch), which is registered
* in the trace and also part of the XML file name. This way, Tracealyzer
* automatically finds the matching XML file, even if you open a old trace
* recorded using a earlier version of the extension (e.g. if the API has
* changed).
*
* LIMITATIONS
*
* The main limitation of this automatic approach is that it only allows for
* tracing call between different .c files. Moreover, you can't trace multiple
* APIs with calls between them. This since the calling file must include
* trcExtensions.h, while the called file must NOT include this.
*
* It is however possible to get around this limitation. You need to add
* #undef lines for each affected function to locally disable the redefinition,
* and modify each function call to instead call the trace wrapper function.
*
* #include "trcExtensions.h"
* #undef foo
* ...
* void foo(int a)
* {
* ...
* }
* ...
* foo__trace(a); // in another function - call foo and trace it
*
* These changes can remain in your code if you like, as the trace wrappers
* works even if the recorder is disabled.
*
* MAKING YOUR OWN EXTENSIONS
*
* Examples are found in the extensions directory. We recommend that you start
* by looking at aws_secure_sockets files (.h and .xml) that provides a basic
* example. The aws_wifi files provides a more advanced example.
* The header files include detailed documentation about how to design them,
*
* The XML files should have the same name as specified in the NAME property
* in the header file, followed by the version, i.e.
*
* <NAME>-v<VERSION_MAJOR>.<<VERSION_MINOR>.<VERSION_PATCH>.xml
*
* Documentation for the XML file format is not yet available, but is under
* development.
*
*
* Terms of Use
* This file is part of the trace recorder library (RECORDER), which is the
* intellectual property of Percepio AB (PERCEPIO) and provided under a
* license as follows.
* The RECORDER may be used free of charge for the purpose of recording data
* intended for analysis in PERCEPIO products. It may not be used or modified
* for other purposes without explicit permission from PERCEPIO.
* You may distribute the RECORDER in its original source code form, assuming
* this text (terms of use, disclaimer, copyright notice) is unchanged. You are
* allowed to distribute the RECORDER with minor modifications intended for
* configuration or porting of the RECORDER, e.g., to allow using it on a
* specific processor, processor family or with a specific communication
* interface. Any such modifications should be documented directly below
* this comment block.
*
* Disclaimer
* The RECORDER is being delivered to you AS IS and PERCEPIO makes no warranty
* as to its use or performance. PERCEPIO does not and cannot warrant the
* performance or results you may obtain by using the RECORDER or documentation.
* PERCEPIO make no warranties, express or implied, as to noninfringement of
* third party rights, merchantability, or fitness for any particular purpose.
* In no event will PERCEPIO, its technology partners, or distributors be liable
* to you for any consequential, incidental or special damages, including any
* lost profits or lost savings, even if a representative of PERCEPIO has been
* advised of the possibility of such damages, or for any claim by any third
* party. Some jurisdictions do not allow the exclusion or limitation of
* incidental, consequential or special damages, or the exclusion of implied
* warranties or limitations on how long an implied warranty may last, so the
* above limitations may not apply to you.
*
* Tabs are used for indent in this file (1 tab = 4 spaces)
*
* Copyright Percepio AB, 2018.
* www.percepio.com
******************************************************************************/
#ifndef TRCEXTENSIONS_H_
#define TRCEXTENSIONS_H_
#include "trcRecorder.h"
/******************************************************************************
* TRC_CFG_EXTENSION_COUNT
*
* Defines the number of extensions included in the trace. Maximum 4 extensions
* can be included.
*
* Default value is 0 (extension support disabled).
*
*****************************************************************************/
#define TRC_CFG_EXTENSION_COUNT 0
/******************************************************************************
* TRC_CFG_EXT_MAX_NAME_LEN
*
* Defines the maximum length of extension name(s), i.e. the <EXTENSION>_NAME
* macro(s) in trcExtensions.h.
*
* This value should will by rounded up to the nearest multiple of 4, and must
* not be zero. To disable extension support, see TRC_CFG_EXTENSION_COUNT.
*
* It is important that this setting is large enough so extension names are
* not truncated, otherwise the host-side Tracealyzer application won't be able
* to find the corresponding XML file.
*
* You may adjust this to reduce memory usage, or increase it to allow for
* longer extension names.
*
* Default value is 20.
*****************************************************************************/
#define TRC_CFG_EXT_MAX_NAME_LEN 20
/******************************************************************************
* TRC_EXTENSION_EVENTCODE_BASE
*
* The first event code used for the Extension system. This will be the first
* event code of the first extension, and other event codes are relative to
* this. This can be modified but this is normally not required.
*****************************************************************************/
#define TRC_EXTENSION_EVENTCODE_BASE 256
/*** Included Extensions ******************************************************
*
* Below you specify what extensions to include. For each
* extension you must define:
*
* - HEADER: The header file that defines the trace extension.
*
* - EXTENSION_PREFIX: The first part of the HEADER definition names.
*
*****************************************************************************/
#define TRC_EXT1_HEADER "aws_secure_sockets.tzext.h"
#define TRC_EXT1_PREFIX TRC_EXT_SOCKETS
#define TRC_EXT2_HEADER "aws_wifi.tzext.h"
#define TRC_EXT2_PREFIX TRC_EXT_WIFI
#define TRC_EXT3_HEADER "Here you specify the header file for Extensions 3."
#define TRC_EXT3_PREFIX NOT_DEFINED
#define TRC_EXT4_HEADER "Here you specify the header file for Extensions 4."
#define TRC_EXT4_PREFIX NOT_DEFINED
/*** Don't modify below ******************************************************/
#define ROUNDUP4(n) (4*((n+3)/4))
typedef struct{
uint16_t firstEventCode;
uint16_t lastEventCode;
uint16_t patchVersion;
uint8_t minorVersion;
uint8_t majorVersion;
char name[ROUNDUP4(TRC_CFG_EXT_MAX_NAME_LEN)];
} PSFExtensionEntryType;
typedef struct{
uint16_t extensionEntryCount;
uint16_t baseEventCode;
#if (TRC_CFG_EXTENSION_COUNT > 0)
uint8_t extensionEntryNameMaxLength;
uint8_t extensionEntrySize;
PSFExtensionEntryType extension[TRC_CFG_EXTENSION_COUNT];
#endif
} PSFExtensionInfoType;
extern PSFExtensionInfoType PSFExtensionInfo;
#define CAT(a, ...) PRIMITIVE_CAT(a, __VA_ARGS__)
#define PRIMITIVE_CAT(a, ...) a ## __VA_ARGS__
#define TRC_EXT_BASECODE (PSFExtensionInfo.extension[TRC_EXT_NUMBER-1].firstEventCode)
#if (TRC_CFG_EXTENSION_COUNT >= 1)
#ifdef TRC_EXT1_HEADER
#define TRC_EXT_NUMBER 1
#include TRC_EXT1_HEADER
#undef TRC_EXT_NUMBER
#endif
#endif
#if (TRC_CFG_EXTENSION_COUNT >= 2)
#ifdef TRC_EXT2_HEADER
#define TRC_EXT_NUMBER 2
#include TRC_EXT2_HEADER
#undef TRC_EXT_NUMBER
#endif
#endif
#if (TRC_CFG_EXTENSION_COUNT >= 3)
#ifdef TRC_EXT3_HEADER
#define TRC_EXT_NUMBER 3
#include TRC_EXT3_HEADER
#undef TRC_EXT_NUMBER
#endif
#endif
#if (TRC_CFG_EXTENSION_COUNT == 4)
#ifdef TRC_EXT3_HEADER
#define TRC_EXT_NUMBER 4
#include TRC_EXT4_HEADER
#undef TRC_EXT_NUMBER
#endif
#endif
#define TRC_EXT1_COUNT CAT(TRC_EXT1_PREFIX, _COUNT)
#define TRC_EXT2_COUNT CAT(TRC_EXT2_PREFIX, _COUNT)
#define TRC_EXT3_COUNT CAT(TRC_EXT3_PREFIX, _COUNT)
#define TRC_EXT4_COUNT CAT(TRC_EXT4_PREFIX, _COUNT)
#define TRC_EXT1_NAME CAT(TRC_EXT1_PREFIX, _NAME)
#define TRC_EXT2_NAME CAT(TRC_EXT2_PREFIX, _NAME)
#define TRC_EXT3_NAME CAT(TRC_EXT3_PREFIX, _NAME)
#define TRC_EXT4_NAME CAT(TRC_EXT4_PREFIX, _NAME)
#define TRC_EXT1_VERSION_MAJOR CAT(TRC_EXT1_PREFIX, _VERSION_MAJOR)
#define TRC_EXT2_VERSION_MAJOR CAT(TRC_EXT2_PREFIX, _VERSION_MAJOR)
#define TRC_EXT3_VERSION_MAJOR CAT(TRC_EXT3_PREFIX, _VERSION_MAJOR)
#define TRC_EXT4_VERSION_MAJOR CAT(TRC_EXT4_PREFIX, _VERSION_MAJOR)
#define TRC_EXT1_VERSION_MINOR CAT(TRC_EXT1_PREFIX, _VERSION_MINOR)
#define TRC_EXT2_VERSION_MINOR CAT(TRC_EXT2_PREFIX, _VERSION_MINOR)
#define TRC_EXT3_VERSION_MINOR CAT(TRC_EXT3_PREFIX, _VERSION_MINOR)
#define TRC_EXT4_VERSION_MINOR CAT(TRC_EXT4_PREFIX, _VERSION_MINOR)
#define TRC_EXT1_VERSION_PATCH CAT(TRC_EXT1_PREFIX, _VERSION_PATCH)
#define TRC_EXT2_VERSION_PATCH CAT(TRC_EXT2_PREFIX, _VERSION_PATCH)
#define TRC_EXT3_VERSION_PATCH CAT(TRC_EXT3_PREFIX, _VERSION_PATCH)
#define TRC_EXT4_VERSION_PATCH CAT(TRC_EXT4_PREFIX, _VERSION_PATCH)
#if ((TRC_CFG_EXTENSION_COUNT > 4) || (TRC_CFG_EXTENSION_COUNT < 0))
#error "TRC_CFG_EXTENSION_COUNT must be in range [0..4]"
#endif
#if (TRC_CFG_EXTENSION_COUNT == 0)
#define TRC_EXTENSIONS_DATA
#endif
#if (TRC_CFG_EXTENSION_COUNT == 1)
#define TRC_EXTENSIONS_DATA \
{ \
{ TRC_EXTENSION_EVENTCODE_BASE, \
TRC_EXTENSION_EVENTCODE_BASE + TRC_EXT1_COUNT-1, \
TRC_EXT1_VERSION_PATCH, \
TRC_EXT1_VERSION_MINOR, \
TRC_EXT1_VERSION_MAJOR, \
TRC_EXT1_NAME } \
}
#endif
#if (TRC_CFG_EXTENSION_COUNT == 2)
#define TRC_EXTENSIONS_DATA \
{ \
{ TRC_EXTENSION_EVENTCODE_BASE, \
TRC_EXTENSION_EVENTCODE_BASE + TRC_EXT1_COUNT-1, \
TRC_EXT1_VERSION_PATCH, \
TRC_EXT1_VERSION_MINOR, \
TRC_EXT1_VERSION_MAJOR, \
TRC_EXT1_NAME } \
,{ TRC_EXTENSION_EVENTCODE_BASE + TRC_EXT1_COUNT, \
TRC_EXTENSION_EVENTCODE_BASE + TRC_EXT1_COUNT + TRC_EXT2_COUNT-1, \
TRC_EXT2_VERSION_PATCH, \
TRC_EXT2_VERSION_MINOR, \
TRC_EXT2_VERSION_MAJOR, \
TRC_EXT2_NAME } \
}
#endif
#if (TRC_CFG_EXTENSION_COUNT == 3)
#define TRC_EXTENSIONS_DATA \
{ \
{ TRC_EXTENSION_EVENTCODE_BASE, \
TRC_EXTENSION_EVENTCODE_BASE + TRC_EXT1_COUNT-1, \
TRC_EXT1_VERSION_PATCH, \
TRC_EXT1_VERSION_MINOR, \
TRC_EXT1_VERSION_MAJOR, \
TRC_EXT1_NAME } \
,{ TRC_EXTENSION_EVENTCODE_BASE + TRC_EXT1_COUNT, \
TRC_EXTENSION_EVENTCODE_BASE + TRC_EXT1_COUNT + TRC_EXT2_COUNT-1, \
TRC_EXT2_VERSION_PATCH, \
TRC_EXT2_VERSION_MINOR, \
TRC_EXT2_VERSION_MAJOR, \
TRC_EXT2_NAME } \
,{ TRC_EXTENSION_EVENTCODE_BASE + TRC_EXT1_COUNT + TRC_EXT2_COUNT, \
TRC_EXTENSION_EVENTCODE_BASE + TRC_EXT1_COUNT + TRC_EXT2_COUNT + TRC_EXT3_COUNT - 1, \
TRC_EXT3_VERSION_PATCH, \
TRC_EXT3_VERSION_MINOR, \
TRC_EXT3_VERSION_MAJOR, \
TRC_EXT3_NAME } \
}
#endif
#if (TRC_CFG_EXTENSION_COUNT == 4)
#define TRC_EXTENSIONS_DATA \
{ \
{ TRC_EXTENSION_EVENTCODE_BASE, \
TRC_EXTENSION_EVENTCODE_BASE + TRC_EXT1_COUNT-1, \
TRC_EXT1_VERSION_PATCH, \
TRC_EXT1_VERSION_MINOR, \
TRC_EXT1_VERSION_MAJOR, \
TRC_EXT1_NAME } \
,{ TRC_EXTENSION_EVENTCODE_BASE + TRC_EXT1_COUNT, \
TRC_EXTENSION_EVENTCODE_BASE + TRC_EXT1_COUNT + TRC_EXT2_COUNT-1, \
TRC_EXT2_VERSION_PATCH, \
TRC_EXT2_VERSION_MINOR, \
TRC_EXT2_VERSION_MAJOR, \
TRC_EXT2_NAME } \
,{ TRC_EXTENSION_EVENTCODE_BASE + TRC_EXT1_COUNT + TRC_EXT2_COUNT, \
TRC_EXTENSION_EVENTCODE_BASE + TRC_EXT1_COUNT + TRC_EXT2_COUNT + TRC_EXT3_COUNT - 1, \
TRC_EXT3_VERSION_PATCH, \
TRC_EXT3_VERSION_MINOR, \
TRC_EXT3_VERSION_MAJOR, \
TRC_EXT3_NAME } \
,{ TRC_EXTENSION_EVENTCODE_BASE + TRC_EXT1_COUNT + TRC_EXT2_COUNT + TRC_EXT3_COUNT, \
TRC_EXTENSION_EVENTCODE_BASE + TRC_EXT1_COUNT + TRC_EXT2_COUNT + TRC_EXT3_COUNT + TRC_EXT4_COUNT- 1, \
TRC_EXT4_VERSION_PATCH, \
TRC_EXT4_VERSION_MINOR, \
TRC_EXT4_VERSION_MAJOR, \
TRC_EXT4_NAME } \
}
#endif
#if (TRC_CFG_EXTENSION_COUNT > 0)
#define TRC_EXTENSION_INFO {TRC_CFG_EXTENSION_COUNT, TRC_EXTENSION_EVENTCODE_BASE, ROUNDUP4(TRC_CFG_EXT_MAX_NAME_LEN), sizeof(PSFExtensionEntryType), TRC_EXTENSIONS_DATA}
#else
#define TRC_EXTENSION_INFO {TRC_CFG_EXTENSION_COUNT, TRC_EXTENSION_EVENTCODE_BASE}
#endif
#endif /* TRCEXTENSIONS_H_ */

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pico-sensor/McuLib/TraceRecorder/include/trcHardwarePort.h Normal file
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/*******************************************************************************
* Trace Recorder Library for Tracealyzer v4.4.1
* Percepio AB, www.percepio.com
*
* trcHardwarePort.h
*
* The hardware abstraction layer for the trace recorder.
*
* Terms of Use
* This file is part of the trace recorder library (RECORDER), which is the
* intellectual property of Percepio AB (PERCEPIO) and provided under a
* license as follows.
* The RECORDER may be used free of charge for the purpose of recording data
* intended for analysis in PERCEPIO products. It may not be used or modified
* for other purposes without explicit permission from PERCEPIO.
* You may distribute the RECORDER in its original source code form, assuming
* this text (terms of use, disclaimer, copyright notice) is unchanged. You are
* allowed to distribute the RECORDER with minor modifications intended for
* configuration or porting of the RECORDER, e.g., to allow using it on a
* specific processor, processor family or with a specific communication
* interface. Any such modifications should be documented directly below
* this comment block.
*
* Disclaimer
* The RECORDER is being delivered to you AS IS and PERCEPIO makes no warranty
* as to its use or performance. PERCEPIO does not and cannot warrant the
* performance or results you may obtain by using the RECORDER or documentation.
* PERCEPIO make no warranties, express or implied, as to noninfringement of
* third party rights, merchantability, or fitness for any particular purpose.
* In no event will PERCEPIO, its technology partners, or distributors be liable
* to you for any consequential, incidental or special damages, including any
* lost profits or lost savings, even if a representative of PERCEPIO has been
* advised of the possibility of such damages, or for any claim by any third
* party. Some jurisdictions do not allow the exclusion or limitation of
* incidental, consequential or special damages, or the exclusion of implied
* warranties or limitations on how long an implied warranty may last, so the
* above limitations may not apply to you.
*
* Tabs are used for indent in this file (1 tab = 4 spaces)
*
* Copyright Percepio AB, 2018.
* www.percepio.com
******************************************************************************/
#ifndef TRC_HARDWARE_PORT_H
#define TRC_HARDWARE_PORT_H
#include "trcPortDefines.h"
#if 1 /* << EST */
#include "FreeRTOSConfig.h"
#if configCPU_FAMILY_IS_ARM(configCPU_FAMILY)
#if McuLib_CONFIG_PEX_SDK_USED/* << EST Kinetis SDK is using CMSIS core, therefore the functions below are defined in core_cmFunc.h. For non-SDK projects, define them locally here */
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__attribute__( ( always_inline ) ) static inline uint32_t __get_PRIMASK(void)
{
uint32_t result;
__asm volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__attribute__( ( always_inline ) ) static inline void __set_PRIMASK(uint32_t priMask)
{
__asm volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
}
#elif McuLib_CONFIG_CPU_IS_STM32
#include "stm32f3xx_hal.h" /* header file for STM32F303K8 */
#elif McuLib_CONFIG_CPU_IS_NORDIC_NRF
#include "nrf.h" /* header file Nordic devices */
#else
#include "fsl_device_registers.h"
#endif /* #if McuLib_CONFIG_PEX_SDK_USED */
#endif /* configCPU_FAMILY_IS_ARM */
#endif /* << EST */
#if (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_NOT_SET)
#error "TRC_CFG_HARDWARE_PORT not selected - see trcConfig.h"
#endif
/*******************************************************************************
* TRC_IRQ_PRIORITY_ORDER
*
* Macro which should be defined as an integer of 0 or 1.
*
* This should be 0 if lower IRQ priority values implies higher priority
* levels, such as on ARM Cortex M. If the opposite scheme is used, i.e.,
* if higher IRQ priority values means higher priority, this should be 1.
*
* This setting is not critical. It is used only to sort and colorize the
* interrupts in priority order, in case you record interrupts using
* the vTraceStoreISRBegin and vTraceStoreISREnd routines.
*
******************************************************************************
*
* HWTC Macros
*
* These macros provides a hardware isolation layer representing the
* hardware timer/counter used for the event timestamping.
*
* TRC_HWTC_COUNT: How to read the current value of the timer/counter.
*
* TRC_HWTC_TYPE: Tells the type of timer/counter used for TRC_HWTC_COUNT:
*
* - TRC_FREE_RUNNING_32BIT_INCR:
* Free-running 32-bit timer/counter, counting upwards from 0.
*
* - TRC_FREE_RUNNING_32BIT_DECR
* Free-running 32-bit timer/counter, counting downwards from 0xFFFFFFFF.
*
* - TRC_OS_TIMER_INCR
* Periodic timer that drives the OS tick interrupt, counting upwards
* from 0 until (TRC_HWTC_PERIOD-1).
*
* - TRC_OS_TIMER_DECR
* Periodic timer that drives the OS tick interrupt, counting downwards
* from TRC_HWTC_PERIOD-1 until 0.
*
* - TRC_CUSTOM_TIMER_INCR
* A custom timer or counter independent of the OS tick, counting
* downwards from TRC_HWTC_PERIOD-1 until 0. (Currently only supported
* in streaming mode).
*
* - TRC_CUSTOM_TIMER_DECR
* A custom timer independent of the OS tick, counting downwards
* from TRC_HWTC_PERIOD-1 until 0. (Currently only supported
* in streaming mode).
*
* TRC_HWTC_PERIOD: The number of HWTC_COUNT ticks until the timer wraps
* around. If using TRC_FREE_RUNNING_32BIT_INCR/DECR, this should be 0.
*
* TRC_HWTC_FREQ_HZ: The clock rate of the TRC_HWTC_COUNT counter in Hz. If using
* TRC_OS_TIMER_INCR/DECR, this is should be TRC_HWTC_PERIOD * TRACE_TICK_RATE_HZ.
* If using a free-running timer, this is often TRACE_CPU_CLOCK_HZ (if running at
* the core clock rate). If using TRC_CUSTOM_TIMER_INCR/DECR, this should match
* the clock rate of your custom timer (i.e., TRC_HWTC_COUNT). If the default value
* of TRC_HWTC_FREQ_HZ is incorrect for your setup, you can override it by calling
* vTraceSetFrequency before calling vTraceEnable.
*
* TRC_HWTC_DIVISOR (used in snapshot mode only):
* In snapshot mode, the timestamp resolution is TRC_HWTC_FREQ_HZ/TRC_HWTC_DIVISOR.
* If the timer frequency is very high (hundreds of MHz), we recommend increasing
* the TRC_HWTC_DIVISOR prescaler, to reduce the bandwidth needed to store
* timestamps. This since extra "XTS" events are inserted if the time since the
* previous event exceeds a certain limit (255 or 65535 depending on event type).
* It is advised to keep the time between most events below 65535 native ticks
* (after division by TRC_HWTC_DIVISOR) to avoid frequent XTS events.
******************************************************************************/
#if (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_NOT_SET)
#error "TRC_CFG_HARDWARE_PORT not selected - see trcConfig.h"
#endif
#if (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_Win32)
/* This can be used as a template for any free-running 32-bit counter */
#define TRC_HWTC_TYPE TRC_FREE_RUNNING_32BIT_INCR
#define TRC_HWTC_COUNT (ulGetRunTimeCounterValue())
#define TRC_HWTC_PERIOD 0
#define TRC_HWTC_DIVISOR 1
#define TRC_HWTC_FREQ_HZ 100000
#define TRC_IRQ_PRIORITY_ORDER 1
#define TRC_PORT_SPECIFIC_INIT()
#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_HWIndependent)
/* Timestamping by OS tick only (typically 1 ms resolution) */
#define TRC_HWTC_TYPE TRC_OS_TIMER_INCR
#define TRC_HWTC_COUNT 0
#define TRC_HWTC_PERIOD 1
#define TRC_HWTC_DIVISOR 1
#define TRC_HWTC_FREQ_HZ TRACE_TICK_RATE_HZ
/* Set the meaning of IRQ priorities in ISR tracing - see above */
#define TRC_IRQ_PRIORITY_ORDER NOT_SET
#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_ARM_Cortex_M)
#ifndef __CORTEX_M
#error "Can't find the CMSIS API. Please include your processor's header file in trcConfig.h"
#endif
/**************************************************************************
* For Cortex-M3, M4 and M7, the DWT cycle counter is used for timestamping.
* For Cortex-M0 and M0+, the SysTick timer is used since DWT is not
* available. Systick timestamping can also be forced on Cortex-M3, M4 and
* M7 by defining the preprocessor directive TRC_CFG_ARM_CM_USE_SYSTICK,
* either directly below or in trcConfig.h.
*
* #define TRC_CFG_ARM_CM_USE_SYSTICK
**************************************************************************/
#if ((__CORTEX_M >= 0x03) && (! defined TRC_CFG_ARM_CM_USE_SYSTICK))
void prvTraceInitCortexM(void);
#define TRC_REG_DEMCR (*(volatile uint32_t*)0xE000EDFC)
#define TRC_REG_DWT_CTRL (*(volatile uint32_t*)0xE0001000)
#define TRC_REG_DWT_CYCCNT (*(volatile uint32_t*)0xE0001004)
#define TRC_REG_DWT_EXCCNT (*(volatile uint32_t*)0xE000100C)
#define TRC_REG_ITM_LOCKACCESS (*(volatile uint32_t*)0xE0001FB0)
#define TRC_ITM_LOCKACCESS_UNLOCK (0xC5ACCE55)
/* Bit mask for TRCENA bit in DEMCR - Global enable for DWT and ITM */
#define TRC_DEMCR_TRCENA (1 << 24)
/* Bit mask for NOPRFCNT bit in DWT_CTRL. If 1, DWT_EXCCNT is not supported */
#define TRC_DWT_CTRL_NOPRFCNT (1 << 24)
/* Bit mask for NOCYCCNT bit in DWT_CTRL. If 1, DWT_CYCCNT is not supported */
#define TRC_DWT_CTRL_NOCYCCNT (1 << 25)
/* Bit mask for EXCEVTENA_ bit in DWT_CTRL. Set to 1 to enable DWT_EXCCNT */
#define TRC_DWT_CTRL_EXCEVTENA (1 << 18)
/* Bit mask for EXCEVTENA_ bit in DWT_CTRL. Set to 1 to enable DWT_CYCCNT */
#define TRC_DWT_CTRL_CYCCNTENA (1)
#define TRC_PORT_SPECIFIC_INIT() prvTraceInitCortexM()
#define TRC_HWTC_TYPE TRC_FREE_RUNNING_32BIT_INCR
#define TRC_HWTC_COUNT TRC_REG_DWT_CYCCNT
#define TRC_HWTC_PERIOD 0
#define TRC_HWTC_DIVISOR 4
#define TRC_HWTC_FREQ_HZ TRACE_CPU_CLOCK_HZ
#define TRC_IRQ_PRIORITY_ORDER 0
#else
#define TRC_HWTC_TYPE TRC_OS_TIMER_DECR
#define TRC_HWTC_COUNT (*((volatile uint32_t*)0xE000E018))
#define TRC_HWTC_PERIOD ((*((volatile uint32_t*)0xE000E014)) + 1)
#define TRC_HWTC_DIVISOR 4
#define TRC_HWTC_FREQ_HZ TRACE_CPU_CLOCK_HZ
#define TRC_IRQ_PRIORITY_ORDER 0
#endif
#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_Renesas_RX600)
#include "iodefine.h"
#if (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_STREAMING)
#define TRC_HWTC_TYPE TRC_OS_TIMER_INCR
#define TRC_HWTC_COUNT (CMT0.CMCNT)
#elif (TRC_CFG_RECORDER_MODE == TRC_RECORDER_MODE_SNAPSHOT)
/* Decreasing counters better for Tickless Idle? */
#define TRC_HWTC_TYPE TRC_OS_TIMER_DECR
#define TRC_HWTC_COUNT (CMT0.CMCOR - CMT0.CMCNT)
#endif
#define TRC_HWTC_PERIOD (CMT0.CMCOR + 1)
#define TRC_HWTC_DIVISOR 1
#define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD)
#define TRC_IRQ_PRIORITY_ORDER 1
#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_MICROCHIP_PIC24_PIC32)
#define TRC_HWTC_TYPE TRC_OS_TIMER_INCR
#define TRC_HWTC_COUNT (TMR1)
#define TRC_HWTC_PERIOD (PR1 + 1)
#define TRC_HWTC_DIVISOR 1
#define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD)
#define TRC_IRQ_PRIORITY_ORDER 1
#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_TEXAS_INSTRUMENTS_TMS570_RM48)
#define TRC_RTIFRC0 *((uint32_t *)0xFFFFFC10)
#define TRC_RTICOMP0 *((uint32_t *)0xFFFFFC50)
#define TRC_RTIUDCP0 *((uint32_t *)0xFFFFFC54)
#define TRC_HWTC_TYPE TRC_OS_TIMER_INCR
#define TRC_HWTC_COUNT (TRC_RTIFRC0 - (TRC_RTICOMP0 - TRC_RTIUDCP0))
#define TRC_HWTC_PERIOD (TRC_RTIUDCP0)
#define TRC_HWTC_DIVISOR 1
#define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD)
#define TRC_IRQ_PRIORITY_ORDER 0
#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_Atmel_AT91SAM7)
/* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */
#define TRC_HWTC_TYPE TRC_OS_TIMER_INCR
#define TRC_HWTC_COUNT ((uint32_t)(AT91C_BASE_PITC->PITC_PIIR & 0xFFFFF))
#define TRC_HWTC_PERIOD ((uint32_t)(AT91C_BASE_PITC->PITC_PIMR + 1))
#define TRC_HWTC_DIVISOR 1
#define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD)
#define TRC_IRQ_PRIORITY_ORDER 1
#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_Atmel_UC3A0)
/* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO*/
/* For Atmel AVR32 (AT32UC3A) */
#define TRC_HWTC_TYPE TRC_OS_TIMER_INCR
#define TRC_HWTC_COUNT ((uint32_t)sysreg_read(AVR32_COUNT))
#define TRC_HWTC_PERIOD ((uint32_t)(sysreg_read(AVR32_COMPARE) + 1))
#define TRC_HWTC_DIVISOR 1
#define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD)
#define TRC_IRQ_PRIORITY_ORDER 1
#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_NXP_LPC210X)
/* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */
/* Tested with LPC2106, but should work with most LPC21XX chips. */
#define TRC_HWTC_TYPE TRC_OS_TIMER_INCR
#define TRC_HWTC_COUNT *((uint32_t *)0xE0004008 )
#define TRC_HWTC_PERIOD *((uint32_t *)0xE0004018 )
#define TRC_HWTC_DIVISOR 1
#define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD)
#define TRC_IRQ_PRIORITY_ORDER 0
#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_TEXAS_INSTRUMENTS_MSP430)
/* UNOFFICIAL PORT - NOT YET VERIFIED */
#define TRC_HWTC_TYPE TRC_OS_TIMER_INCR
#define TRC_HWTC_COUNT (TA0R)
#define TRC_HWTC_PERIOD (((uint16_t)TACCR0)+1)
#define TRC_HWTC_DIVISOR 1
#define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD)
#define TRC_IRQ_PRIORITY_ORDER 1
#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_XILINX_PPC405)
/* UNOFFICIAL PORT - NOT YET VERIFIED */
#define TRC_HWTC_TYPE TRC_OS_TIMER_DECR
#define TRC_HWTC_COUNT mfspr(0x3db)
#define TRC_HWTC_PERIOD (TRACE_CPU_CLOCK_HZ / TRACE_TICK_RATE_HZ)
#define TRC_HWTC_DIVISOR 1
#define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD)
#define TRC_IRQ_PRIORITY_ORDER 0
#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_XILINX_PPC440)
/* UNOFFICIAL PORT */
/* This should work with most PowerPC chips */
#define TRC_HWTC_TYPE TRC_OS_TIMER_DECR
#define TRC_HWTC_COUNT mfspr(0x016)
#define TRC_HWTC_PERIOD (TRACE_CPU_CLOCK_HZ / TRACE_TICK_RATE_HZ)
#define TRC_HWTC_DIVISOR 1
#define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD)
#define TRC_IRQ_PRIORITY_ORDER 0
#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_XILINX_MICROBLAZE)
/* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */
/* This should work with most Microblaze configurations.
* It uses the AXI Timer 0 - the tick interrupt source.
* If an AXI Timer 0 peripheral is available on your hardware platform, no modifications are required.
*/
#include "xtmrctr_l.h"
#define TRC_HWTC_TYPE TRC_OS_TIMER_DECR
#define TRC_HWTC_COUNT XTmrCtr_GetTimerCounterReg( XPAR_TMRCTR_0_BASEADDR, 0 )
#define TRC_HWTC_PERIOD (XTmrCtr_mGetLoadReg( XPAR_TMRCTR_0_BASEADDR, 0) + 1)
#define TRC_HWTC_DIVISOR 16
#define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD)
#define TRC_IRQ_PRIORITY_ORDER 0
#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_XILINX_ZyncUltraScaleR5)
#include "xttcps_hw.h"
#define TRC_HWTC_TYPE TRC_OS_TIMER_INCR
#define TRC_HWTC_COUNT (*(volatile uint32_t *)(configTIMER_BASEADDR + XTTCPS_COUNT_VALUE_OFFSET))
#define TRC_HWTC_PERIOD (*(volatile uint32_t *)(configTIMER_BASEADDR + XTTCPS_INTERVAL_VAL_OFFSET))
#define TRC_HWTC_DIVISOR 16
#define TRC_HWTC_FREQ_HZ (TRC_HWTC_PERIOD * TRACE_TICK_RATE_HZ)
#define TRC_IRQ_PRIORITY_ORDER 0
#ifdef __GNUC__
/* For Arm Cortex-A and Cortex-R in general. */
static inline uint32_t prvGetCPSR(void)
{
unsigned long ret;
/* GCC-style assembly for getting the CPSR/APSR register, where the system execution mode is found. */
asm volatile (" mrs %0, cpsr" : "=r" (ret) : /* no inputs */ );
return ret;
}
#else
#error "Only GCC Supported!"
#endif
#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_Altera_NiosII)
/* OFFICIAL PORT */
#include <system.h>
#include <altera_avalon_timer_regs.h>
#define NOT_SET 1
/* The base address for the sustem timer set.
* The name user for the system timer can be found in the BSP editor.
* If the name of the timer is sys_tmr SYSTEM_TIMER_BASE should be set to SYS_TMR_BASE.
*/
#define SYSTEM_TIMER_BASE NOT_SET
#if (SYSTEM_TIMER == NOT_SET)
#error "Set SYSTEM_TIMER_BASE to the timer base used for system ticks."
#endif
static inline uint32_t altera_nios2_GetTimerSnapReg(void)
{
/* A processor can read the current counter value by first writing to either snapl or snaph to request a coherent snapshot of the counter,
* and then reading snapl and snaph for the full 32-bit value.
*/
IOWR_ALTERA_AVALON_TIMER_SNAPL(SYSTEM_TIMER_BASE, 0);
return (IORD_ALTERA_AVALON_TIMER_SNAPH(SYSTEM_TIMER_BASE) << 16) | IORD_ALTERA_AVALON_TIMER_SNAPL(SYSTEM_TIMER_BASE);
}
#define TRC_HWTC_TYPE TRC_OS_TIMER_DECR
#define TRC_HWTC_COUNT altera_nios2_GetTimerSnapReg()
#define TRC_HWTC_PERIOD (configCPU_CLOCK_HZ / configTICK_RATE_HZ )
#define TRC_HWTC_DIVISOR 16
#define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD)
#define TRC_IRQ_PRIORITY_ORDER 0
#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_ARM_CORTEX_A9)
/**************************************************************************
* This hardware port only supports FreeRTOS and the GCC compiler at the
* moment, due to the implementation of critical sections (trcKernelPort.h).
*
* Assuming FreeRTOS is used:
*
* For critical sections, this uses vTaskEnterCritical is when called from
* task context and ulPortSetInterruptMask when called from ISR context.
* Thus, it does not disable all ISRs. This means that the trace recorder
* can only be called from ISRs with priority less or equal to
* configMAX_API_CALL_INTERRUPT_PRIORITY (like FreeRTOS fromISR functions).
*
* This hardware port has been tested on it a Xilinx Zync 7000 (Cortex-A9),
* but should work with all Cortex-A and R processors assuming that
* TRC_CA9_MPCORE_PERIPHERAL_BASE_ADDRESS is set accordingly.
**************************************************************************/
/* INPUT YOUR PERIPHERAL BASE ADDRESS HERE (0xF8F00000 for Xilinx Zynq 7000)*/
#define TRC_CA9_MPCORE_PERIPHERAL_BASE_ADDRESS 0
#if (TRC_CA9_MPCORE_PERIPHERAL_BASE_ADDRESS == 0)
#error "Please specify TRC_CA9_MPCORE_PERIPHERAL_BASE_ADDRESS."
#endif
#define TRC_CA9_MPCORE_PRIVATE_MEMORY_OFFSET 0x0600
#define TRC_CA9_MPCORE_PRIVCTR_PERIOD_REG (*(volatile uint32_t*)(TRC_CA9_MPCORE_PERIPHERAL_BASE_ADDRESS + TRC_CA9_MPCORE_PRIVATE_MEMORY_OFFSET + 0x00))
#define TRC_CA9_MPCORE_PRIVCTR_COUNTER_REG (*(volatile uint32_t*)(TRC_CA9_MPCORE_PERIPHERAL_BASE_ADDRESS + TRC_CA9_MPCORE_PRIVATE_MEMORY_OFFSET + 0x04))
#define TRC_CA9_MPCORE_PRIVCTR_CONTROL_REG (*(volatile uint32_t*)(TRC_CA9_MPCORE_PERIPHERAL_BASE_ADDRESS + TRC_CA9_MPCORE_PRIVATE_MEMORY_OFFSET + 0x08))
#define TRC_CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_MASK 0x0000FF00
#define TRC_CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_SHIFT 8
#define TRC_CA9_MPCORE_PRIVCTR_PRESCALER (((TRC_CA9_MPCORE_PRIVCTR_CONTROL_REG & TRC_CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_MASK) >> TRC_CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_SHIFT) + 1)
#define TRC_HWTC_TYPE TRC_OS_TIMER_DECR
#define TRC_HWTC_COUNT TRC_CA9_MPCORE_PRIVCTR_COUNTER_REG
#define TRC_HWTC_PERIOD (TRC_CA9_MPCORE_PRIVCTR_PERIOD_REG + 1)
/****************************************************************************************
NOTE: The private timer ticks with a very high frequency (half the core-clock usually),
depending on the prescaler used. If a low prescaler is used, the number of HW ticks between
the trace events gets large, and thereby inefficient to store (sometimes extra events are
needed). To improve efficiency, you may use the TRC_HWTC_DIVISOR as an additional prescaler.
*****************************************************************************************/
#define TRC_HWTC_DIVISOR 1
#define TRC_HWTC_FREQ_HZ (TRACE_TICK_RATE_HZ * TRC_HWTC_PERIOD)
#define TRC_IRQ_PRIORITY_ORDER 0
#ifdef __GNUC__
/* For Arm Cortex-A and Cortex-R in general. */
static inline uint32_t prvGetCPSR(void)
{
unsigned long ret;
/* GCC-style assembly for getting the CPSR/APSR register, where the system execution mode is found. */
asm volatile (" mrs %0, cpsr" : "=r" (ret) : /* no inputs */ );
return ret;
}
#else
#error "Only GCC Supported!"
#endif
#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_POWERPC_Z4)
/* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */
#define TRC_HWTC_TYPE TRC_OS_TIMER_DECR
//#define HWTC_COUNT_DIRECTION DIRECTION_DECREMENTING
#define TRC_HWTC_COUNT PIT.TIMER[configTICK_PIT_CHANNEL].CVAL.R // must be the PIT channel used for the systick
#define TRC_HWTC_PERIOD ((configPIT_CLOCK_HZ / configTICK_RATE_HZ) - 1U) // TODO FIXME or maybe not -1? what's the right "period" value?
#define TRC_HWTC_FREQ_HZ configPIT_CLOCK_HZ
#define TRC_HWTC_DIVISOR 1
#define TRC_IRQ_PRIORITY_ORDER 1 // higher IRQ priority values are more significant
#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_APPLICATION_DEFINED)
#if !( defined (TRC_HWTC_TYPE) && defined (TRC_HWTC_COUNT) && defined (TRC_HWTC_PERIOD) && defined (TRC_HWTC_FREQ_HZ) && defined (TRC_IRQ_PRIORITY_ORDER) )
#error "The hardware port is not completely defined!"
#endif
#elif (TRC_CFG_HARDWARE_PORT == TRC_HARDWARE_PORT_PROCESSOR_EXPERT) /* << EST */
#include "portTicks.h" /* << EST */
#elif (TRC_CFG_HARDWARE_PORT != TRC_HARDWARE_PORT_NOT_SET)
#error "TRC_CFG_HARDWARE_PORT had unsupported value!"
#define TRC_CFG_HARDWARE_PORT TRC_HARDWARE_PORT_NOT_SET
#endif
#ifndef TRC_HWTC_DIVISOR
#define TRC_HWTC_DIVISOR 1
#endif
#ifndef TRC_PORT_SPECIFIC_INIT
#define TRC_PORT_SPECIFIC_INIT()
#endif
/* If Win32 port */
#ifdef WIN32
#undef _WIN32_WINNT
#define _WIN32_WINNT 0x0600
/* Standard includes. */
#include <stdio.h>
#include <windows.h>
#include <direct.h>
/***************************************************************************
* The Win32 port by default saves the trace to file and then kills the
* program when the recorder is stopped, to facilitate quick, simple tests
* of the recorder.
***************************************************************************/
#define WIN32_PORT_SAVE_WHEN_STOPPED 1
#define WIN32_PORT_EXIT_WHEN_STOPPED 1
#endif
#if (TRC_CFG_HARDWARE_PORT != TRC_HARDWARE_PORT_NOT_SET)
#ifndef TRC_HWTC_TYPE
#error "TRC_HWTC_TYPE is not set!"
#endif
#ifndef TRC_HWTC_COUNT
#error "TRC_HWTC_COUNT is not set!"
#endif
#ifndef TRC_HWTC_PERIOD
#error "TRC_HWTC_PERIOD is not set!"
#endif
#ifndef TRC_HWTC_DIVISOR
#error "TRC_HWTC_DIVISOR is not set!"
#endif
#ifndef TRC_IRQ_PRIORITY_ORDER
#error "TRC_IRQ_PRIORITY_ORDER is not set!"
#elif (TRC_IRQ_PRIORITY_ORDER != 0) && (TRC_IRQ_PRIORITY_ORDER != 1)
#error "TRC_IRQ_PRIORITY_ORDER has bad value!"
#endif
#if (TRC_HWTC_DIVISOR < 1)
#error "TRC_HWTC_DIVISOR must be a non-zero positive value!"
#endif
#ifndef TRC_HWTC_FREQ_HZ
#error "TRC_HWTC_FREQ_HZ not defined!"
#endif
#endif
#endif /*TRC_SNAPSHOT_HARDWARE_PORT_H*/

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/*******************************************************************************
* Trace Recorder Library for Tracealyzer v4.4.1
* Percepio AB, www.percepio.com
*
* trcPortDefines.h
*
* Some common defines for the trace recorder.
*
* Terms of Use
* This file is part of the trace recorder library (RECORDER), which is the
* intellectual property of Percepio AB (PERCEPIO) and provided under a
* license as follows.
* The RECORDER may be used free of charge for the purpose of recording data
* intended for analysis in PERCEPIO products. It may not be used or modified
* for other purposes without explicit permission from PERCEPIO.
* You may distribute the RECORDER in its original source code form, assuming
* this text (terms of use, disclaimer, copyright notice) is unchanged. You are
* allowed to distribute the RECORDER with minor modifications intended for
* configuration or porting of the RECORDER, e.g., to allow using it on a
* specific processor, processor family or with a specific communication
* interface. Any such modifications should be documented directly below
* this comment block.
*
* Disclaimer
* The RECORDER is being delivered to you AS IS and PERCEPIO makes no warranty
* as to its use or performance. PERCEPIO does not and cannot warrant the
* performance or results you may obtain by using the RECORDER or documentation.
* PERCEPIO make no warranties, express or implied, as to noninfringement of
* third party rights, merchantability, or fitness for any particular purpose.
* In no event will PERCEPIO, its technology partners, or distributors be liable
* to you for any consequential, incidental or special damages, including any
* lost profits or lost savings, even if a representative of PERCEPIO has been
* advised of the possibility of such damages, or for any claim by any third
* party. Some jurisdictions do not allow the exclusion or limitation of
* incidental, consequential or special damages, or the exclusion of implied
* warranties or limitations on how long an implied warranty may last, so the
* above limitations may not apply to you.
*
* Tabs are used for indent in this file (1 tab = 4 spaces)
*
* Copyright Percepio AB, 2018.
* www.percepio.com
******************************************************************************/
#ifndef TRC_PORTDEFINES_H
#define TRC_PORTDEFINES_H
#define TRC_FREE_RUNNING_32BIT_INCR 1
#define TRC_FREE_RUNNING_32BIT_DECR 2
#define TRC_OS_TIMER_INCR 3
#define TRC_OS_TIMER_DECR 4
#define TRC_CUSTOM_TIMER_INCR 5
#define TRC_CUSTOM_TIMER_DECR 6
/* Start options for vTraceEnable. */
#define TRC_INIT 0
#define TRC_START 1
#define TRC_START_AWAIT_HOST 2
/* Command codes for TzCtrl task */
#define CMD_SET_ACTIVE 1 /* Start (param1 = 1) or Stop (param1 = 0) */
/* The final command code, used to validate commands. */
#define CMD_LAST_COMMAND 1
#define TRC_RECORDER_MODE_SNAPSHOT 0
#define TRC_RECORDER_MODE_STREAMING 1
#define TRC_RECORDER_BUFFER_ALLOCATION_STATIC (0x00)
#define TRC_RECORDER_BUFFER_ALLOCATION_DYNAMIC (0x01)
#define TRC_RECORDER_BUFFER_ALLOCATION_CUSTOM (0x02)
/* Filter Groups */
#define FilterGroup0 (uint16_t)0x0001
#define FilterGroup1 (uint16_t)0x0002
#define FilterGroup2 (uint16_t)0x0004
#define FilterGroup3 (uint16_t)0x0008
#define FilterGroup4 (uint16_t)0x0010
#define FilterGroup5 (uint16_t)0x0020
#define FilterGroup6 (uint16_t)0x0040
#define FilterGroup7 (uint16_t)0x0080
#define FilterGroup8 (uint16_t)0x0100
#define FilterGroup9 (uint16_t)0x0200
#define FilterGroup10 (uint16_t)0x0400
#define FilterGroup11 (uint16_t)0x0800
#define FilterGroup12 (uint16_t)0x1000
#define FilterGroup13 (uint16_t)0x2000
#define FilterGroup14 (uint16_t)0x4000
#define FilterGroup15 (uint16_t)0x8000
/******************************************************************************
* Supported ports
*
* TRC_HARDWARE_PORT_HWIndependent
* A hardware independent fallback option for event timestamping. Provides low
* resolution timestamps based on the OS tick.
* This may be used on the Win32 port, but may also be used on embedded hardware
* platforms. All time durations will be truncated to the OS tick frequency,
* typically 1 KHz. This means that a task or ISR that executes in less than
* 1 ms get an execution time of zero.
*
* TRC_HARDWARE_PORT_APPLICATION_DEFINED
* Allows for defining the port macros in other source code files.
*
* TRC_HARDWARE_PORT_Win32
* "Accurate" timestamping based on the Windows performance counter for Win32
* builds. Note that this gives the host machine time, not the kernel time.
*
* Hardware specific ports
* To get accurate timestamping, a hardware timer is necessary. Below are the
* available ports. Some of these are "unofficial", meaning that
* they have not yet been verified by Percepio but have been contributed by
* external developers. They should work, otherwise let us know by emailing
* support@percepio.com. Some work on any OS platform, while other are specific
* to a certain operating system.
*****************************************************************************/
/****** Port Name ************************************* Code ** Official ** OS Platform *********/
#define TRC_HARDWARE_PORT_APPLICATION_DEFINED 98 /* - - */
#define TRC_HARDWARE_PORT_NOT_SET 99 /* - - */
#define TRC_HARDWARE_PORT_HWIndependent 0 /* Yes Any */
#define TRC_HARDWARE_PORT_Win32 1 /* Yes FreeRTOS on Win32 */
#define TRC_HARDWARE_PORT_Atmel_AT91SAM7 2 /* No Any */
#define TRC_HARDWARE_PORT_Atmel_UC3A0 3 /* No Any */
#define TRC_HARDWARE_PORT_ARM_Cortex_M 4 /* Yes Any */
#define TRC_HARDWARE_PORT_Renesas_RX600 6 /* Yes Any */
#define TRC_HARDWARE_PORT_MICROCHIP_PIC24_PIC32 7 /* Yes Any */
#define TRC_HARDWARE_PORT_TEXAS_INSTRUMENTS_TMS570_RM48 8 /* Yes Any */
#define TRC_HARDWARE_PORT_TEXAS_INSTRUMENTS_MSP430 9 /* No Any */
#define TRC_HARDWARE_PORT_XILINX_PPC405 11 /* No FreeRTOS */
#define TRC_HARDWARE_PORT_XILINX_PPC440 12 /* No FreeRTOS */
#define TRC_HARDWARE_PORT_XILINX_MICROBLAZE 13 /* No Any */
#define TRC_HARDWARE_PORT_XILINX_ZyncUltraScaleR5 14 /* No FreeRTOS */
#define TRC_HARDWARE_PORT_NXP_LPC210X 15 /* No Any */
#define TRC_HARDWARE_PORT_ARM_CORTEX_A9 16 /* Yes Any */
#define TRC_HARDWARE_PORT_POWERPC_Z4 17 /* No FreeRTOS */
#define TRC_HARDWARE_PORT_Altera_NiosII 18 /* Yes Any (Tested with FreeRTOS) */
#define TRC_HARDWARE_PORT_PROCESSOR_EXPERT 95 /* No FreeRTOS */ /* << EST */
#endif /*TRC_PORTDEFINES_H*/

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