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This commit is contained in:
Rémi Heredero
2024-04-17 14:20:36 +02:00
parent 8a64f5c04b
commit 1b569b2b42
23 changed files with 7609 additions and 222 deletions
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15
06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbgpio_tb_entity.vhg Normal file
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-- VHDL Entity AhbLiteComponents_test.ahbGpio_tb.symbol
--
-- Created:
-- by - axel.amand.UNKNOWN (WE7860)
-- at - 14:51:39 28.04.2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
ENTITY ahbGpio_tb IS
-- Declarations
END ahbGpio_tb ;

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06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbgpio_tb_struct.vhg Normal file
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--
-- VHDL Architecture AhbLiteComponents_test.ahbGpio_tb.struct
--
-- Created:
-- by - axel.amand.UNKNOWN (WE7860)
-- at - 15:06:49 28.04.2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY AhbLite;
USE AhbLite.ahbLite.all;
LIBRARY AhbLiteComponents;
LIBRARY AhbLiteComponents_test;
ARCHITECTURE struct OF ahbGpio_tb IS
-- Architecture declarations
constant ioNb: positive := 8;
constant clockFrequency : real := 60.0E6;
--constant clockFrequency : real := 66.0E6;
-- Internal signal declarations
SIGNAL hAddr : unsigned( ahbAddressBitNb-1 DOWNTO 0 );
SIGNAL hClk : std_uLogic;
SIGNAL hRData : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0);
SIGNAL hReady : std_uLogic;
SIGNAL hReset_n : std_uLogic;
SIGNAL hResp : std_uLogic;
SIGNAL hSel : std_uLogic;
SIGNAL hTrans : std_ulogic_vector(ahbTransBitNb-1 DOWNTO 0);
SIGNAL hWData : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0);
SIGNAL hWrite : std_uLogic;
SIGNAL io : std_logic_vector(ioNb-1 DOWNTO 0);
SIGNAL ioEn : std_ulogic_vector(ioNb-1 DOWNTO 0);
SIGNAL ioIn : std_ulogic_vector(ioNb-1 DOWNTO 0);
SIGNAL ioOut : std_ulogic_vector(ioNb-1 DOWNTO 0);
-- Component Declarations
COMPONENT ahbGpio
GENERIC (
ioNb : positive := 8
);
PORT (
hAddr : IN unsigned ( ahbAddressBitNb-1 DOWNTO 0 );
hClk : IN std_uLogic ;
hReset_n : IN std_uLogic ;
hSel : IN std_uLogic ;
hTrans : IN std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0);
hWData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
hWrite : IN std_uLogic ;
ioIn : IN std_ulogic_vector (ioNb-1 DOWNTO 0);
hRData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
hReady : OUT std_uLogic ;
hResp : OUT std_uLogic ;
ioEn : OUT std_ulogic_vector (ioNb-1 DOWNTO 0);
ioOut : OUT std_ulogic_vector (ioNb-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT ahbGpio_tester
GENERIC (
ioNb : positive;
clockFrequency : real
);
PORT (
hRData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
hReady : IN std_uLogic ;
hResp : IN std_uLogic ;
hAddr : OUT unsigned ( ahbAddressBitNb-1 DOWNTO 0 );
hClk : OUT std_uLogic ;
hReset_n : OUT std_uLogic ;
hSel : OUT std_uLogic ;
hTrans : OUT std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0);
hWData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
hWrite : OUT std_uLogic ;
io : INOUT std_logic_vector (ioNb-1 DOWNTO 0)
);
END COMPONENT;
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : ahbGpio USE ENTITY AhbLiteComponents.ahbGpio;
FOR ALL : ahbGpio_tester USE ENTITY AhbLiteComponents_test.ahbGpio_tester;
-- pragma synthesis_on
BEGIN
-- Architecture concurrent statements
-- HDL Embedded Text Block 1 eb1
tristate: process(ioEn, ioOut)
begin
for index in io'range loop
if ioEn(index) = '1' then
io(index) <= ioOut(index);
else
io(index) <= 'Z';
end if;
end loop;
end process tristate;
ioIn <= std_ulogic_vector(io);
-- Instance port mappings.
I_DUT : ahbGpio
GENERIC MAP (
ioNb => ioNb
)
PORT MAP (
hAddr => hAddr,
hClk => hClk,
hReset_n => hReset_n,
hSel => hSel,
hTrans => hTrans,
hWData => hWData,
hWrite => hWrite,
ioIn => ioIn,
hRData => hRData,
hReady => hReady,
hResp => hResp,
ioEn => ioEn,
ioOut => ioOut
);
I_tester : ahbGpio_tester
GENERIC MAP (
ioNb => ioNb,
clockFrequency => clockFrequency
)
PORT MAP (
hRData => hRData,
hReady => hReady,
hResp => hResp,
hAddr => hAddr,
hClk => hClk,
hReset_n => hReset_n,
hSel => hSel,
hTrans => hTrans,
hWData => hWData,
hWrite => hWrite,
io => io
);
END struct;

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06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbgpio_tester_entity.vhg Normal file
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-- VHDL Entity AhbLiteComponents_test.ahbGpio_tester.interface
--
-- Created:
-- by - axel.amand.UNKNOWN (WE7860)
-- at - 14:51:40 28.04.2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY AhbLite;
USE AhbLite.ahbLite.all;
ENTITY ahbGpio_tester IS
GENERIC(
ioNb : positive;
clockFrequency : real
);
PORT(
hRData : IN std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
hReady : IN std_uLogic;
hResp : IN std_uLogic;
hAddr : OUT unsigned ( ahbAddressBitNb-1 DOWNTO 0 );
hClk : OUT std_uLogic;
hReset_n : OUT std_uLogic;
hSel : OUT std_uLogic;
hTrans : OUT std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0);
hWData : OUT std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
hWrite : OUT std_uLogic;
io : INOUT std_logic_vector (ioNb-1 DOWNTO 0)
);
-- Declarations
END ahbGpio_tester ;