some file i don't know if needed

06-07-08-09-SystemOnChip/AhbLiteComponents/hdl/ahbuart_entity.vhg

@@ -0,0 +1,38 @@
+-- VHDL Entity AhbLiteComponents.ahbUart.symbol
+--
+-- Created:
+--          by - remi.heredero.UNKNOWN (WE2330808)
+--          at - 15:08:33 23.02.2024
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.all;
+LIBRARY AhbLite;
+  USE AhbLite.ahbLite.all;
+
+ENTITY ahbUart IS
+    GENERIC( 
+        txFifoDepth : positive := 8;
+        rxFifoDepth : positive := 1
+    );
+    PORT( 
+        RxD      : IN     std_ulogic;
+        hAddr    : IN     unsigned ( ahbAddressBitNb-1 DOWNTO 0 );
+        hClk     : IN     std_uLogic;
+        hReset_n : IN     std_uLogic;
+        hSel     : IN     std_uLogic;
+        hTrans   : IN     std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0);
+        hWData   : IN     std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
+        hWrite   : IN     std_uLogic;
+        TxD      : OUT    std_ulogic;
+        hRData   : OUT    std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
+        hReady   : OUT    std_uLogic;
+        hResp    : OUT    std_uLogic
+    );
+
+-- Declarations
+
+END ahbUart ;
+

06-07-08-09-SystemOnChip/AhbLiteComponents/hds/.xrf/ahbuart_entity.xrf

@@ -0,0 +1,51 @@
+DESIGN ahb@uart
+VIEW symbol.sb
+NO_GRAPHIC 0
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 104,0 8 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 13,0 15 1 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2839,0 20 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2452,0 21 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2514,0 22 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2519,0 23 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2692,0 24 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2494,0 25 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2464,0 26 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2474,0 27 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2651,0 28 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2469,0 29 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2504,0 30 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2509,0 31 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 1,0 34 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 1,0 35 0 

06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbuart_tb_entity.vhg

@@ -0,0 +1,15 @@
+-- VHDL Entity AhbLiteComponents_test.ahbUart_tb.symbol
+--
+-- Created:
+--          by - zas.UNKNOWN (ZELL)
+--          at - 17:08:42 02/17/2020
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+
+
+ENTITY ahbUart_tb IS
+-- Declarations
+
+END ahbUart_tb ;
+

06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbuart_tb_struct.vhg

@@ -0,0 +1,132 @@
+--
+-- VHDL Architecture AhbLiteComponents_test.ahbUart_tb.struct
+--
+-- Created:
+--          by - axel.amand.UNKNOWN (WE7860)
+--          at - 15:07:00 28.04.2023
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.all;
+LIBRARY AhbLite;
+  USE AhbLite.ahbLite.all;
+
+LIBRARY AhbLiteComponents;
+LIBRARY AhbLiteComponents_test;
+
+ARCHITECTURE struct OF ahbUart_tb IS
+
+    -- Architecture declarations
+    constant txFifoDepth: positive := 1;
+    constant rxFifoDepth: positive := 1;
+    
+    constant clockFrequency : real := 60.0E6;
+    --constant clockFrequency : real := 66.0E6;
+
+    -- Internal signal declarations
+    SIGNAL RxD      : std_ulogic;
+    SIGNAL TxD      : std_ulogic;
+    SIGNAL hAddr    : unsigned( ahbAddressBitNb-1 DOWNTO 0 );
+    SIGNAL hClk     : std_uLogic;
+    SIGNAL hRData   : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0);
+    SIGNAL hReady   : std_uLogic;
+    SIGNAL hReset_n : std_uLogic;
+    SIGNAL hResp    : std_uLogic;
+    SIGNAL hSel     : std_uLogic;
+    SIGNAL hTrans   : std_ulogic_vector(ahbTransBitNb-1 DOWNTO 0);
+    SIGNAL hWData   : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0);
+    SIGNAL hWrite   : std_uLogic;
+
+
+    -- Component Declarations
+    COMPONENT ahbUart
+    GENERIC (
+        txFifoDepth : positive := 8;
+        rxFifoDepth : positive := 1
+    );
+    PORT (
+        RxD      : IN     std_ulogic ;
+        hAddr    : IN     unsigned ( ahbAddressBitNb-1 DOWNTO 0 );
+        hClk     : IN     std_uLogic ;
+        hReset_n : IN     std_uLogic ;
+        hSel     : IN     std_uLogic ;
+        hTrans   : IN     std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0);
+        hWData   : IN     std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
+        hWrite   : IN     std_uLogic ;
+        TxD      : OUT    std_ulogic ;
+        hRData   : OUT    std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
+        hReady   : OUT    std_uLogic ;
+        hResp    : OUT    std_uLogic 
+    );
+    END COMPONENT;
+    COMPONENT ahbUart_tester
+    GENERIC (
+        clockFrequency : real
+    );
+    PORT (
+        TxD      : IN     std_ulogic ;
+        hRData   : IN     std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
+        hReady   : IN     std_uLogic ;
+        hResp    : IN     std_uLogic ;
+        RxD      : OUT    std_ulogic ;
+        hAddr    : OUT    unsigned ( ahbAddressBitNb-1 DOWNTO 0 );
+        hClk     : OUT    std_uLogic ;
+        hReset_n : OUT    std_uLogic ;
+        hSel     : OUT    std_uLogic ;
+        hTrans   : OUT    std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0);
+        hWData   : OUT    std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
+        hWrite   : OUT    std_uLogic 
+    );
+    END COMPONENT;
+
+    -- Optional embedded configurations
+    -- pragma synthesis_off
+    FOR ALL : ahbUart USE ENTITY AhbLiteComponents.ahbUart;
+    FOR ALL : ahbUart_tester USE ENTITY AhbLiteComponents_test.ahbUart_tester;
+    -- pragma synthesis_on
+
+
+BEGIN
+
+    -- Instance port mappings.
+    I_DUT : ahbUart
+        GENERIC MAP (
+            txFifoDepth => txFifoDepth,
+            rxFifoDepth => rxFifoDepth
+        )
+        PORT MAP (
+            RxD      => RxD,
+            hAddr    => hAddr,
+            hClk     => hClk,
+            hReset_n => hReset_n,
+            hSel     => hSel,
+            hTrans   => hTrans,
+            hWData   => hWData,
+            hWrite   => hWrite,
+            TxD      => TxD,
+            hRData   => hRData,
+            hReady   => hReady,
+            hResp    => hResp
+        );
+    I_tester : ahbUart_tester
+        GENERIC MAP (
+            clockFrequency => clockFrequency
+        )
+        PORT MAP (
+            TxD      => TxD,
+            hRData   => hRData,
+            hReady   => hReady,
+            hResp    => hResp,
+            RxD      => RxD,
+            hAddr    => hAddr,
+            hClk     => hClk,
+            hReset_n => hReset_n,
+            hSel     => hSel,
+            hTrans   => hTrans,
+            hWData   => hWData,
+            hWrite   => hWrite
+        );
+
+END struct;

06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbuart_tester_entity.vhg

@@ -0,0 +1,37 @@
+-- VHDL Entity AhbLiteComponents_test.ahbUart_tester.interface
+--
+-- Created:
+--          by - zas.UNKNOWN (ZELL)
+--          at - 17:08:42 02/17/2020
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.all;
+LIBRARY AhbLite;
+  USE AhbLite.ahbLite.all;
+
+ENTITY ahbUart_tester IS
+    GENERIC( 
+        clockFrequency : real
+    );
+    PORT( 
+        TxD      : IN     std_ulogic;
+        hRData   : IN     std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
+        hReady   : IN     std_uLogic;
+        hResp    : IN     std_uLogic;
+        RxD      : OUT    std_ulogic;
+        hAddr    : OUT    unsigned ( ahbAddressBitNb-1 DOWNTO 0 );
+        hClk     : OUT    std_uLogic;
+        hReset_n : OUT    std_uLogic;
+        hSel     : OUT    std_uLogic;
+        hTrans   : OUT    std_ulogic_vector (ahbTransBitNb-1 DOWNTO 0);
+        hWData   : OUT    std_ulogic_vector (ahbDataBitNb-1 DOWNTO 0);
+        hWrite   : OUT    std_uLogic
+    );
+
+-- Declarations
+
+END ahbUart_tester ;
+

06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.xrf/ahbuart_tb_entity.xrf

@@ -0,0 +1,12 @@
+DESIGN ahb@uart_tb
+VIEW symbol.sb
+NO_GRAPHIC 0
+DESIGN ahb@uart_tb
+VIEW symbol.sb
+GRAPHIC 53,0 8 0 
+DESIGN ahb@uart_tb
+VIEW symbol.sb
+GRAPHIC 1,0 11 0 
+DESIGN ahb@uart_tb
+VIEW symbol.sb
+GRAPHIC 1,0 12 0 

06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.xrf/ahbuart_tb_struct.xrf

@@ -0,0 +1,213 @@
+DESIGN ahb@uart_tb
+VIEW struct.bd
+NO_GRAPHIC 0
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 187,0 9 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+NO_GRAPHIC 14
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 0,0 18 2 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 1,0 21 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+NO_GRAPHIC 21
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 13297,0 28 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 13305,0 29 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12627,0 30 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12563,0 31 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12587,0 32 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12579,0 33 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12555,0 34 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12571,0 35 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12595,0 36 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12611,0 37 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12619,0 38 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12603,0 39 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+NO_GRAPHIC 40
+DESIGN ahb@uart_tb
+VIEW struct.bd
+NO_GRAPHIC 41
+LIBRARY AhbLiteComponents
+DESIGN ahb@uart
+VIEW student@version
+GRAPHIC 13707,0 43 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 14,0 44 1 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2839,0 49 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2452,0 50 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2514,0 51 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2519,0 52 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2692,0 53 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2494,0 54 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2464,0 55 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2474,0 56 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2651,0 57 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2469,0 58 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2504,0 59 0 
+DESIGN ahb@uart
+VIEW symbol.sb
+GRAPHIC 2509,0 60 0 
+LIBRARY AhbLiteComponents_test
+DESIGN ahb@uart_tester
+VIEW test
+GRAPHIC 12657,0 63 0 
+DESIGN ahb@uart_tester
+VIEW interface
+GRAPHIC 14,0 64 1 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 13307,0 68 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12589,0 69 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12581,0 70 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12573,0 71 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 13299,0 72 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12629,0 73 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12565,0 74 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12557,0 75 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12597,0 76 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12613,0 77 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12621,0 78 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12605,0 79 0 
+LIBRARY AhbLiteComponents_test
+DESIGN ahb@uart_tb
+VIEW struct.bd
+NO_GRAPHIC 82
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 13707,0 85 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12657,0 86 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+NO_GRAPHIC 89
+DESIGN ahb@uart_tb
+VIEW struct.bd
+NO_GRAPHIC 91
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 13707,0 93 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 13714,0 94 1 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 13299,0 99 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12629,0 100 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12565,0 101 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12557,0 102 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12597,0 103 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12613,0 104 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12621,0 105 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12605,0 106 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 13307,0 107 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12589,0 108 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12581,0 109 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12573,0 110 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12657,0 112 0 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+GRAPHIC 12664,0 113 1 
+DESIGN ahb@uart_tb
+VIEW struct.bd
+NO_GRAPHIC 131

06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.xrf/ahbuart_tester_entity.xrf

@@ -0,0 +1,51 @@
+DESIGN ahb@uart_tester
+VIEW interface
+NO_GRAPHIC 0
+DESIGN ahb@uart_tester
+VIEW interface
+GRAPHIC 50,0 8 0 
+DESIGN ahb@uart_tester
+VIEW interface
+GRAPHIC 13,0 15 1 
+DESIGN ahb@uart_tester
+VIEW interface
+GRAPHIC 1269,0 19 0 
+DESIGN ahb@uart_tester
+VIEW interface
+GRAPHIC 1224,0 20 0 
+DESIGN ahb@uart_tester
+VIEW interface
+GRAPHIC 1229,0 21 0 
+DESIGN ahb@uart_tester
+VIEW interface
+GRAPHIC 1239,0 22 0 
+DESIGN ahb@uart_tester
+VIEW interface
+GRAPHIC 1264,0 23 0 
+DESIGN ahb@uart_tester
+VIEW interface
+GRAPHIC 1214,0 24 0 
+DESIGN ahb@uart_tester
+VIEW interface
+GRAPHIC 1219,0 25 0 
+DESIGN ahb@uart_tester
+VIEW interface
+GRAPHIC 1234,0 26 0 
+DESIGN ahb@uart_tester
+VIEW interface
+GRAPHIC 1244,0 27 0 
+DESIGN ahb@uart_tester
+VIEW interface
+GRAPHIC 1249,0 28 0 
+DESIGN ahb@uart_tester
+VIEW interface
+GRAPHIC 1254,0 29 0 
+DESIGN ahb@uart_tester
+VIEW interface
+GRAPHIC 1259,0 30 0 
+DESIGN ahb@uart_tester
+VIEW interface
+GRAPHIC 1,0 33 0 
+DESIGN ahb@uart_tester
+VIEW interface
+GRAPHIC 1,0 34 0 

06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/hds_user_prefs.bak

@@ -4149,7 +4149,7 @@ hdsWorkspaceLocation ""
 relativeLibraryRootDir ""
 vmLabelLatestDontAskAgain 0
 vmLabelWorkspaceDontAskAgain 0
-logWindowGeometry "636x406+308+98"
+logWindowGeometry "636x514+308+98"
 diagramBrowserTabNo 0
 showInsertPortHint 0
 showContentFirstTime 0
@@ -6336,6 +6336,7 @@ yPos 9
 width 974
 height 1047
 activeSidePanelTab 2
+activeLibraryTab 5
 sidePanelSize 278
 showUnixHiddenFiles 0
 componentBrowserXpos 569

06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk

@@ -46,7 +46,7 @@ settingsMap [
 "GlitchGeneration"
 "1"
 "InitCmd"
-"C:/Users/remi.heredero/GIT/2024-sem-labs-herederoremi/06-07-08-09-SystemOnChip/Simulation/ahbGpio.do"
+"C:/Users/remi.heredero/GIT/2024-sem-labs-herederoremi/06-07-08-09-SystemOnChip/Simulation/ahbUart.do"
 "LogFile"
 ""
 "RemoteHost"