add resize + tabel
This commit is contained in:
@@ -0,0 +1,55 @@
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6699
02-SplineInterpolator/Prefs/hds_user/v2019.2/hds_user_prefs.bak
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6699
02-SplineInterpolator/Prefs/hds_user/v2019.2/hds_user_prefs.bak
Normal file
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,34 @@
|
||||
-- VHDL Entity SplineInterpolator.interpolatorCalculatePolynom.symbol
|
||||
--
|
||||
-- Created:
|
||||
-- by - francois.francois (Aphelia)
|
||||
-- at - 13:00:14 02/19/19
|
||||
--
|
||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.numeric_std.all;
|
||||
|
||||
ENTITY interpolatorCalculatePolynom IS
|
||||
GENERIC(
|
||||
signalBitNb : positive := 16;
|
||||
coeffBitNb : positive := 16;
|
||||
oversamplingBitNb : positive := 8
|
||||
);
|
||||
PORT(
|
||||
clock : IN std_ulogic;
|
||||
reset : IN std_ulogic;
|
||||
restartPolynom : IN std_ulogic;
|
||||
d : IN signed (coeffBitNb-1 DOWNTO 0);
|
||||
sampleOut : OUT signed (signalBitNb-1 DOWNTO 0);
|
||||
c : IN signed (coeffBitNb-1 DOWNTO 0);
|
||||
b : IN signed (coeffBitNb-1 DOWNTO 0);
|
||||
a : IN signed (coeffBitNb-1 DOWNTO 0);
|
||||
en : IN std_ulogic
|
||||
);
|
||||
|
||||
-- Declarations
|
||||
|
||||
END interpolatorCalculatePolynom ;
|
||||
|
||||
@@ -0,0 +1,33 @@
|
||||
-- VHDL Entity SplineInterpolator.interpolatorCoefficients.symbol
|
||||
--
|
||||
-- Created:
|
||||
-- by - francois.francois (Aphelia)
|
||||
-- at - 13:00:20 02/19/19
|
||||
--
|
||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.numeric_std.all;
|
||||
|
||||
ENTITY interpolatorCoefficients IS
|
||||
GENERIC(
|
||||
bitNb : positive := 16;
|
||||
coeffBitNb : positive := 16
|
||||
);
|
||||
PORT(
|
||||
sample1 : IN signed (bitNb-1 DOWNTO 0);
|
||||
sample2 : IN signed (bitNb-1 DOWNTO 0);
|
||||
sample3 : IN signed (bitNb-1 DOWNTO 0);
|
||||
sample4 : IN signed (bitNb-1 DOWNTO 0);
|
||||
a : OUT signed (coeffBitNb-1 DOWNTO 0);
|
||||
b : OUT signed (coeffBitNb-1 DOWNTO 0);
|
||||
c : OUT signed (coeffBitNb-1 DOWNTO 0);
|
||||
d : OUT signed (coeffBitNb-1 DOWNTO 0);
|
||||
interpolateLinear : IN std_ulogic
|
||||
);
|
||||
|
||||
-- Declarations
|
||||
|
||||
END interpolatorCoefficients ;
|
||||
|
||||
@@ -0,0 +1,31 @@
|
||||
-- VHDL Entity SplineInterpolator.interpolatorShiftRegister.symbol
|
||||
--
|
||||
-- Created:
|
||||
-- by - francois.francois (Aphelia)
|
||||
-- at - 13:00:24 02/19/19
|
||||
--
|
||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.numeric_std.all;
|
||||
|
||||
ENTITY interpolatorShiftRegister IS
|
||||
GENERIC(
|
||||
signalBitNb : positive := 16
|
||||
);
|
||||
PORT(
|
||||
clock : IN std_ulogic;
|
||||
reset : IN std_ulogic;
|
||||
shiftSamples : IN std_ulogic;
|
||||
sampleIn : IN signed (signalBitNb-1 DOWNTO 0);
|
||||
sample1 : OUT signed (signalBitNb-1 DOWNTO 0);
|
||||
sample2 : OUT signed (signalBitNb-1 DOWNTO 0);
|
||||
sample3 : OUT signed (signalBitNb-1 DOWNTO 0);
|
||||
sample4 : OUT signed (signalBitNb-1 DOWNTO 0)
|
||||
);
|
||||
|
||||
-- Declarations
|
||||
|
||||
END interpolatorShiftRegister ;
|
||||
|
||||
@@ -0,0 +1,27 @@
|
||||
-- VHDL Entity SplineInterpolator.interpolatorTrigger.symbol
|
||||
--
|
||||
-- Created:
|
||||
-- by - francois.francois (Aphelia)
|
||||
-- at - 13:00:28 02/19/19
|
||||
--
|
||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.numeric_std.all;
|
||||
|
||||
ENTITY interpolatorTrigger IS
|
||||
GENERIC(
|
||||
counterBitNb : positive := 4
|
||||
);
|
||||
PORT(
|
||||
triggerOut : OUT std_ulogic;
|
||||
clock : IN std_ulogic;
|
||||
reset : IN std_ulogic;
|
||||
en : IN std_ulogic
|
||||
);
|
||||
|
||||
-- Declarations
|
||||
|
||||
END interpolatorTrigger ;
|
||||
|
||||
@@ -0,0 +1,25 @@
|
||||
-- VHDL Entity SplineInterpolator.offsetToUnsigned.symbol
|
||||
--
|
||||
-- Created:
|
||||
-- by - francois.francois (Aphelia)
|
||||
-- at - 13:00:32 02/19/19
|
||||
--
|
||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.numeric_std.all;
|
||||
|
||||
ENTITY offsetToUnsigned IS
|
||||
GENERIC(
|
||||
bitNb : positive := 16
|
||||
);
|
||||
PORT(
|
||||
unsignedOut : OUT unsigned (bitNb-1 DOWNTO 0);
|
||||
signedIn : IN signed (bitNb-1 DOWNTO 0)
|
||||
);
|
||||
|
||||
-- Declarations
|
||||
|
||||
END offsetToUnsigned ;
|
||||
|
||||
@@ -0,0 +1,26 @@
|
||||
-- VHDL Entity SplineInterpolator.resizer.symbol
|
||||
--
|
||||
-- Created:
|
||||
-- by - francois.francois (Aphelia)
|
||||
-- at - 13:00:36 02/19/19
|
||||
--
|
||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.numeric_std.all;
|
||||
|
||||
ENTITY resizer IS
|
||||
GENERIC(
|
||||
inputBitNb : positive := 16;
|
||||
outputBitNb : positive := 16
|
||||
);
|
||||
PORT(
|
||||
resizeOut : OUT unsigned (outputBitNb-1 DOWNTO 0);
|
||||
resizeIn : IN unsigned (inputBitNb-1 DOWNTO 0)
|
||||
);
|
||||
|
||||
-- Declarations
|
||||
|
||||
END resizer ;
|
||||
|
||||
@@ -1,4 +1,24 @@
|
||||
ARCHITECTURE studentVersion OF resizer IS
|
||||
|
||||
signal mySignal : unsigned(outputBitNb-1 downto 0);
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
BEGIN
|
||||
resizeOut <= (others => '0');
|
||||
|
||||
INPUT_BIGGER: if inputBitNb >= outputBitNb generate
|
||||
process(resizeIn)
|
||||
begin
|
||||
mySignal <= resize(shift_right(resizeIn, inputBitNb - outputBitNb), outputBitNb);
|
||||
end process;
|
||||
end generate INPUT_BIGGER;
|
||||
|
||||
OUTPUT_BIGGER: if inputBitNb <= outputBitNb generate
|
||||
process(resizeIn)
|
||||
begin
|
||||
mySignal <= shift_left(resize(resizeIn, outputBitNb), outputBitNb - inputBitNb);
|
||||
end process;
|
||||
end generate OUTPUT_BIGGER;
|
||||
|
||||
resizeOut <= mySignal;
|
||||
|
||||
END ARCHITECTURE studentVersion;
|
||||
|
||||
@@ -1,15 +1,25 @@
|
||||
ARCHITECTURE studentVersion OF sineTable IS
|
||||
|
||||
signal phaseTableAddress : unsigned(tableAddressBitNb-1 downto 0);
|
||||
signal phaseTableAddress2 : unsigned(tableAddressBitNb-1 downto 0);
|
||||
signal quarterSine : signed(sine'range);
|
||||
|
||||
BEGIN
|
||||
|
||||
phaseTableAddress <= phase(phase'high-2 downto phase'high-2-tableAddressBitNb+1);
|
||||
|
||||
quarterTable: process(phaseTableAddress)
|
||||
sequenceTable: process(phase)
|
||||
begin
|
||||
case to_integer(phaseTableAddress) is
|
||||
if phase(phase'high-1) = '1' then
|
||||
phaseTableAddress2 <= 8 - phaseTableAddress;
|
||||
else
|
||||
phaseTableAddress2 <= phaseTableAddress;
|
||||
end if;
|
||||
end process sequenceTable;
|
||||
|
||||
quarterTable: process(phaseTableAddress2)
|
||||
begin
|
||||
case to_integer(phaseTableAddress2) is
|
||||
when 0 => quarterSine <= to_signed(16#0000#, quarterSine'length);
|
||||
when 1 => quarterSine <= to_signed(16#18F9#, quarterSine'length);
|
||||
when 2 => quarterSine <= to_signed(16#30FB#, quarterSine'length);
|
||||
@@ -22,6 +32,15 @@ BEGIN
|
||||
end case;
|
||||
end process quarterTable;
|
||||
|
||||
sine <= (others => '0');
|
||||
invert: process(quarterSine)
|
||||
begin
|
||||
if phase(phase'high) = '1' then
|
||||
sine <= NOT quarterSine;
|
||||
else
|
||||
sine <= quarterSine;
|
||||
end if;
|
||||
end process invert;
|
||||
|
||||
--sine <= quarterSine;
|
||||
|
||||
END ARCHITECTURE studentVersion;
|
||||
|
||||
@@ -0,0 +1,31 @@
|
||||
-- VHDL Entity SplineInterpolator.sineGen.symbol
|
||||
--
|
||||
-- Created:
|
||||
-- by - francois.francois (Aphelia)
|
||||
-- at - 13:00:40 02/19/19
|
||||
--
|
||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.numeric_std.all;
|
||||
|
||||
ENTITY sineGen IS
|
||||
GENERIC(
|
||||
signalBitNb : positive := 16;
|
||||
phaseBitNb : positive := 10
|
||||
);
|
||||
PORT(
|
||||
clock : IN std_ulogic;
|
||||
reset : IN std_ulogic;
|
||||
step : IN unsigned (phaseBitNb-1 DOWNTO 0);
|
||||
sawtooth : OUT unsigned (signalBitNb-1 DOWNTO 0);
|
||||
sine : OUT unsigned (signalBitNb-1 DOWNTO 0);
|
||||
square : OUT unsigned (signalBitNb-1 DOWNTO 0);
|
||||
triangle : OUT unsigned (signalBitNb-1 DOWNTO 0)
|
||||
);
|
||||
|
||||
-- Declarations
|
||||
|
||||
END sineGen ;
|
||||
|
||||
307
02-SplineInterpolator/SplineInterpolator/hdl/sinegen_struct.vhg
Normal file
307
02-SplineInterpolator/SplineInterpolator/hdl/sinegen_struct.vhg
Normal file
@@ -0,0 +1,307 @@
|
||||
--
|
||||
-- VHDL Architecture SplineInterpolator.sineGen.struct
|
||||
--
|
||||
-- Created:
|
||||
-- by - axel.amand.UNKNOWN (WE7860)
|
||||
-- at - 14:42:04 28.04.2023
|
||||
--
|
||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.numeric_std.all;
|
||||
|
||||
LIBRARY SplineInterpolator;
|
||||
LIBRARY WaveformGenerator;
|
||||
|
||||
ARCHITECTURE struct OF sineGen IS
|
||||
|
||||
-- Architecture declarations
|
||||
constant tableAddressBitNb : positive := 3;
|
||||
constant sampleCountBitNb : positive := phaseBitNb-2-tableAddressBitNb;
|
||||
constant coeffBitNb : positive := signalBitNb+4;
|
||||
|
||||
-- Internal signal declarations
|
||||
SIGNAL a : signed(coeffBitNb-1 DOWNTO 0);
|
||||
SIGNAL b : signed(coeffBitNb-1 DOWNTO 0);
|
||||
SIGNAL c : signed(coeffBitNb-1 DOWNTO 0);
|
||||
SIGNAL d : signed(coeffBitNb-1 DOWNTO 0);
|
||||
SIGNAL logic0 : std_ulogic;
|
||||
SIGNAL logic1 : std_ulogic;
|
||||
SIGNAL newPolynom : std_ulogic;
|
||||
SIGNAL phase : unsigned(phaseBitNb-1 DOWNTO 0);
|
||||
SIGNAL sample1 : signed(signalBitNb-1 DOWNTO 0);
|
||||
SIGNAL sample2 : signed(signalBitNb-1 DOWNTO 0);
|
||||
SIGNAL sample3 : signed(signalBitNb-1 DOWNTO 0);
|
||||
SIGNAL sample4 : signed(signalBitNb-1 DOWNTO 0);
|
||||
SIGNAL sineSamples : signed(signalBitNb-1 DOWNTO 0);
|
||||
SIGNAL sineSigned : signed(signalBitNb-1 DOWNTO 0);
|
||||
|
||||
-- Implicit buffer signal declarations
|
||||
SIGNAL sawtooth_internal : unsigned (signalBitNb-1 DOWNTO 0);
|
||||
|
||||
|
||||
-- Component Declarations
|
||||
COMPONENT interpolatorCalculatePolynom
|
||||
GENERIC (
|
||||
signalBitNb : positive := 16;
|
||||
coeffBitNb : positive := 16;
|
||||
oversamplingBitNb : positive := 8
|
||||
);
|
||||
PORT (
|
||||
clock : IN std_ulogic ;
|
||||
reset : IN std_ulogic ;
|
||||
restartPolynom : IN std_ulogic ;
|
||||
d : IN signed (coeffBitNb-1 DOWNTO 0);
|
||||
sampleOut : OUT signed (signalBitNb-1 DOWNTO 0);
|
||||
c : IN signed (coeffBitNb-1 DOWNTO 0);
|
||||
b : IN signed (coeffBitNb-1 DOWNTO 0);
|
||||
a : IN signed (coeffBitNb-1 DOWNTO 0);
|
||||
en : IN std_ulogic
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT interpolatorCoefficients
|
||||
GENERIC (
|
||||
bitNb : positive := 16;
|
||||
coeffBitNb : positive := 16
|
||||
);
|
||||
PORT (
|
||||
sample1 : IN signed (bitNb-1 DOWNTO 0);
|
||||
sample2 : IN signed (bitNb-1 DOWNTO 0);
|
||||
sample3 : IN signed (bitNb-1 DOWNTO 0);
|
||||
sample4 : IN signed (bitNb-1 DOWNTO 0);
|
||||
a : OUT signed (coeffBitNb-1 DOWNTO 0);
|
||||
b : OUT signed (coeffBitNb-1 DOWNTO 0);
|
||||
c : OUT signed (coeffBitNb-1 DOWNTO 0);
|
||||
d : OUT signed (coeffBitNb-1 DOWNTO 0);
|
||||
interpolateLinear : IN std_ulogic
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT interpolatorShiftRegister
|
||||
GENERIC (
|
||||
signalBitNb : positive := 16
|
||||
);
|
||||
PORT (
|
||||
clock : IN std_ulogic ;
|
||||
reset : IN std_ulogic ;
|
||||
shiftSamples : IN std_ulogic ;
|
||||
sampleIn : IN signed (signalBitNb-1 DOWNTO 0);
|
||||
sample1 : OUT signed (signalBitNb-1 DOWNTO 0);
|
||||
sample2 : OUT signed (signalBitNb-1 DOWNTO 0);
|
||||
sample3 : OUT signed (signalBitNb-1 DOWNTO 0);
|
||||
sample4 : OUT signed (signalBitNb-1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT interpolatorTrigger
|
||||
GENERIC (
|
||||
counterBitNb : positive := 4
|
||||
);
|
||||
PORT (
|
||||
triggerOut : OUT std_ulogic ;
|
||||
clock : IN std_ulogic ;
|
||||
reset : IN std_ulogic ;
|
||||
en : IN std_ulogic
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT offsetToUnsigned
|
||||
GENERIC (
|
||||
bitNb : positive := 16
|
||||
);
|
||||
PORT (
|
||||
unsignedOut : OUT unsigned (bitNb-1 DOWNTO 0);
|
||||
signedIn : IN signed (bitNb-1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT resizer
|
||||
GENERIC (
|
||||
inputBitNb : positive := 16;
|
||||
outputBitNb : positive := 16
|
||||
);
|
||||
PORT (
|
||||
resizeOut : OUT unsigned (outputBitNb-1 DOWNTO 0);
|
||||
resizeIn : IN unsigned (inputBitNb-1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT sineTable
|
||||
GENERIC (
|
||||
inputBitNb : positive := 16;
|
||||
outputBitNb : positive := 16;
|
||||
tableAddressBitNb : positive := 3
|
||||
);
|
||||
PORT (
|
||||
sine : OUT signed (outputBitNb-1 DOWNTO 0);
|
||||
phase : IN unsigned (inputBitNb-1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT sawtoothGen
|
||||
GENERIC (
|
||||
bitNb : positive := 16
|
||||
);
|
||||
PORT (
|
||||
sawtooth : OUT unsigned (bitNb-1 DOWNTO 0);
|
||||
clock : IN std_ulogic ;
|
||||
reset : IN std_ulogic ;
|
||||
step : IN unsigned (bitNb-1 DOWNTO 0);
|
||||
en : IN std_ulogic
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT sawtoothToSquare
|
||||
GENERIC (
|
||||
bitNb : positive := 16
|
||||
);
|
||||
PORT (
|
||||
square : OUT unsigned (bitNb-1 DOWNTO 0);
|
||||
sawtooth : IN unsigned (bitNb-1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT sawtoothToTriangle
|
||||
GENERIC (
|
||||
bitNb : positive := 16
|
||||
);
|
||||
PORT (
|
||||
triangle : OUT unsigned (bitNb-1 DOWNTO 0);
|
||||
sawtooth : IN unsigned (bitNb-1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
-- Optional embedded configurations
|
||||
-- pragma synthesis_off
|
||||
FOR ALL : interpolatorCalculatePolynom USE ENTITY SplineInterpolator.interpolatorCalculatePolynom;
|
||||
FOR ALL : interpolatorCoefficients USE ENTITY SplineInterpolator.interpolatorCoefficients;
|
||||
FOR ALL : interpolatorShiftRegister USE ENTITY SplineInterpolator.interpolatorShiftRegister;
|
||||
FOR ALL : interpolatorTrigger USE ENTITY SplineInterpolator.interpolatorTrigger;
|
||||
FOR ALL : offsetToUnsigned USE ENTITY SplineInterpolator.offsetToUnsigned;
|
||||
FOR ALL : resizer USE ENTITY SplineInterpolator.resizer;
|
||||
FOR ALL : sawtoothGen USE ENTITY WaveformGenerator.sawtoothGen;
|
||||
FOR ALL : sawtoothToSquare USE ENTITY WaveformGenerator.sawtoothToSquare;
|
||||
FOR ALL : sawtoothToTriangle USE ENTITY WaveformGenerator.sawtoothToTriangle;
|
||||
FOR ALL : sineTable USE ENTITY SplineInterpolator.sineTable;
|
||||
-- pragma synthesis_on
|
||||
|
||||
|
||||
BEGIN
|
||||
-- Architecture concurrent statements
|
||||
-- HDL Embedded Text Block 2 eb2
|
||||
logic1 <= '1';
|
||||
|
||||
-- HDL Embedded Text Block 3 eb3
|
||||
logic0 <= '0';
|
||||
|
||||
|
||||
-- Instance port mappings.
|
||||
I_spline : interpolatorCalculatePolynom
|
||||
GENERIC MAP (
|
||||
signalBitNb => signalBitNb,
|
||||
coeffBitNb => coeffBitNb,
|
||||
oversamplingBitNb => sampleCountBitNb
|
||||
)
|
||||
PORT MAP (
|
||||
clock => clock,
|
||||
reset => reset,
|
||||
restartPolynom => newPolynom,
|
||||
d => d,
|
||||
sampleOut => sineSigned,
|
||||
c => c,
|
||||
b => b,
|
||||
a => a,
|
||||
en => logic1
|
||||
);
|
||||
I_coeffs : interpolatorCoefficients
|
||||
GENERIC MAP (
|
||||
bitNb => signalBitNb,
|
||||
coeffBitNb => coeffBitNb
|
||||
)
|
||||
PORT MAP (
|
||||
sample1 => sample1,
|
||||
sample2 => sample2,
|
||||
sample3 => sample3,
|
||||
sample4 => sample4,
|
||||
a => a,
|
||||
b => b,
|
||||
c => c,
|
||||
d => d,
|
||||
interpolateLinear => logic0
|
||||
);
|
||||
I_shReg : interpolatorShiftRegister
|
||||
GENERIC MAP (
|
||||
signalBitNb => signalBitNb
|
||||
)
|
||||
PORT MAP (
|
||||
clock => clock,
|
||||
reset => reset,
|
||||
shiftSamples => newPolynom,
|
||||
sampleIn => sineSamples,
|
||||
sample1 => sample1,
|
||||
sample2 => sample2,
|
||||
sample3 => sample3,
|
||||
sample4 => sample4
|
||||
);
|
||||
I_trig : interpolatorTrigger
|
||||
GENERIC MAP (
|
||||
counterBitNb => sampleCountBitNb
|
||||
)
|
||||
PORT MAP (
|
||||
triggerOut => newPolynom,
|
||||
clock => clock,
|
||||
reset => reset,
|
||||
en => logic1
|
||||
);
|
||||
I_unsigned : offsetToUnsigned
|
||||
GENERIC MAP (
|
||||
bitNb => signalBitNb
|
||||
)
|
||||
PORT MAP (
|
||||
unsignedOut => sine,
|
||||
signedIn => sineSigned
|
||||
);
|
||||
I_size : resizer
|
||||
GENERIC MAP (
|
||||
inputBitNb => phaseBitNb,
|
||||
outputBitNb => signalBitNb
|
||||
)
|
||||
PORT MAP (
|
||||
resizeOut => sawtooth_internal,
|
||||
resizeIn => phase
|
||||
);
|
||||
I_sin : sineTable
|
||||
GENERIC MAP (
|
||||
inputBitNb => phaseBitNb,
|
||||
outputBitNb => signalBitNb,
|
||||
tableAddressBitNb => tableAddressBitNb
|
||||
)
|
||||
PORT MAP (
|
||||
sine => sineSamples,
|
||||
phase => phase
|
||||
);
|
||||
I_saw : sawtoothGen
|
||||
GENERIC MAP (
|
||||
bitNb => phaseBitNb
|
||||
)
|
||||
PORT MAP (
|
||||
sawtooth => phase,
|
||||
clock => clock,
|
||||
reset => reset,
|
||||
step => step,
|
||||
en => logic1
|
||||
);
|
||||
I_square : sawtoothToSquare
|
||||
GENERIC MAP (
|
||||
bitNb => signalBitNb
|
||||
)
|
||||
PORT MAP (
|
||||
square => square,
|
||||
sawtooth => sawtooth_internal
|
||||
);
|
||||
I_tri : sawtoothToTriangle
|
||||
GENERIC MAP (
|
||||
bitNb => signalBitNb
|
||||
)
|
||||
PORT MAP (
|
||||
triangle => triangle,
|
||||
sawtooth => sawtooth_internal
|
||||
);
|
||||
|
||||
-- Implicit buffered output assignments
|
||||
sawtooth <= sawtooth_internal;
|
||||
|
||||
END struct;
|
||||
@@ -0,0 +1,27 @@
|
||||
-- VHDL Entity SplineInterpolator.sineTable.symbol
|
||||
--
|
||||
-- Created:
|
||||
-- by - francois.francois (Aphelia)
|
||||
-- at - 13:00:46 02/19/19
|
||||
--
|
||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.numeric_std.all;
|
||||
|
||||
ENTITY sineTable IS
|
||||
GENERIC(
|
||||
inputBitNb : positive := 16;
|
||||
outputBitNb : positive := 16;
|
||||
tableAddressBitNb : positive := 3
|
||||
);
|
||||
PORT(
|
||||
sine : OUT signed (outputBitNb-1 DOWNTO 0);
|
||||
phase : IN unsigned (inputBitNb-1 DOWNTO 0)
|
||||
);
|
||||
|
||||
-- Declarations
|
||||
|
||||
END sineTable ;
|
||||
|
||||
BIN
02-SplineInterpolator/SplineInterpolator/hds/.cache.dat
Normal file
BIN
02-SplineInterpolator/SplineInterpolator/hds/.cache.dat
Normal file
Binary file not shown.
@@ -0,0 +1,42 @@
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
NO_GRAPHIC 0
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 50,0 8 0
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 13,0 13 1
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 83,0 19 0
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 89,0 20 0
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 94,0 21 0
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 104,0 22 0
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 109,0 23 0
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 125,0 24 0
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 130,0 25 0
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 135,0 26 0
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 141,0 27 0
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 30 0
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 31 0
|
||||
@@ -0,0 +1,42 @@
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
NO_GRAPHIC 0
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 50,0 8 0
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 13,0 13 1
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 104,0 18 0
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 109,0 19 0
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 114,0 20 0
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 119,0 21 0
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 125,0 22 0
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 130,0 23 0
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 140,0 24 0
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 135,0 25 0
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 149,0 26 0
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 29 0
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 30 0
|
||||
@@ -0,0 +1,39 @@
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
NO_GRAPHIC 0
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 50,0 8 0
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 13,0 13 1
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 83,0 17 0
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 89,0 18 0
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 94,0 19 0
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 99,0 20 0
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 104,0 21 0
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 109,0 22 0
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 114,0 23 0
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 119,0 24 0
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 27 0
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 28 0
|
||||
@@ -0,0 +1,27 @@
|
||||
DESIGN interpolator@trigger
|
||||
VIEW symbol.sb
|
||||
NO_GRAPHIC 0
|
||||
DESIGN interpolator@trigger
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 50,0 8 0
|
||||
DESIGN interpolator@trigger
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 13,0 13 1
|
||||
DESIGN interpolator@trigger
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 57,0 17 0
|
||||
DESIGN interpolator@trigger
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 83,0 18 0
|
||||
DESIGN interpolator@trigger
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 89,0 19 0
|
||||
DESIGN interpolator@trigger
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 94,0 20 0
|
||||
DESIGN interpolator@trigger
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 23 0
|
||||
DESIGN interpolator@trigger
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 24 0
|
||||
@@ -0,0 +1,21 @@
|
||||
DESIGN offset@to@unsigned
|
||||
VIEW symbol.sb
|
||||
NO_GRAPHIC 0
|
||||
DESIGN offset@to@unsigned
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 50,0 8 0
|
||||
DESIGN offset@to@unsigned
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 13,0 13 1
|
||||
DESIGN offset@to@unsigned
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 57,0 17 0
|
||||
DESIGN offset@to@unsigned
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 83,0 18 0
|
||||
DESIGN offset@to@unsigned
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 21 0
|
||||
DESIGN offset@to@unsigned
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 22 0
|
||||
@@ -0,0 +1,21 @@
|
||||
DESIGN resizer
|
||||
VIEW symbol.sb
|
||||
NO_GRAPHIC 0
|
||||
DESIGN resizer
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 50,0 8 0
|
||||
DESIGN resizer
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 13,0 13 1
|
||||
DESIGN resizer
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 57,0 18 0
|
||||
DESIGN resizer
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 83,0 19 0
|
||||
DESIGN resizer
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 22 0
|
||||
DESIGN resizer
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 23 0
|
||||
@@ -0,0 +1,36 @@
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
NO_GRAPHIC 0
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 50,0 8 0
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 13,0 13 1
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 52,0 18 0
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 88,0 19 0
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 128,0 20 0
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 98,0 21 0
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 103,0 22 0
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 108,0 23 0
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 118,0 24 0
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 27 0
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 28 0
|
||||
@@ -0,0 +1,519 @@
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 84,0 9 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 12
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 0,0 16 2
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1,0 19 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 19
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1701,0 24 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1709,0 25 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1717,0 26 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1725,0 27 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2579,0 28 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2447,0 29 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1658,0 30 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 726,0 31 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1277,0 32 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1285,0 33 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1293,0 34 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1301,0 35 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1102,0 36 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2227,0 37 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 38
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 887,0 40 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 42
|
||||
LIBRARY SplineInterpolator
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW student@version
|
||||
GRAPHIC 3829,0 44 0
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 14,0 45 1
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 83,0 51 0
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 89,0 52 0
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 94,0 53 0
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 104,0 54 0
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 109,0 55 0
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 125,0 56 0
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 130,0 57 0
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 135,0 58 0
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 141,0 59 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3784,0 62 0
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 14,0 63 1
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 104,0 68 0
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 109,0 69 0
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 114,0 70 0
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 119,0 71 0
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 125,0 72 0
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 130,0 73 0
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 140,0 74 0
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 135,0 75 0
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 149,0 76 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3739,0 79 0
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 14,0 80 1
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 83,0 84 0
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 89,0 85 0
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 94,0 86 0
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 99,0 87 0
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 104,0 88 0
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 109,0 89 0
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 114,0 90 0
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 119,0 91 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3698,0 94 0
|
||||
DESIGN interpolator@trigger
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 14,0 95 1
|
||||
DESIGN interpolator@trigger
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 57,0 99 0
|
||||
DESIGN interpolator@trigger
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 83,0 100 0
|
||||
DESIGN interpolator@trigger
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 89,0 101 0
|
||||
DESIGN interpolator@trigger
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 94,0 102 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3846,0 105 0
|
||||
DESIGN offset@to@unsigned
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 14,0 106 1
|
||||
DESIGN offset@to@unsigned
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 57,0 110 0
|
||||
DESIGN offset@to@unsigned
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 83,0 111 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3584,0 114 0
|
||||
DESIGN resizer
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 14,0 115 1
|
||||
DESIGN resizer
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 57,0 120 0
|
||||
DESIGN resizer
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 83,0 121 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3601,0 124 0
|
||||
DESIGN sine@table
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 14,0 125 1
|
||||
DESIGN sine@table
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 57,0 131 0
|
||||
DESIGN sine@table
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 83,0 132 0
|
||||
LIBRARY WaveformGenerator
|
||||
DESIGN sawtooth@gen
|
||||
VIEW student@version
|
||||
GRAPHIC 3673,0 135 0
|
||||
DESIGN sawtooth@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 14,0 136 1
|
||||
DESIGN sawtooth@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 57,0 140 0
|
||||
DESIGN sawtooth@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 52,0 141 0
|
||||
DESIGN sawtooth@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 76,0 142 0
|
||||
DESIGN sawtooth@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 83,0 143 0
|
||||
DESIGN sawtooth@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 89,0 144 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2908,0 147 0
|
||||
DESIGN sawtooth@to@square
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 14,0 148 1
|
||||
DESIGN sawtooth@to@square
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 57,0 152 0
|
||||
DESIGN sawtooth@to@square
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 83,0 153 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2925,0 156 0
|
||||
DESIGN sawtooth@to@triangle
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 14,0 157 1
|
||||
DESIGN sawtooth@to@triangle
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 57,0 161 0
|
||||
DESIGN sawtooth@to@triangle
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 83,0 162 0
|
||||
LIBRARY SplineInterpolator
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 165
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3829,0 168 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3784,0 169 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3739,0 170 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3698,0 171 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3846,0 172 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3584,0 173 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3673,0 174 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2908,0 175 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2925,0 176 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3601,0 177 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 180
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2375,0 183 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 185
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2562,0 186 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 188
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 189
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3829,0 191 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3836,0 192 1
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1814,0 198 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1822,0 199 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1830,0 200 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1727,0 201 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2219,0 202 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1719,0 203 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1711,0 204 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1703,0 205 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2394,0 206 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3784,0 208 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3791,0 209 1
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1279,0 214 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1287,0 215 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1295,0 216 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1303,0 217 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1703,0 218 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1711,0 219 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1719,0 220 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1727,0 221 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2571,0 222 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3739,0 224 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3746,0 225 1
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1228,0 229 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1220,0 230 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1106,0 231 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1096,0 232 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1279,0 233 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1287,0 234 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1295,0 235 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1303,0 236 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3698,0 238 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3705,0 239 1
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1106,0 243 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 985,0 244 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 993,0 245 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2386,0 246 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3846,0 248 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3853,0 249 1
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 562,0 253 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2219,0 254 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3584,0 256 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3591,0 257 1
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 601,0 262 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 414,0 263 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3601,0 265 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3608,0 266 1
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1096,0 272 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 472,0 273 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3673,0 275 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3680,0 276 1
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 414,0 280 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 15,0 281 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 237,0 282 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 781,0 283 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2449,0 284 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2908,0 286 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2915,0 287 1
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 480,0 291 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 887,0 292 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2925,0 294 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2932,0 295 1
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 424,0 299 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 858,0 300 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 887,0 304 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 306
|
||||
@@ -0,0 +1,21 @@
|
||||
DESIGN sine@table
|
||||
VIEW symbol.sb
|
||||
NO_GRAPHIC 0
|
||||
DESIGN sine@table
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 50,0 8 0
|
||||
DESIGN sine@table
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 13,0 13 1
|
||||
DESIGN sine@table
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 57,0 19 0
|
||||
DESIGN sine@table
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 83,0 20 0
|
||||
DESIGN sine@table
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 23 0
|
||||
DESIGN sine@table
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 24 0
|
||||
@@ -0,0 +1,15 @@
|
||||
-- VHDL Entity SplineInterpolator_test.sineGen_tb.symbol
|
||||
--
|
||||
-- Created:
|
||||
-- by - francois.francois (Aphelia)
|
||||
-- at - 13:00:04 02/19/19
|
||||
--
|
||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
|
||||
|
||||
|
||||
ENTITY sineGen_tb IS
|
||||
-- Declarations
|
||||
|
||||
END sineGen_tb ;
|
||||
|
||||
@@ -0,0 +1,108 @@
|
||||
--
|
||||
-- VHDL Architecture SplineInterpolator_test.sineGen_tb.struct
|
||||
--
|
||||
-- Created:
|
||||
-- by - axel.amand.UNKNOWN (WE7860)
|
||||
-- at - 14:41:39 28.04.2023
|
||||
--
|
||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY SplineInterpolator;
|
||||
LIBRARY SplineInterpolator_test;
|
||||
|
||||
ARCHITECTURE struct OF sineGen_tb IS
|
||||
|
||||
-- Architecture declarations
|
||||
constant signalBitNb: positive := 16;
|
||||
constant phaseBitNb: positive := 10;
|
||||
constant clockFrequency: real := 60.0E6;
|
||||
--constant clockFrequency: real := 66.0E6;
|
||||
|
||||
-- Internal signal declarations
|
||||
SIGNAL clock : std_ulogic;
|
||||
SIGNAL reset : std_ulogic;
|
||||
SIGNAL sawtooth : unsigned(signalBitNb-1 DOWNTO 0);
|
||||
SIGNAL sine : unsigned(signalBitNb-1 DOWNTO 0);
|
||||
SIGNAL square : unsigned(signalBitNb-1 DOWNTO 0);
|
||||
SIGNAL step : unsigned(phaseBitNb-1 DOWNTO 0);
|
||||
SIGNAL triangle : unsigned(signalBitNb-1 DOWNTO 0);
|
||||
|
||||
|
||||
-- Component Declarations
|
||||
COMPONENT sineGen
|
||||
GENERIC (
|
||||
signalBitNb : positive := 16;
|
||||
phaseBitNb : positive := 10
|
||||
);
|
||||
PORT (
|
||||
clock : IN std_ulogic ;
|
||||
reset : IN std_ulogic ;
|
||||
step : IN unsigned (phaseBitNb-1 DOWNTO 0);
|
||||
sawtooth : OUT unsigned (signalBitNb-1 DOWNTO 0);
|
||||
sine : OUT unsigned (signalBitNb-1 DOWNTO 0);
|
||||
square : OUT unsigned (signalBitNb-1 DOWNTO 0);
|
||||
triangle : OUT unsigned (signalBitNb-1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT sineGen_tester
|
||||
GENERIC (
|
||||
signalBitNb : positive := 16;
|
||||
phaseBitNb : positive := 10;
|
||||
clockFrequency : real := 60.0E6
|
||||
);
|
||||
PORT (
|
||||
sawtooth : IN unsigned (signalBitNb-1 DOWNTO 0);
|
||||
sine : IN unsigned (signalBitNb-1 DOWNTO 0);
|
||||
square : IN unsigned (signalBitNb-1 DOWNTO 0);
|
||||
triangle : IN unsigned (signalBitNb-1 DOWNTO 0);
|
||||
clock : OUT std_ulogic ;
|
||||
reset : OUT std_ulogic ;
|
||||
step : OUT unsigned (phaseBitNb-1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
-- Optional embedded configurations
|
||||
-- pragma synthesis_off
|
||||
FOR ALL : sineGen USE ENTITY SplineInterpolator.sineGen;
|
||||
FOR ALL : sineGen_tester USE ENTITY SplineInterpolator_test.sineGen_tester;
|
||||
-- pragma synthesis_on
|
||||
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instance port mappings.
|
||||
I_DUT : sineGen
|
||||
GENERIC MAP (
|
||||
signalBitNb => signalBitNb,
|
||||
phaseBitNb => phaseBitNb
|
||||
)
|
||||
PORT MAP (
|
||||
clock => clock,
|
||||
reset => reset,
|
||||
step => step,
|
||||
sawtooth => sawtooth,
|
||||
sine => sine,
|
||||
square => square,
|
||||
triangle => triangle
|
||||
);
|
||||
I_tb : sineGen_tester
|
||||
GENERIC MAP (
|
||||
signalBitNb => signalBitNb,
|
||||
phaseBitNb => phaseBitNb,
|
||||
clockFrequency => clockFrequency
|
||||
)
|
||||
PORT MAP (
|
||||
sawtooth => sawtooth,
|
||||
sine => sine,
|
||||
square => square,
|
||||
triangle => triangle,
|
||||
clock => clock,
|
||||
reset => reset,
|
||||
step => step
|
||||
);
|
||||
|
||||
END struct;
|
||||
@@ -0,0 +1,32 @@
|
||||
-- VHDL Entity SplineInterpolator_test.sineGen_tester.interface
|
||||
--
|
||||
-- Created:
|
||||
-- by - axel.amand.UNKNOWN (WE7860)
|
||||
-- at - 14:41:39 28.04.2023
|
||||
--
|
||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY sineGen_tester IS
|
||||
GENERIC(
|
||||
signalBitNb : positive := 16;
|
||||
phaseBitNb : positive := 10;
|
||||
clockFrequency : real := 60.0E6
|
||||
);
|
||||
PORT(
|
||||
sawtooth : IN unsigned (signalBitNb-1 DOWNTO 0);
|
||||
sine : IN unsigned (signalBitNb-1 DOWNTO 0);
|
||||
square : IN unsigned (signalBitNb-1 DOWNTO 0);
|
||||
triangle : IN unsigned (signalBitNb-1 DOWNTO 0);
|
||||
clock : OUT std_ulogic;
|
||||
reset : OUT std_ulogic;
|
||||
step : OUT unsigned (phaseBitNb-1 DOWNTO 0)
|
||||
);
|
||||
|
||||
-- Declarations
|
||||
|
||||
END sineGen_tester ;
|
||||
|
||||
BIN
02-SplineInterpolator/SplineInterpolator_test/hds/.cache.dat
Normal file
BIN
02-SplineInterpolator/SplineInterpolator_test/hds/.cache.dat
Normal file
Binary file not shown.
@@ -0,0 +1,12 @@
|
||||
DESIGN sine@gen_tb
|
||||
VIEW symbol.sb
|
||||
NO_GRAPHIC 0
|
||||
DESIGN sine@gen_tb
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 50,0 8 0
|
||||
DESIGN sine@gen_tb
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 11 0
|
||||
DESIGN sine@gen_tb
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 12 0
|
||||
@@ -0,0 +1,153 @@
|
||||
DESIGN sine@gen_tb
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 0
|
||||
DESIGN sine@gen_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 142,0 9 0
|
||||
DESIGN sine@gen_tb
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 12
|
||||
DESIGN sine@gen_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 0,0 16 2
|
||||
DESIGN sine@gen_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1,0 19 0
|
||||
DESIGN sine@gen_tb
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 19
|
||||
DESIGN sine@gen_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 53,0 25 0
|
||||
DESIGN sine@gen_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 45,0 26 0
|
||||
DESIGN sine@gen_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 933,0 27 0
|
||||
DESIGN sine@gen_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 909,0 28 0
|
||||
DESIGN sine@gen_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 925,0 29 0
|
||||
DESIGN sine@gen_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 996,0 30 0
|
||||
DESIGN sine@gen_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 917,0 31 0
|
||||
DESIGN sine@gen_tb
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 32
|
||||
DESIGN sine@gen_tb
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 33
|
||||
LIBRARY SplineInterpolator
|
||||
DESIGN sine@gen
|
||||
VIEW struct
|
||||
GRAPHIC 1519,0 35 0
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 14,0 36 1
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 52,0 41 0
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 88,0 42 0
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 128,0 43 0
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 98,0 44 0
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 103,0 45 0
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 108,0 46 0
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 118,0 47 0
|
||||
LIBRARY SplineInterpolator_test
|
||||
DESIGN sine@gen_tester
|
||||
VIEW test
|
||||
GRAPHIC 421,0 50 0
|
||||
DESIGN sine@gen_tester
|
||||
VIEW interface
|
||||
GRAPHIC 14,0 51 1
|
||||
DESIGN sine@gen_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 935,0 57 0
|
||||
DESIGN sine@gen_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 911,0 58 0
|
||||
DESIGN sine@gen_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 927,0 59 0
|
||||
DESIGN sine@gen_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 919,0 60 0
|
||||
DESIGN sine@gen_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 55,0 61 0
|
||||
DESIGN sine@gen_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 47,0 62 0
|
||||
DESIGN sine@gen_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 998,0 63 0
|
||||
LIBRARY SplineInterpolator_test
|
||||
DESIGN sine@gen_tb
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 66
|
||||
DESIGN sine@gen_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1519,0 69 0
|
||||
DESIGN sine@gen_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 421,0 70 0
|
||||
DESIGN sine@gen_tb
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 73
|
||||
DESIGN sine@gen_tb
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 75
|
||||
DESIGN sine@gen_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1519,0 77 0
|
||||
DESIGN sine@gen_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1526,0 78 1
|
||||
DESIGN sine@gen_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 55,0 83 0
|
||||
DESIGN sine@gen_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 47,0 84 0
|
||||
DESIGN sine@gen_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 998,0 85 0
|
||||
DESIGN sine@gen_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 935,0 86 0
|
||||
DESIGN sine@gen_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 911,0 87 0
|
||||
DESIGN sine@gen_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 927,0 88 0
|
||||
DESIGN sine@gen_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 919,0 89 0
|
||||
DESIGN sine@gen_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 421,0 91 0
|
||||
DESIGN sine@gen_tb
|
||||
VIEW struct.bd
|
||||
GRAPHIC 428,0 92 1
|
||||
DESIGN sine@gen_tb
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 107
|
||||
@@ -0,0 +1,36 @@
|
||||
DESIGN sine@gen_tester
|
||||
VIEW interface
|
||||
NO_GRAPHIC 0
|
||||
DESIGN sine@gen_tester
|
||||
VIEW interface
|
||||
GRAPHIC 50,0 8 0
|
||||
DESIGN sine@gen_tester
|
||||
VIEW interface
|
||||
GRAPHIC 13,0 13 1
|
||||
DESIGN sine@gen_tester
|
||||
VIEW interface
|
||||
GRAPHIC 409,0 19 0
|
||||
DESIGN sine@gen_tester
|
||||
VIEW interface
|
||||
GRAPHIC 414,0 20 0
|
||||
DESIGN sine@gen_tester
|
||||
VIEW interface
|
||||
GRAPHIC 419,0 21 0
|
||||
DESIGN sine@gen_tester
|
||||
VIEW interface
|
||||
GRAPHIC 429,0 22 0
|
||||
DESIGN sine@gen_tester
|
||||
VIEW interface
|
||||
GRAPHIC 399,0 23 0
|
||||
DESIGN sine@gen_tester
|
||||
VIEW interface
|
||||
GRAPHIC 404,0 24 0
|
||||
DESIGN sine@gen_tester
|
||||
VIEW interface
|
||||
GRAPHIC 424,0 25 0
|
||||
DESIGN sine@gen_tester
|
||||
VIEW interface
|
||||
GRAPHIC 1,0 28 0
|
||||
DESIGN sine@gen_tester
|
||||
VIEW interface
|
||||
GRAPHIC 1,0 29 0
|
||||
Reference in New Issue
Block a user