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add resize + tabel

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This commit is contained in:
Rémi Heredero
2024-03-05 11:48:52 +01:00
parent 73dd7da0db
commit 681c567da7
46 changed files with 14970 additions and 524 deletions
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34
02-SplineInterpolator/SplineInterpolator/hdl/interpolatorcalculatepolynom_entity.vhg Normal file
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-- VHDL Entity SplineInterpolator.interpolatorCalculatePolynom.symbol
--
-- Created:
-- by - francois.francois (Aphelia)
-- at - 13:00:14 02/19/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY interpolatorCalculatePolynom IS
GENERIC(
signalBitNb : positive := 16;
coeffBitNb : positive := 16;
oversamplingBitNb : positive := 8
);
PORT(
clock : IN std_ulogic;
reset : IN std_ulogic;
restartPolynom : IN std_ulogic;
d : IN signed (coeffBitNb-1 DOWNTO 0);
sampleOut : OUT signed (signalBitNb-1 DOWNTO 0);
c : IN signed (coeffBitNb-1 DOWNTO 0);
b : IN signed (coeffBitNb-1 DOWNTO 0);
a : IN signed (coeffBitNb-1 DOWNTO 0);
en : IN std_ulogic
);
-- Declarations
END interpolatorCalculatePolynom ;

33
02-SplineInterpolator/SplineInterpolator/hdl/interpolatorcoefficients_entity.vhg Normal file
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-- VHDL Entity SplineInterpolator.interpolatorCoefficients.symbol
--
-- Created:
-- by - francois.francois (Aphelia)
-- at - 13:00:20 02/19/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY interpolatorCoefficients IS
GENERIC(
bitNb : positive := 16;
coeffBitNb : positive := 16
);
PORT(
sample1 : IN signed (bitNb-1 DOWNTO 0);
sample2 : IN signed (bitNb-1 DOWNTO 0);
sample3 : IN signed (bitNb-1 DOWNTO 0);
sample4 : IN signed (bitNb-1 DOWNTO 0);
a : OUT signed (coeffBitNb-1 DOWNTO 0);
b : OUT signed (coeffBitNb-1 DOWNTO 0);
c : OUT signed (coeffBitNb-1 DOWNTO 0);
d : OUT signed (coeffBitNb-1 DOWNTO 0);
interpolateLinear : IN std_ulogic
);
-- Declarations
END interpolatorCoefficients ;

31
02-SplineInterpolator/SplineInterpolator/hdl/interpolatorshiftregister_entity.vhg Normal file
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-- VHDL Entity SplineInterpolator.interpolatorShiftRegister.symbol
--
-- Created:
-- by - francois.francois (Aphelia)
-- at - 13:00:24 02/19/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY interpolatorShiftRegister IS
GENERIC(
signalBitNb : positive := 16
);
PORT(
clock : IN std_ulogic;
reset : IN std_ulogic;
shiftSamples : IN std_ulogic;
sampleIn : IN signed (signalBitNb-1 DOWNTO 0);
sample1 : OUT signed (signalBitNb-1 DOWNTO 0);
sample2 : OUT signed (signalBitNb-1 DOWNTO 0);
sample3 : OUT signed (signalBitNb-1 DOWNTO 0);
sample4 : OUT signed (signalBitNb-1 DOWNTO 0)
);
-- Declarations
END interpolatorShiftRegister ;

27
02-SplineInterpolator/SplineInterpolator/hdl/interpolatortrigger_entity.vhg Normal file
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-- VHDL Entity SplineInterpolator.interpolatorTrigger.symbol
--
-- Created:
-- by - francois.francois (Aphelia)
-- at - 13:00:28 02/19/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY interpolatorTrigger IS
GENERIC(
counterBitNb : positive := 4
);
PORT(
triggerOut : OUT std_ulogic;
clock : IN std_ulogic;
reset : IN std_ulogic;
en : IN std_ulogic
);
-- Declarations
END interpolatorTrigger ;

25
02-SplineInterpolator/SplineInterpolator/hdl/offsettounsigned_entity.vhg Normal file
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-- VHDL Entity SplineInterpolator.offsetToUnsigned.symbol
--
-- Created:
-- by - francois.francois (Aphelia)
-- at - 13:00:32 02/19/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY offsetToUnsigned IS
GENERIC(
bitNb : positive := 16
);
PORT(
unsignedOut : OUT unsigned (bitNb-1 DOWNTO 0);
signedIn : IN signed (bitNb-1 DOWNTO 0)
);
-- Declarations
END offsetToUnsigned ;

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02-SplineInterpolator/SplineInterpolator/hdl/resizer_entity.vhg Normal file
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-- VHDL Entity SplineInterpolator.resizer.symbol
--
-- Created:
-- by - francois.francois (Aphelia)
-- at - 13:00:36 02/19/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY resizer IS
GENERIC(
inputBitNb : positive := 16;
outputBitNb : positive := 16
);
PORT(
resizeOut : OUT unsigned (outputBitNb-1 DOWNTO 0);
resizeIn : IN unsigned (inputBitNb-1 DOWNTO 0)
);
-- Declarations
END resizer ;

22
02-SplineInterpolator/SplineInterpolator/hdl/resizer_studentVersion.vhd
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@@ -1,4 +1,24 @@
ARCHITECTURE studentVersion OF resizer IS
signal mySignal : unsigned(outputBitNb-1 downto 0);
--------------------------------------------------------------------------------
BEGIN
resizeOut <= (others => '0');
INPUT_BIGGER: if inputBitNb >= outputBitNb generate
process(resizeIn)
begin
mySignal <= resize(shift_right(resizeIn, inputBitNb - outputBitNb), outputBitNb);
end process;
end generate INPUT_BIGGER;
OUTPUT_BIGGER: if inputBitNb <= outputBitNb generate
process(resizeIn)
begin
mySignal <= shift_left(resize(resizeIn, outputBitNb), outputBitNb - inputBitNb);
end process;
end generate OUTPUT_BIGGER;
resizeOut <= mySignal;
END ARCHITECTURE studentVersion;

25
02-SplineInterpolator/SplineInterpolator/hdl/sineTable_studentVersion.vhd
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@@ -1,15 +1,25 @@
ARCHITECTURE studentVersion OF sineTable IS
signal phaseTableAddress : unsigned(tableAddressBitNb-1 downto 0);
signal phaseTableAddress2 : unsigned(tableAddressBitNb-1 downto 0);
signal quarterSine : signed(sine'range);
BEGIN
phaseTableAddress <= phase(phase'high-2 downto phase'high-2-tableAddressBitNb+1);
quarterTable: process(phaseTableAddress)
sequenceTable: process(phase)
begin
case to_integer(phaseTableAddress) is
if phase(phase'high-1) = '1' then
phaseTableAddress2 <= 8 - phaseTableAddress;
else
phaseTableAddress2 <= phaseTableAddress;
end if;
end process sequenceTable;
quarterTable: process(phaseTableAddress2)
begin
case to_integer(phaseTableAddress2) is
when 0 => quarterSine <= to_signed(16#0000#, quarterSine'length);
when 1 => quarterSine <= to_signed(16#18F9#, quarterSine'length);
when 2 => quarterSine <= to_signed(16#30FB#, quarterSine'length);
@@ -22,6 +32,15 @@ BEGIN
end case;
end process quarterTable;
sine <= (others => '0');
invert: process(quarterSine)
begin
if phase(phase'high) = '1' then
sine <= NOT quarterSine;
else
sine <= quarterSine;
end if;
end process invert;
--sine <= quarterSine;
END ARCHITECTURE studentVersion;

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02-SplineInterpolator/SplineInterpolator/hdl/sinegen_entity.vhg Normal file
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-- VHDL Entity SplineInterpolator.sineGen.symbol
--
-- Created:
-- by - francois.francois (Aphelia)
-- at - 13:00:40 02/19/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY sineGen IS
GENERIC(
signalBitNb : positive := 16;
phaseBitNb : positive := 10
);
PORT(
clock : IN std_ulogic;
reset : IN std_ulogic;
step : IN unsigned (phaseBitNb-1 DOWNTO 0);
sawtooth : OUT unsigned (signalBitNb-1 DOWNTO 0);
sine : OUT unsigned (signalBitNb-1 DOWNTO 0);
square : OUT unsigned (signalBitNb-1 DOWNTO 0);
triangle : OUT unsigned (signalBitNb-1 DOWNTO 0)
);
-- Declarations
END sineGen ;

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02-SplineInterpolator/SplineInterpolator/hdl/sinegen_struct.vhg Normal file
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--
-- VHDL Architecture SplineInterpolator.sineGen.struct
--
-- Created:
-- by - axel.amand.UNKNOWN (WE7860)
-- at - 14:42:04 28.04.2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY SplineInterpolator;
LIBRARY WaveformGenerator;
ARCHITECTURE struct OF sineGen IS
-- Architecture declarations
constant tableAddressBitNb : positive := 3;
constant sampleCountBitNb : positive := phaseBitNb-2-tableAddressBitNb;
constant coeffBitNb : positive := signalBitNb+4;
-- Internal signal declarations
SIGNAL a : signed(coeffBitNb-1 DOWNTO 0);
SIGNAL b : signed(coeffBitNb-1 DOWNTO 0);
SIGNAL c : signed(coeffBitNb-1 DOWNTO 0);
SIGNAL d : signed(coeffBitNb-1 DOWNTO 0);
SIGNAL logic0 : std_ulogic;
SIGNAL logic1 : std_ulogic;
SIGNAL newPolynom : std_ulogic;
SIGNAL phase : unsigned(phaseBitNb-1 DOWNTO 0);
SIGNAL sample1 : signed(signalBitNb-1 DOWNTO 0);
SIGNAL sample2 : signed(signalBitNb-1 DOWNTO 0);
SIGNAL sample3 : signed(signalBitNb-1 DOWNTO 0);
SIGNAL sample4 : signed(signalBitNb-1 DOWNTO 0);
SIGNAL sineSamples : signed(signalBitNb-1 DOWNTO 0);
SIGNAL sineSigned : signed(signalBitNb-1 DOWNTO 0);
-- Implicit buffer signal declarations
SIGNAL sawtooth_internal : unsigned (signalBitNb-1 DOWNTO 0);
-- Component Declarations
COMPONENT interpolatorCalculatePolynom
GENERIC (
signalBitNb : positive := 16;
coeffBitNb : positive := 16;
oversamplingBitNb : positive := 8
);
PORT (
clock : IN std_ulogic ;
reset : IN std_ulogic ;
restartPolynom : IN std_ulogic ;
d : IN signed (coeffBitNb-1 DOWNTO 0);
sampleOut : OUT signed (signalBitNb-1 DOWNTO 0);
c : IN signed (coeffBitNb-1 DOWNTO 0);
b : IN signed (coeffBitNb-1 DOWNTO 0);
a : IN signed (coeffBitNb-1 DOWNTO 0);
en : IN std_ulogic
);
END COMPONENT;
COMPONENT interpolatorCoefficients
GENERIC (
bitNb : positive := 16;
coeffBitNb : positive := 16
);
PORT (
sample1 : IN signed (bitNb-1 DOWNTO 0);
sample2 : IN signed (bitNb-1 DOWNTO 0);
sample3 : IN signed (bitNb-1 DOWNTO 0);
sample4 : IN signed (bitNb-1 DOWNTO 0);
a : OUT signed (coeffBitNb-1 DOWNTO 0);
b : OUT signed (coeffBitNb-1 DOWNTO 0);
c : OUT signed (coeffBitNb-1 DOWNTO 0);
d : OUT signed (coeffBitNb-1 DOWNTO 0);
interpolateLinear : IN std_ulogic
);
END COMPONENT;
COMPONENT interpolatorShiftRegister
GENERIC (
signalBitNb : positive := 16
);
PORT (
clock : IN std_ulogic ;
reset : IN std_ulogic ;
shiftSamples : IN std_ulogic ;
sampleIn : IN signed (signalBitNb-1 DOWNTO 0);
sample1 : OUT signed (signalBitNb-1 DOWNTO 0);
sample2 : OUT signed (signalBitNb-1 DOWNTO 0);
sample3 : OUT signed (signalBitNb-1 DOWNTO 0);
sample4 : OUT signed (signalBitNb-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT interpolatorTrigger
GENERIC (
counterBitNb : positive := 4
);
PORT (
triggerOut : OUT std_ulogic ;
clock : IN std_ulogic ;
reset : IN std_ulogic ;
en : IN std_ulogic
);
END COMPONENT;
COMPONENT offsetToUnsigned
GENERIC (
bitNb : positive := 16
);
PORT (
unsignedOut : OUT unsigned (bitNb-1 DOWNTO 0);
signedIn : IN signed (bitNb-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT resizer
GENERIC (
inputBitNb : positive := 16;
outputBitNb : positive := 16
);
PORT (
resizeOut : OUT unsigned (outputBitNb-1 DOWNTO 0);
resizeIn : IN unsigned (inputBitNb-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT sineTable
GENERIC (
inputBitNb : positive := 16;
outputBitNb : positive := 16;
tableAddressBitNb : positive := 3
);
PORT (
sine : OUT signed (outputBitNb-1 DOWNTO 0);
phase : IN unsigned (inputBitNb-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT sawtoothGen
GENERIC (
bitNb : positive := 16
);
PORT (
sawtooth : OUT unsigned (bitNb-1 DOWNTO 0);
clock : IN std_ulogic ;
reset : IN std_ulogic ;
step : IN unsigned (bitNb-1 DOWNTO 0);
en : IN std_ulogic
);
END COMPONENT;
COMPONENT sawtoothToSquare
GENERIC (
bitNb : positive := 16
);
PORT (
square : OUT unsigned (bitNb-1 DOWNTO 0);
sawtooth : IN unsigned (bitNb-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT sawtoothToTriangle
GENERIC (
bitNb : positive := 16
);
PORT (
triangle : OUT unsigned (bitNb-1 DOWNTO 0);
sawtooth : IN unsigned (bitNb-1 DOWNTO 0)
);
END COMPONENT;
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : interpolatorCalculatePolynom USE ENTITY SplineInterpolator.interpolatorCalculatePolynom;
FOR ALL : interpolatorCoefficients USE ENTITY SplineInterpolator.interpolatorCoefficients;
FOR ALL : interpolatorShiftRegister USE ENTITY SplineInterpolator.interpolatorShiftRegister;
FOR ALL : interpolatorTrigger USE ENTITY SplineInterpolator.interpolatorTrigger;
FOR ALL : offsetToUnsigned USE ENTITY SplineInterpolator.offsetToUnsigned;
FOR ALL : resizer USE ENTITY SplineInterpolator.resizer;
FOR ALL : sawtoothGen USE ENTITY WaveformGenerator.sawtoothGen;
FOR ALL : sawtoothToSquare USE ENTITY WaveformGenerator.sawtoothToSquare;
FOR ALL : sawtoothToTriangle USE ENTITY WaveformGenerator.sawtoothToTriangle;
FOR ALL : sineTable USE ENTITY SplineInterpolator.sineTable;
-- pragma synthesis_on
BEGIN
-- Architecture concurrent statements
-- HDL Embedded Text Block 2 eb2
logic1 <= '1';
-- HDL Embedded Text Block 3 eb3
logic0 <= '0';
-- Instance port mappings.
I_spline : interpolatorCalculatePolynom
GENERIC MAP (
signalBitNb => signalBitNb,
coeffBitNb => coeffBitNb,
oversamplingBitNb => sampleCountBitNb
)
PORT MAP (
clock => clock,
reset => reset,
restartPolynom => newPolynom,
d => d,
sampleOut => sineSigned,
c => c,
b => b,
a => a,
en => logic1
);
I_coeffs : interpolatorCoefficients
GENERIC MAP (
bitNb => signalBitNb,
coeffBitNb => coeffBitNb
)
PORT MAP (
sample1 => sample1,
sample2 => sample2,
sample3 => sample3,
sample4 => sample4,
a => a,
b => b,
c => c,
d => d,
interpolateLinear => logic0
);
I_shReg : interpolatorShiftRegister
GENERIC MAP (
signalBitNb => signalBitNb
)
PORT MAP (
clock => clock,
reset => reset,
shiftSamples => newPolynom,
sampleIn => sineSamples,
sample1 => sample1,
sample2 => sample2,
sample3 => sample3,
sample4 => sample4
);
I_trig : interpolatorTrigger
GENERIC MAP (
counterBitNb => sampleCountBitNb
)
PORT MAP (
triggerOut => newPolynom,
clock => clock,
reset => reset,
en => logic1
);
I_unsigned : offsetToUnsigned
GENERIC MAP (
bitNb => signalBitNb
)
PORT MAP (
unsignedOut => sine,
signedIn => sineSigned
);
I_size : resizer
GENERIC MAP (
inputBitNb => phaseBitNb,
outputBitNb => signalBitNb
)
PORT MAP (
resizeOut => sawtooth_internal,
resizeIn => phase
);
I_sin : sineTable
GENERIC MAP (
inputBitNb => phaseBitNb,
outputBitNb => signalBitNb,
tableAddressBitNb => tableAddressBitNb
)
PORT MAP (
sine => sineSamples,
phase => phase
);
I_saw : sawtoothGen
GENERIC MAP (
bitNb => phaseBitNb
)
PORT MAP (
sawtooth => phase,
clock => clock,
reset => reset,
step => step,
en => logic1
);
I_square : sawtoothToSquare
GENERIC MAP (
bitNb => signalBitNb
)
PORT MAP (
square => square,
sawtooth => sawtooth_internal
);
I_tri : sawtoothToTriangle
GENERIC MAP (
bitNb => signalBitNb
)
PORT MAP (
triangle => triangle,
sawtooth => sawtooth_internal
);
-- Implicit buffered output assignments
sawtooth <= sawtooth_internal;
END struct;

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02-SplineInterpolator/SplineInterpolator/hdl/sinetable_entity.vhg Normal file
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-- VHDL Entity SplineInterpolator.sineTable.symbol
--
-- Created:
-- by - francois.francois (Aphelia)
-- at - 13:00:46 02/19/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY sineTable IS
GENERIC(
inputBitNb : positive := 16;
outputBitNb : positive := 16;
tableAddressBitNb : positive := 3
);
PORT(
sine : OUT signed (outputBitNb-1 DOWNTO 0);
phase : IN unsigned (inputBitNb-1 DOWNTO 0)
);
-- Declarations
END sineTable ;