Klagarge/SEm-Labos
1
0
Fork 0
Code

add ahbGPIO

Browse Source
This commit is contained in:
Rémi Heredero 2024-04-19 16:11:36 +02:00
parent 1b569b2b42
commit 6ce04fe6d4
8 changed files with 4387 additions and 280 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

102
06-07-08-09-SystemOnChip/AhbLiteComponents/hdl/ahbGpio_studentVersion.vhd
View File

@ -17,18 +17,22 @@
-- Read registers -- Read registers
-- 00, data register provides the values detected on the lines. -- 00, data register provides the values detected on the lines.
-- --
signal addresses is unsigned(32 downto 0);
signal bRead is std_ulogic;
signal bWrite is std_ulogic;
ARCHITECTURE studentVersion OF ahbGpio IS ARCHITECTURE studentVersion OF ahbGpio IS
signal addresses: unsigned(hAddr'range);
signal bRead: std_ulogic;
signal bWrite: std_ulogic;
signal bDone: std_ulogic;
BEGIN BEGIN
process(hReset_n, hClk) begin process(hReset_n, hClk) begin
if hReset_n = '1' then if hReset_n = '0' then
-- AHB-Lite -- AHB-Lite
--hRData <= (OTHERS => 'Z');
hRData <= (OTHERS => '0'); hRData <= (OTHERS => '0');
hReady <= '0'; hReady <= '1';
hResp <= '0'; hResp <= '0';
-- Out -- Out
@ -37,16 +41,90 @@ BEGIN
addresses <= (OTHERS => '0'); addresses <= (OTHERS => '0');
bRead <= '0'; bRead <= '0';
bWrite <= '1'; bWrite <= '0';
bDone <= '0';
elsif rising_edge(hClk) then elsif rising_edge(hClk) then
if hSel = '1' then if hSel = '1' then
CASE hAddr is bWrite <= hWrite;
WHEN 00 => bRead <= not hWrite;
WHEN 01 => addresses <= hAddr;
WHEN OTHERS hReady <= '0';
end CASE; bDone <= '0';
else
bWrite <= '0';
bRead <= '0';
end if; end if;
if bRead = '1' and bWrite = '0' then
-------------------------------------------------------------------------
-- READ
-------------------------------------------------------------------------
if addresses = "00" then
-- ##### Read data register #####
--hRData <= unsigned(resize(ioIn, ioNb));
for i in 0 to ioNb-1 loop
hRData(i) <= ioIn(i);
end loop;
bDone <= '1';
elsif addresses = "01" then
report "@@@@@@@@@@ Not possible to change output in READ mode @@@@@@@@@@" severity error;
end if;
elsif bRead = '0' and bWrite = '1' then
-------------------------------------------------------------------------
-- WRITE
-------------------------------------------------------------------------
if addresses = "00" then
-- ##### Write data register #####
--ioOut <= resize(std_ulogic_vector(hWData), ioNb);
for i in 0 to ioNb-1 loop
ioOut(i) <= hWData(i);
end loop;
bDone <= '1';
elsif addresses = "01" then
-- ##### Write direction register #####
--ioEn <= hWData;
for i in 0 to ioNb-1 loop
ioEn(i) <= hWData(i);
end loop;
bDone <= '1';
end if;
elsif bRead = '1' and bWrite = '1' then
-------------------------------------------------------------------------
-- SHOULD NEVER HAPPEN
-------------------------------------------------------------------------
report "@@@@@@@@@@ READ and WRITE can't happened in same time @@@@@@@@@@" severity error;
end if;
if (ioIn and ioEn) = (ioEn and ioOut) then
hResp <= '0';
else
hResp <= '1';
end if;
if bDone = '1' then
--hRData <= (OTHERS => 'Z');
bDone <= '0';
hReady <= '1';
end if;
end if; end if;
for i in (ioNb-1) downto 0 loop
if (ioEn(i) and ioIn(i)) /= (ioEn(i) and ioOut(i)) then
--ioEn(i) <= '0';
report "an output was in conflict" severity note;
end if;
end loop;
end process; end process;
-- AHB-Lite -- AHB-Lite

BIN
06-07-08-09-SystemOnChip/AhbLiteComponents/hds/.cache.dat
View File

Binary file not shown.

4
06-07-08-09-SystemOnChip/AhbLiteComponents_test/hdl/ahbgpio_tb_struct.vhg
View File

@ -2,8 +2,8 @@
-- VHDL Architecture AhbLiteComponents_test.ahbGpio_tb.struct -- VHDL Architecture AhbLiteComponents_test.ahbGpio_tb.struct
-- --
-- Created: -- Created:
-- by - axel.amand.UNKNOWN (WE7860) -- by - remi.heredero.UNKNOWN (WE2330808)
-- at - 15:06:49 28.04.2023 -- at - 14:16:25 19.04.2024
-- --
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) -- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
-- --

BIN
06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/.cache.dat
View File

Binary file not shown.

88
06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/ahb@gpio_tb/struct.bd
View File

@ -74,23 +74,23 @@ value " "
) )
(vvPair (vvPair
variable "HDLDir" variable "HDLDir"
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hdl" value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hdl"
) )
(vvPair (vvPair
variable "HDSDir" variable "HDSDir"
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds" value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds"
) )
(vvPair (vvPair
variable "SideDataDesignDir" variable "SideDataDesignDir"
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb\\struct.bd.info" value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb\\struct.bd.info"
) )
(vvPair (vvPair
variable "SideDataUserDir" variable "SideDataUserDir"
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb\\struct.bd.user" value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb\\struct.bd.user"
) )
(vvPair (vvPair
variable "SourceDir" variable "SourceDir"
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds" value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds"
) )
(vvPair (vvPair
variable "appl" variable "appl"
@ -114,15 +114,15 @@ value "%(unit)_%(view)_config"
) )
(vvPair (vvPair
variable "d" variable "d"
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb" value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb"
) )
(vvPair (vvPair
variable "d_logical" variable "d_logical"
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahbGpio_tb" value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahbGpio_tb"
) )
(vvPair (vvPair
variable "date" variable "date"
value "28.04.2023" value "19.04.2024"
) )
(vvPair (vvPair
variable "day" variable "day"
@ -134,7 +134,7 @@ value "vendredi"
) )
(vvPair (vvPair
variable "dd" variable "dd"
value "28" value "19"
) )
(vvPair (vvPair
variable "designName" variable "designName"
@ -162,11 +162,11 @@ value "struct"
) )
(vvPair (vvPair
variable "graphical_source_author" variable "graphical_source_author"
value "axel.amand" value "remi.heredero"
) )
(vvPair (vvPair
variable "graphical_source_date" variable "graphical_source_date"
value "28.04.2023" value "19.04.2024"
) )
(vvPair (vvPair
variable "graphical_source_group" variable "graphical_source_group"
@ -174,11 +174,11 @@ value "UNKNOWN"
) )
(vvPair (vvPair
variable "graphical_source_host" variable "graphical_source_host"
value "WE7860" value "WE2330808"
) )
(vvPair (vvPair
variable "graphical_source_time" variable "graphical_source_time"
value "15:06:49" value "14:16:25"
) )
(vvPair (vvPair
variable "group" variable "group"
@ -186,7 +186,7 @@ value "UNKNOWN"
) )
(vvPair (vvPair
variable "host" variable "host"
value "WE7860" value "WE2330808"
) )
(vvPair (vvPair
variable "language" variable "language"
@ -222,11 +222,11 @@ value "avril"
) )
(vvPair (vvPair
variable "p" variable "p"
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb\\struct.bd" value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb\\struct.bd"
) )
(vvPair (vvPair
variable "p_logical" variable "p_logical"
value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahbGpio_tb\\struct.bd" value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahbGpio_tb\\struct.bd"
) )
(vvPair (vvPair
variable "package_name" variable "package_name"
@ -306,7 +306,7 @@ value "struct"
) )
(vvPair (vvPair
variable "time" variable "time"
value "15:06:49" value "14:16:25"
) )
(vvPair (vvPair
variable "unit" variable "unit"
@ -314,7 +314,7 @@ value "ahbGpio_tb"
) )
(vvPair (vvPair
variable "user" variable "user"
value "axel.amand" value "remi.heredero"
) )
(vvPair (vvPair
variable "version" variable "version"
@ -326,11 +326,11 @@ value "struct"
) )
(vvPair (vvPair
variable "year" variable "year"
value "2023" value "2024"
) )
(vvPair (vvPair
variable "yy" variable "yy"
value "23" value "24"
) )
] ]
) )
@ -668,8 +668,7 @@ isHidden 1
font "Courier New,9,0" font "Courier New,9,0"
) )
xt "0,0,15500,1200" xt "0,0,15500,1200"
st "SIGNAL hReset_n : std_uLogic st "SIGNAL hReset_n : std_uLogic"
"
) )
) )
*13 (Net *13 (Net
@ -687,8 +686,7 @@ isHidden 1
font "Courier New,9,0" font "Courier New,9,0"
) )
xt "0,0,15500,1200" xt "0,0,15500,1200"
st "SIGNAL hClk : std_uLogic st "SIGNAL hClk : std_uLogic"
"
) )
) )
*14 (Net *14 (Net
@ -706,8 +704,7 @@ isHidden 1
font "Courier New,9,0" font "Courier New,9,0"
) )
xt "0,0,15500,1200" xt "0,0,15500,1200"
st "SIGNAL hResp : std_uLogic st "SIGNAL hResp : std_uLogic"
"
) )
) )
*15 (Net *15 (Net
@ -725,8 +722,7 @@ isHidden 1
font "Courier New,9,0" font "Courier New,9,0"
) )
xt "0,0,15500,1200" xt "0,0,15500,1200"
st "SIGNAL hReady : std_uLogic st "SIGNAL hReady : std_uLogic"
"
) )
) )
*16 (Net *16 (Net
@ -745,8 +741,7 @@ isHidden 1
font "Courier New,9,0" font "Courier New,9,0"
) )
xt "0,0,32000,1200" xt "0,0,32000,1200"
st "SIGNAL hRData : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0) st "SIGNAL hRData : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0)"
"
) )
) )
*17 (Net *17 (Net
@ -764,8 +759,7 @@ isHidden 1
font "Courier New,9,0" font "Courier New,9,0"
) )
xt "0,0,15500,1200" xt "0,0,15500,1200"
st "SIGNAL hSel : std_uLogic st "SIGNAL hSel : std_uLogic"
"
) )
) )
*18 (Net *18 (Net
@ -783,8 +777,7 @@ isHidden 1
font "Courier New,9,0" font "Courier New,9,0"
) )
xt "0,0,15500,1200" xt "0,0,15500,1200"
st "SIGNAL hWrite : std_uLogic st "SIGNAL hWrite : std_uLogic"
"
) )
) )
*19 (Net *19 (Net
@ -803,8 +796,7 @@ isHidden 1
font "Courier New,9,0" font "Courier New,9,0"
) )
xt "0,0,32500,1200" xt "0,0,32500,1200"
st "SIGNAL hTrans : std_ulogic_vector(ahbTransBitNb-1 DOWNTO 0) st "SIGNAL hTrans : std_ulogic_vector(ahbTransBitNb-1 DOWNTO 0)"
"
) )
) )
*20 (Net *20 (Net
@ -823,8 +815,7 @@ isHidden 1
font "Courier New,9,0" font "Courier New,9,0"
) )
xt "0,0,32000,1200" xt "0,0,32000,1200"
st "SIGNAL hWData : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0) st "SIGNAL hWData : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0)"
"
) )
) )
*21 (Net *21 (Net
@ -843,8 +834,7 @@ isHidden 1
font "Courier New,9,0" font "Courier New,9,0"
) )
xt "0,0,30000,1200" xt "0,0,30000,1200"
st "SIGNAL hAddr : unsigned( ahbAddressBitNb-1 DOWNTO 0 ) st "SIGNAL hAddr : unsigned( ahbAddressBitNb-1 DOWNTO 0 )"
"
) )
) )
*22 (Blk *22 (Blk
@ -1616,8 +1606,7 @@ isHidden 1
font "Courier New,9,0" font "Courier New,9,0"
) )
xt "0,0,28000,1200" xt "0,0,28000,1200"
st "SIGNAL ioEn : std_ulogic_vector(ioNb-1 DOWNTO 0) st "SIGNAL ioEn : std_ulogic_vector(ioNb-1 DOWNTO 0)"
"
) )
) )
*48 (Net *48 (Net
@ -1636,8 +1625,7 @@ isHidden 1
font "Courier New,9,0" font "Courier New,9,0"
) )
xt "0,0,28000,1200" xt "0,0,28000,1200"
st "SIGNAL ioOut : std_ulogic_vector(ioNb-1 DOWNTO 0) st "SIGNAL ioOut : std_ulogic_vector(ioNb-1 DOWNTO 0)"
"
) )
) )
*49 (Net *49 (Net
@ -1656,8 +1644,7 @@ isHidden 1
font "Courier New,9,0" font "Courier New,9,0"
) )
xt "0,0,28000,1200" xt "0,0,28000,1200"
st "SIGNAL ioIn : std_ulogic_vector(ioNb-1 DOWNTO 0) st "SIGNAL ioIn : std_ulogic_vector(ioNb-1 DOWNTO 0)"
"
) )
) )
*50 (Net *50 (Net
@ -1676,8 +1663,7 @@ isHidden 1
font "Courier New,9,0" font "Courier New,9,0"
) )
xt "0,0,27500,1200" xt "0,0,27500,1200"
st "SIGNAL io : std_logic_vector(ioNb-1 DOWNTO 0) st "SIGNAL io : std_logic_vector(ioNb-1 DOWNTO 0)"
"
) )
) )
*51 (Wire *51 (Wire
@ -2351,8 +2337,8 @@ tm "BdCompilerDirectivesTextMgr"
] ]
associable 1 associable 1
) )
windowSize "-8,-8,1928,1048" windowSize "164,195,1039,926"
viewArea "27426,17402,170102,94921" viewArea "49240,25632,103588,71748"
cachedDiagramExtent "0,0,138000,93000" cachedDiagramExtent "0,0,138000,93000"
pageSetupInfo (PageSetupInfo pageSetupInfo (PageSetupInfo
ptrCmd "\\\\SUN\\PREA309_HPLJ3005DN.PRINTERS.SYSTEM.SION.HEVs,winspool," ptrCmd "\\\\SUN\\PREA309_HPLJ3005DN.PRINTERS.SYSTEM.SION.HEVs,winspool,"
@ -2376,7 +2362,7 @@ boundaryWidth 0
) )
hasePageBreakOrigin 1 hasePageBreakOrigin 1
pageBreakOrigin "29000,19000" pageBreakOrigin "29000,19000"
lastUid 13522,0 lastUid 13575,0
defaultCommentText (CommentText defaultCommentText (CommentText
shape (Rectangle shape (Rectangle
layer 0 layer 0

4005
06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/ahb@gpio_tb/struct.bd.bak Normal file
View File

File diff suppressed because it is too large Load Diff

93
06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/hds_user_prefs
View File

@ -4149,7 +4149,7 @@ hdsWorkspaceLocation ""
relativeLibraryRootDir "" relativeLibraryRootDir ""
vmLabelLatestDontAskAgain 0 vmLabelLatestDontAskAgain 0
vmLabelWorkspaceDontAskAgain 0 vmLabelWorkspaceDontAskAgain 0
logWindowGeometry "636x406+308+98" logWindowGeometry "636x514+308+98"
diagramBrowserTabNo 0 diagramBrowserTabNo 0
showInsertPortHint 0 showInsertPortHint 0
showContentFirstTime 0 showContentFirstTime 0
@ -6031,6 +6031,96 @@ disableFilters 1
] ]
layoutExpression "V(H(A(C(DesignUnits),C(LogicalObjects)),A(C(Files))),A(C(DesignHierarchy)))" layoutExpression "V(H(A(C(DesignUnits),C(LogicalObjects)),A(C(Files))),A(C(DesignHierarchy)))"
) )
(Viewpoint_v2
name "Parse Errors Report"
TreeListVPDatas [
(TreeListVPData
theList "Hierarchy"
columns [
(TreeListVPData_Column
name "Design Unit Name"
displayName ""
width 150
)
(TreeListVPData_Column
name "Extends"
displayName ""
width 100
)
(TreeListVPData_Column
name "Name"
displayName ""
width 250
)
(TreeListVPData_Column
name "Library"
displayName ""
width 120
)
]
filterString ""
accessRights 2
)
]
SmartTableVPDatas [
(SmartTableVPData
theList "Logical Objects"
columns [
(SmartTableVPData_Column
name "Parse Error"
width 22
alignment 0
)
(SmartTableVPData_Column
name "File Name"
width 150
alignment 0
)
(SmartTableVPData_Column
name "Language"
width 100
alignment 0
)
(SmartTableVPData_Column
name "Library"
width 120
alignment 0
)
(SmartTableVPData_Column
name "Location"
width 200
alignment 0
)
(SmartTableVPData_Column
name "Absolute Path"
width 14
alignment 1
)
]
filterNames [
"Architectures and Modules"
"Configurations"
"Entities"
"Files"
"Instances"
"Packages"
"SV Classes"
"SV Interfaces"
"SV Packages"
"SV Program Blocks"
]
filterString "1"
filterColumn "Parse Error"
matchCase 0
matchWholeWordOnly 0
regularExpression 1
groupNames [
]
disableFilters 1
)
]
layoutExpression "V(A(C(LogicalObjects)))"
)
] ]
WorkTabs [ WorkTabs [
(WorkTab (WorkTab
@ -6226,6 +6316,7 @@ activeViewpointIdx 0
) )
] ]
ViewpointsOnOutlookBar [ ViewpointsOnOutlookBar [
"Parse Errors Report"
] ]
lastActiveViewpoint "Default Viewpoint" lastActiveViewpoint "Default Viewpoint"
expandedTemplateNodes [ expandedTemplateNodes [

375
06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/hds_user_prefs.bak
View File

@ -1280,6 +1280,7 @@ projectPaths [
"C:\\work\\repo\\edu\\sem\\labo\\solution\\sem_labs\\06-07-08-09-SystemOnChip\\Prefs\\hds.hdp" "C:\\work\\repo\\edu\\sem\\labo\\solution\\sem_labs\\06-07-08-09-SystemOnChip\\Prefs\\hds.hdp"
"C:\\work\\edu\\sem\\labo\\sem_labs\\06-07-08-09-SystemOnChip\\Prefs\\hds.hdp" "C:\\work\\edu\\sem\\labo\\sem_labs\\06-07-08-09-SystemOnChip\\Prefs\\hds.hdp"
"C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\hds.hdp" "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\hds.hdp"
"C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\hds.hdp"
] ]
libMappingsRootDir "" libMappingsRootDir ""
teamLibMappingsRootDir "" teamLibMappingsRootDir ""
@ -1300,288 +1301,144 @@ exportedDirectories [
exportStdIncludeRefs 1 exportStdIncludeRefs 1
exportStdPackageRefs 1 exportStdPackageRefs 1
) )
printerName "\\\\vmenpprint1.hevs.ch\\VS-FOLLOWME-PRN" printerName "\\\\vmenpprint1\\VS-ENP.23.N308-PRN"
pageSizes [ pageSizes [
(PageSizeInfo (PageSizeInfo
name "12\" x 18\"" name "Letter"
type 512 width 783
width 1106 height 1013
height 1658
) )
(PageSizeInfo (PageSizeInfo
name "11\" x 17\"" name "Legal"
type 17
width 1013
height 1566
)
(PageSizeInfo
name "Legal (8,5\" x 14\")"
type 5 type 5
width 783 width 783
height 1290 height 1290
) )
(PageSizeInfo (PageSizeInfo
name "Letter (8,5\" x 11\")" name "Statement"
width 783
height 1013
)
(PageSizeInfo
name "Executive (7,25\"x10,5\")"
type 7
width 667
height 967
)
(PageSizeInfo
name "5,5\" x 8,5\""
type 6 type 6
width 506 width 506
height 783 height 783
) )
(PageSizeInfo (PageSizeInfo
name "A3 (297 x 420 mm)" name "Executive"
type 7
width 667
height 967
)
(PageSizeInfo
name "A3"
type 8 type 8
width 1077 width 1077
height 1523 height 1523
) )
(PageSizeInfo (PageSizeInfo
name "A4 (210 x 297 mm)" name "A4"
type 9 type 9
width 761 width 761
height 1077 height 1077
) )
(PageSizeInfo (PageSizeInfo
name "A5 (148 x 210 mm)" name "A5"
type 11 type 11
width 538 width 536
height 761 height 761
) )
(PageSizeInfo (PageSizeInfo
name "A6 (105 x 148 mm)" name "B4 (JIS)"
type 70
width 380
height 538
)
(PageSizeInfo
name "B4 JIS (257 x 364 mm)"
type 12 type 12
width 932 width 932
height 1320 height 1320
) )
(PageSizeInfo (PageSizeInfo
name "B5 JIS (182 x 257 mm)" name "B5 (JIS)"
type 13 type 13
width 660 width 660
height 932 height 932
) )
(PageSizeInfo (PageSizeInfo
name "B6 JIS (128 x 182 mm)" name "11×17"
type 88 type 17
width 464 width 1013
height 660 height 1566
) )
(PageSizeInfo (PageSizeInfo
name "8\" x 13\"" name "Envelope #10"
type 518
width 737
height 1198
)
(PageSizeInfo
name "8,25\" x 13\""
type 519
width 760
height 1198
)
(PageSizeInfo
name "8,5\" x 13\""
type 14
width 783
height 1198
)
(PageSizeInfo
name "8.5\" x 13.4\""
type 551
width 783
height 1235
)
(PageSizeInfo
name "Com10 Env.(4,125\"x9,5\")"
type 20 type 20
width 380 width 379
height 875 height 875
) )
(PageSizeInfo (PageSizeInfo
name "Env.Monar.(3,875\"x7,5\")" name "Envelope DL"
type 37
width 357
height 691
)
(PageSizeInfo
name "Env. DL (110 x 220 mm)"
type 27 type 27
width 399 width 399
height 798 height 798
) )
(PageSizeInfo (PageSizeInfo
name "Env. C6 (114 x 162 mm)" name "Envelope C5"
type 31
width 413
height 587
)
(PageSizeInfo
name "Env. C5 (162 x 229 mm)"
type 28 type 28
width 587 width 587
height 830 height 830
) )
(PageSizeInfo (PageSizeInfo
name "8K (267 x 390 mm)" name "Envelope B5"
type 520 type 34
width 968 width 638
height 1415 height 907
) )
(PageSizeInfo (PageSizeInfo
name "16K (195 x 267 mm)" name "Envelope Monarch"
type 521 type 37
width 707 width 357
height 968 height 691
) )
(PageSizeInfo (PageSizeInfo
name "8,25\" x 14\"" name "Japanese Postcard"
type 522 type 43
width 760 width 362
height 1290 height 536
) )
(PageSizeInfo (PageSizeInfo
name "11\" x 14\"" name "A6"
type 524 type 70
width 1013 width 380
height 1290 height 536
) )
(PageSizeInfo (PageSizeInfo
name "13\" x 19,2\"" name "Double Japan Postcard Rotated"
type 525 type 82
width 1198 width 536
height 1769 height 725
) )
(PageSizeInfo (PageSizeInfo
name "13\" x 19\"" name "Executive (JIS)"
type 526 type 119
width 1198 width 783
height 1751 height 1196
) )
(PageSizeInfo (PageSizeInfo
name "12,6\" x 19,2\"" name "Oficio 8.5x13"
type 527 type 120
width 1161 width 783
height 1769 height 1198
) )
(PageSizeInfo (PageSizeInfo
name "12,6\" x 18,5\"" name "12x18"
type 528 type 121
width 1161 width 1105
height 1704
)
(PageSizeInfo
name "13\" x 18\""
type 529
width 1198
height 1658 height 1658
) )
(PageSizeInfo (PageSizeInfo
name "10\" x 14\"" name "8K 273x394 mm"
type 16 type 139
width 921 width 990
height 1290 height 1428
) )
(PageSizeInfo (PageSizeInfo
name "10\" x 15\"" name "16K 197x273 mm"
type 546 type 140
width 921 width 714
height 1382 height 990
)
(PageSizeInfo
name "11\" x 15\""
type 539
width 1013
height 1382
)
(PageSizeInfo
name "SRA3 (320 x 450 mm)"
type 530
width 1161
height 1632
)
(PageSizeInfo
name "SRA4 (225 x 320 mm)"
type 531
width 816
height 1161
)
(PageSizeInfo
name "Format papier personnalisé"
type 256
width 783
height 1013
)
(PageSizeInfo
name "Custom Paper Size1(215,9 x 279,4 mm)"
type 257
width 783
height 1013
)
(PageSizeInfo
name "Custom Paper Size2(215,9 x 279,4 mm)"
type 258
width 783
height 1013
)
(PageSizeInfo
name "Custom Paper Size3(215,9 x 279,4 mm)"
type 259
width 783
height 1013
)
(PageSizeInfo
name "Custom Paper Size4(215,9 x 279,4 mm)"
type 260
width 783
height 1013
)
(PageSizeInfo
name "Custom Paper Size5(215,9 x 279,4 mm)"
type 261
width 783
height 1013
)
(PageSizeInfo
name "Custom Paper Size6(215,9 x 279,4 mm)"
type 262
width 783
height 1013
)
(PageSizeInfo
name "Custom Paper Size7(215,9 x 279,4 mm)"
type 263
width 783
height 1013
)
(PageSizeInfo
name "Custom Paper Size8(215,9 x 279,4 mm)"
type 264
width 783
height 1013
)
(PageSizeInfo
name "Custom Paper Size9(215,9 x 279,4 mm)"
type 265
width 783
height 1013
)
(PageSizeInfo
name "Custom Paper Size10(215,9 x 279,4 mm)"
type 266
width 783
height 1013
) )
] ]
exportPageSetupInfo (PageSetupInfo exportPageSetupInfo (PageSetupInfo
@ -4292,7 +4149,7 @@ hdsWorkspaceLocation ""
relativeLibraryRootDir "" relativeLibraryRootDir ""
vmLabelLatestDontAskAgain 0 vmLabelLatestDontAskAgain 0
vmLabelWorkspaceDontAskAgain 0 vmLabelWorkspaceDontAskAgain 0
logWindowGeometry "636x406+-823+276" logWindowGeometry "636x406+308+98"
diagramBrowserTabNo 0 diagramBrowserTabNo 0
showInsertPortHint 0 showInsertPortHint 0
showContentFirstTime 0 showContentFirstTime 0
@ -6174,6 +6031,96 @@ disableFilters 1
] ]
layoutExpression "V(H(A(C(DesignUnits),C(LogicalObjects)),A(C(Files))),A(C(DesignHierarchy)))" layoutExpression "V(H(A(C(DesignUnits),C(LogicalObjects)),A(C(Files))),A(C(DesignHierarchy)))"
) )
(Viewpoint_v2
name "Parse Errors Report"
TreeListVPDatas [
(TreeListVPData
theList "Hierarchy"
columns [
(TreeListVPData_Column
name "Design Unit Name"
displayName ""
width 150
)
(TreeListVPData_Column
name "Extends"
displayName ""
width 100
)
(TreeListVPData_Column
name "Name"
displayName ""
width 250
)
(TreeListVPData_Column
name "Library"
displayName ""
width 120
)
]
filterString ""
accessRights 2
)
]
SmartTableVPDatas [
(SmartTableVPData
theList "Logical Objects"
columns [
(SmartTableVPData_Column
name "Parse Error"
width 22
alignment 0
)
(SmartTableVPData_Column
name "File Name"
width 150
alignment 0
)
(SmartTableVPData_Column
name "Language"
width 100
alignment 0
)
(SmartTableVPData_Column
name "Library"
width 120
alignment 0
)
(SmartTableVPData_Column
name "Location"
width 200
alignment 0
)
(SmartTableVPData_Column
name "Absolute Path"
width 14
alignment 1
)
]
filterNames [
"Architectures and Modules"
"Configurations"
"Entities"
"Files"
"Instances"
"Packages"
"SV Classes"
"SV Interfaces"
"SV Packages"
"SV Program Blocks"
]
filterString "1"
filterColumn "Parse Error"
matchCase 0
matchWholeWordOnly 0
regularExpression 1
groupNames [
]
disableFilters 1
)
]
layoutExpression "V(A(C(LogicalObjects)))"
)
] ]
WorkTabs [ WorkTabs [
(WorkTab (WorkTab
@ -6369,6 +6316,7 @@ activeViewpointIdx 0
) )
] ]
ViewpointsOnOutlookBar [ ViewpointsOnOutlookBar [
"Parse Errors Report"
] ]
lastActiveViewpoint "Default Viewpoint" lastActiveViewpoint "Default Viewpoint"
expandedTemplateNodes [ expandedTemplateNodes [
@ -6384,11 +6332,10 @@ size 180
] ]
displayHierarchy 0 displayHierarchy 0
xPos 0 xPos 0
yPos 0 yPos 9
width 1936 width 974
height 1056 height 1047
activeSidePanelTab 2 activeSidePanelTab 2
activeLibraryTab 1
sidePanelSize 278 sidePanelSize 278
showUnixHiddenFiles 0 showUnixHiddenFiles 0
componentBrowserXpos 569 componentBrowserXpos 569