add ahbGPIO
This commit is contained in:
parent
1b569b2b42
commit
6ce04fe6d4
@ -17,18 +17,22 @@
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-- Read registers
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-- 00, data register provides the values detected on the lines.
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--
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signal addresses is unsigned(32 downto 0);
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signal bRead is std_ulogic;
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signal bWrite is std_ulogic;
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ARCHITECTURE studentVersion OF ahbGpio IS
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signal addresses: unsigned(hAddr'range);
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signal bRead: std_ulogic;
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signal bWrite: std_ulogic;
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signal bDone: std_ulogic;
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BEGIN
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process(hReset_n, hClk) begin
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if hReset_n = '1' then
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if hReset_n = '0' then
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-- AHB-Lite
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--hRData <= (OTHERS => 'Z');
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hRData <= (OTHERS => '0');
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hReady <= '0';
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hReady <= '1';
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hResp <= '0';
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-- Out
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@ -37,16 +41,90 @@ BEGIN
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addresses <= (OTHERS => '0');
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bRead <= '0';
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bWrite <= '1';
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bWrite <= '0';
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bDone <= '0';
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elsif rising_edge(hClk) then
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if hSel = '1' then
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CASE hAddr is
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WHEN 00 =>
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WHEN 01 =>
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WHEN OTHERS
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end CASE;
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bWrite <= hWrite;
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bRead <= not hWrite;
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addresses <= hAddr;
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hReady <= '0';
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bDone <= '0';
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else
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bWrite <= '0';
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bRead <= '0';
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end if;
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if bRead = '1' and bWrite = '0' then
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-------------------------------------------------------------------------
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-- READ
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-------------------------------------------------------------------------
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if addresses = "00" then
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-- ##### Read data register #####
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--hRData <= unsigned(resize(ioIn, ioNb));
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for i in 0 to ioNb-1 loop
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hRData(i) <= ioIn(i);
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end loop;
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bDone <= '1';
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elsif addresses = "01" then
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report "@@@@@@@@@@ Not possible to change output in READ mode @@@@@@@@@@" severity error;
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end if;
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elsif bRead = '0' and bWrite = '1' then
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-------------------------------------------------------------------------
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-- WRITE
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-------------------------------------------------------------------------
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if addresses = "00" then
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-- ##### Write data register #####
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--ioOut <= resize(std_ulogic_vector(hWData), ioNb);
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for i in 0 to ioNb-1 loop
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ioOut(i) <= hWData(i);
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end loop;
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bDone <= '1';
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elsif addresses = "01" then
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-- ##### Write direction register #####
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--ioEn <= hWData;
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for i in 0 to ioNb-1 loop
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ioEn(i) <= hWData(i);
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end loop;
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bDone <= '1';
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end if;
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elsif bRead = '1' and bWrite = '1' then
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-------------------------------------------------------------------------
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-- SHOULD NEVER HAPPEN
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-------------------------------------------------------------------------
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report "@@@@@@@@@@ READ and WRITE can't happened in same time @@@@@@@@@@" severity error;
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end if;
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if (ioIn and ioEn) = (ioEn and ioOut) then
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hResp <= '0';
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else
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hResp <= '1';
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end if;
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if bDone = '1' then
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--hRData <= (OTHERS => 'Z');
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bDone <= '0';
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hReady <= '1';
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end if;
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end if;
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for i in (ioNb-1) downto 0 loop
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if (ioEn(i) and ioIn(i)) /= (ioEn(i) and ioOut(i)) then
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--ioEn(i) <= '0';
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report "an output was in conflict" severity note;
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end if;
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end loop;
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end process;
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-- AHB-Lite
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Binary file not shown.
@ -2,8 +2,8 @@
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-- VHDL Architecture AhbLiteComponents_test.ahbGpio_tb.struct
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--
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-- Created:
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-- by - axel.amand.UNKNOWN (WE7860)
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-- at - 15:06:49 28.04.2023
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-- by - remi.heredero.UNKNOWN (WE2330808)
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-- at - 14:16:25 19.04.2024
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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Binary file not shown.
@ -74,23 +74,23 @@ value " "
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)
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(vvPair
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variable "HDLDir"
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value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hdl"
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value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hdl"
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)
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(vvPair
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variable "HDSDir"
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value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds"
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value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds"
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)
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(vvPair
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variable "SideDataDesignDir"
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value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb\\struct.bd.info"
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value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb\\struct.bd.info"
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)
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(vvPair
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variable "SideDataUserDir"
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value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb\\struct.bd.user"
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value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb\\struct.bd.user"
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)
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(vvPair
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variable "SourceDir"
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value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds"
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value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds"
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)
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(vvPair
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variable "appl"
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@ -114,15 +114,15 @@ value "%(unit)_%(view)_config"
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)
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(vvPair
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variable "d"
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value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb"
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value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb"
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)
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(vvPair
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variable "d_logical"
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value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahbGpio_tb"
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value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahbGpio_tb"
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)
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(vvPair
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variable "date"
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value "28.04.2023"
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value "19.04.2024"
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)
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(vvPair
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variable "day"
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@ -134,7 +134,7 @@ value "vendredi"
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)
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(vvPair
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variable "dd"
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value "28"
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value "19"
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)
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(vvPair
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variable "designName"
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@ -162,11 +162,11 @@ value "struct"
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)
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(vvPair
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variable "graphical_source_author"
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value "axel.amand"
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value "remi.heredero"
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)
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(vvPair
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variable "graphical_source_date"
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value "28.04.2023"
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value "19.04.2024"
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)
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(vvPair
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variable "graphical_source_group"
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@ -174,11 +174,11 @@ value "UNKNOWN"
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)
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(vvPair
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variable "graphical_source_host"
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value "WE7860"
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value "WE2330808"
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)
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(vvPair
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variable "graphical_source_time"
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value "15:06:49"
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value "14:16:25"
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)
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(vvPair
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variable "group"
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@ -186,7 +186,7 @@ value "UNKNOWN"
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)
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(vvPair
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variable "host"
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value "WE7860"
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value "WE2330808"
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)
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(vvPair
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variable "language"
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@ -222,11 +222,11 @@ value "avril"
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)
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(vvPair
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variable "p"
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value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb\\struct.bd"
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value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahb@gpio_tb\\struct.bd"
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)
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(vvPair
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variable "p_logical"
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value "C:\\dev\\sem-labs\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahbGpio_tb\\struct.bd"
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value "C:\\Users\\remi.heredero\\GIT\\2024-sem-labs-herederoremi\\06-07-08-09-SystemOnChip\\Prefs\\..\\AhbLiteComponents_test\\hds\\ahbGpio_tb\\struct.bd"
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)
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(vvPair
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variable "package_name"
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@ -306,7 +306,7 @@ value "struct"
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)
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(vvPair
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variable "time"
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value "15:06:49"
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value "14:16:25"
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)
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(vvPair
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variable "unit"
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@ -314,7 +314,7 @@ value "ahbGpio_tb"
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)
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(vvPair
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variable "user"
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value "axel.amand"
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value "remi.heredero"
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)
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(vvPair
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variable "version"
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@ -326,11 +326,11 @@ value "struct"
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)
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(vvPair
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variable "year"
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value "2023"
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value "2024"
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)
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(vvPair
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variable "yy"
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value "23"
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value "24"
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)
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]
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)
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@ -668,8 +668,7 @@ isHidden 1
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font "Courier New,9,0"
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)
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xt "0,0,15500,1200"
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st "SIGNAL hReset_n : std_uLogic
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"
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st "SIGNAL hReset_n : std_uLogic"
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)
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)
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*13 (Net
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@ -687,8 +686,7 @@ isHidden 1
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font "Courier New,9,0"
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)
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xt "0,0,15500,1200"
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st "SIGNAL hClk : std_uLogic
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"
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st "SIGNAL hClk : std_uLogic"
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)
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)
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*14 (Net
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@ -706,8 +704,7 @@ isHidden 1
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font "Courier New,9,0"
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)
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xt "0,0,15500,1200"
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st "SIGNAL hResp : std_uLogic
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"
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st "SIGNAL hResp : std_uLogic"
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)
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)
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*15 (Net
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@ -725,8 +722,7 @@ isHidden 1
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font "Courier New,9,0"
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)
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xt "0,0,15500,1200"
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st "SIGNAL hReady : std_uLogic
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"
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st "SIGNAL hReady : std_uLogic"
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)
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)
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*16 (Net
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@ -745,8 +741,7 @@ isHidden 1
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font "Courier New,9,0"
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)
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xt "0,0,32000,1200"
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st "SIGNAL hRData : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0)
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"
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st "SIGNAL hRData : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0)"
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)
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)
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*17 (Net
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@ -764,8 +759,7 @@ isHidden 1
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font "Courier New,9,0"
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)
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xt "0,0,15500,1200"
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st "SIGNAL hSel : std_uLogic
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"
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st "SIGNAL hSel : std_uLogic"
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)
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)
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*18 (Net
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@ -783,8 +777,7 @@ isHidden 1
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font "Courier New,9,0"
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)
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xt "0,0,15500,1200"
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st "SIGNAL hWrite : std_uLogic
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"
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st "SIGNAL hWrite : std_uLogic"
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)
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)
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*19 (Net
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@ -803,8 +796,7 @@ isHidden 1
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font "Courier New,9,0"
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)
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xt "0,0,32500,1200"
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st "SIGNAL hTrans : std_ulogic_vector(ahbTransBitNb-1 DOWNTO 0)
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"
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st "SIGNAL hTrans : std_ulogic_vector(ahbTransBitNb-1 DOWNTO 0)"
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)
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)
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*20 (Net
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@ -823,8 +815,7 @@ isHidden 1
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font "Courier New,9,0"
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)
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xt "0,0,32000,1200"
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st "SIGNAL hWData : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0)
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"
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st "SIGNAL hWData : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0)"
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)
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)
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*21 (Net
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@ -843,8 +834,7 @@ isHidden 1
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font "Courier New,9,0"
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)
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xt "0,0,30000,1200"
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st "SIGNAL hAddr : unsigned( ahbAddressBitNb-1 DOWNTO 0 )
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"
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st "SIGNAL hAddr : unsigned( ahbAddressBitNb-1 DOWNTO 0 )"
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)
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)
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*22 (Blk
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@ -1616,8 +1606,7 @@ isHidden 1
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font "Courier New,9,0"
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)
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xt "0,0,28000,1200"
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st "SIGNAL ioEn : std_ulogic_vector(ioNb-1 DOWNTO 0)
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"
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st "SIGNAL ioEn : std_ulogic_vector(ioNb-1 DOWNTO 0)"
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)
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)
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*48 (Net
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||||
@ -1636,8 +1625,7 @@ isHidden 1
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font "Courier New,9,0"
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)
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xt "0,0,28000,1200"
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st "SIGNAL ioOut : std_ulogic_vector(ioNb-1 DOWNTO 0)
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"
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||||
st "SIGNAL ioOut : std_ulogic_vector(ioNb-1 DOWNTO 0)"
|
||||
)
|
||||
)
|
||||
*49 (Net
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||||
@ -1656,8 +1644,7 @@ isHidden 1
|
||||
font "Courier New,9,0"
|
||||
)
|
||||
xt "0,0,28000,1200"
|
||||
st "SIGNAL ioIn : std_ulogic_vector(ioNb-1 DOWNTO 0)
|
||||
"
|
||||
st "SIGNAL ioIn : std_ulogic_vector(ioNb-1 DOWNTO 0)"
|
||||
)
|
||||
)
|
||||
*50 (Net
|
||||
@ -1676,8 +1663,7 @@ isHidden 1
|
||||
font "Courier New,9,0"
|
||||
)
|
||||
xt "0,0,27500,1200"
|
||||
st "SIGNAL io : std_logic_vector(ioNb-1 DOWNTO 0)
|
||||
"
|
||||
st "SIGNAL io : std_logic_vector(ioNb-1 DOWNTO 0)"
|
||||
)
|
||||
)
|
||||
*51 (Wire
|
||||
@ -2351,8 +2337,8 @@ tm "BdCompilerDirectivesTextMgr"
|
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]
|
||||
associable 1
|
||||
)
|
||||
windowSize "-8,-8,1928,1048"
|
||||
viewArea "27426,17402,170102,94921"
|
||||
windowSize "164,195,1039,926"
|
||||
viewArea "49240,25632,103588,71748"
|
||||
cachedDiagramExtent "0,0,138000,93000"
|
||||
pageSetupInfo (PageSetupInfo
|
||||
ptrCmd "\\\\SUN\\PREA309_HPLJ3005DN.PRINTERS.SYSTEM.SION.HEVs,winspool,"
|
||||
@ -2376,7 +2362,7 @@ boundaryWidth 0
|
||||
)
|
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hasePageBreakOrigin 1
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||||
pageBreakOrigin "29000,19000"
|
||||
lastUid 13522,0
|
||||
lastUid 13575,0
|
||||
defaultCommentText (CommentText
|
||||
shape (Rectangle
|
||||
layer 0
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -4149,7 +4149,7 @@ hdsWorkspaceLocation ""
|
||||
relativeLibraryRootDir ""
|
||||
vmLabelLatestDontAskAgain 0
|
||||
vmLabelWorkspaceDontAskAgain 0
|
||||
logWindowGeometry "636x406+308+98"
|
||||
logWindowGeometry "636x514+308+98"
|
||||
diagramBrowserTabNo 0
|
||||
showInsertPortHint 0
|
||||
showContentFirstTime 0
|
||||
@ -6031,6 +6031,96 @@ disableFilters 1
|
||||
]
|
||||
layoutExpression "V(H(A(C(DesignUnits),C(LogicalObjects)),A(C(Files))),A(C(DesignHierarchy)))"
|
||||
)
|
||||
(Viewpoint_v2
|
||||
name "Parse Errors Report"
|
||||
TreeListVPDatas [
|
||||
(TreeListVPData
|
||||
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Loading…
Reference in New Issue
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