add encoding SM --not finish yet

Libs/Memory/hdl/fifo_bram_entity.vhg

@@ -0,0 +1,32 @@
+-- VHDL Entity Memory.FIFO_bram.symbol
+--
+-- Created:
+--          by - francois.francois (Aphelia)
+--          at - 13:45:15 08/28/19
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.all;
+
+ENTITY FIFO_bram IS
+    GENERIC( 
+        dataBitNb : positive := 8;
+        depth     : positive := 8
+    );
+    PORT( 
+        write   : IN     std_ulogic;
+        clock   : IN     std_ulogic;
+        reset   : IN     std_ulogic;
+        dataOut : OUT    std_ulogic_vector (dataBitNb-1 DOWNTO 0);
+        read    : IN     std_ulogic;
+        dataIn  : IN     std_ulogic_vector (dataBitNb-1 DOWNTO 0);
+        empty   : OUT    std_ulogic;
+        full    : OUT    std_ulogic
+    );
+
+-- Declarations
+
+END FIFO_bram ;
+

Libs/Memory/hds/.xrf/fifo_bram_entity.xrf

@@ -0,0 +1,39 @@
+DESIGN @f@i@f@o_bram
+VIEW symbol.sb
+NO_GRAPHIC 0
+DESIGN @f@i@f@o_bram
+VIEW symbol.sb
+GRAPHIC 50,0 8 0 
+DESIGN @f@i@f@o_bram
+VIEW symbol.sb
+GRAPHIC 13,0 13 1 
+DESIGN @f@i@f@o_bram
+VIEW symbol.sb
+GRAPHIC 168,0 18 0 
+DESIGN @f@i@f@o_bram
+VIEW symbol.sb
+GRAPHIC 173,0 19 0 
+DESIGN @f@i@f@o_bram
+VIEW symbol.sb
+GRAPHIC 178,0 20 0 
+DESIGN @f@i@f@o_bram
+VIEW symbol.sb
+GRAPHIC 188,0 21 0 
+DESIGN @f@i@f@o_bram
+VIEW symbol.sb
+GRAPHIC 193,0 22 0 
+DESIGN @f@i@f@o_bram
+VIEW symbol.sb
+GRAPHIC 216,0 23 0 
+DESIGN @f@i@f@o_bram
+VIEW symbol.sb
+GRAPHIC 221,0 24 0 
+DESIGN @f@i@f@o_bram
+VIEW symbol.sb
+GRAPHIC 229,0 25 0 
+DESIGN @f@i@f@o_bram
+VIEW symbol.sb
+GRAPHIC 1,0 28 0 
+DESIGN @f@i@f@o_bram
+VIEW symbol.sb
+GRAPHIC 1,0 29 0 

Libs/RS232/hdl/serialportreceiver_entity.vhg

@@ -0,0 +1,29 @@
+-- VHDL Entity RS232.serialPortReceiver.symbol
+--
+-- Created:
+--          by - francois.francois (Aphelia)
+--          at - 13:45:48 08/28/19
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.all;
+
+ENTITY serialPortReceiver IS
+    GENERIC( 
+        dataBitNb      : positive := 8;
+        baudRateDivide : positive := 2083
+    );
+    PORT( 
+        RxD       : IN     std_ulogic;
+        clock     : IN     std_ulogic;
+        reset     : IN     std_ulogic;
+        dataOut   : OUT    std_ulogic_vector (dataBitNb-1 DOWNTO 0);
+        dataValid : OUT    std_ulogic
+    );
+
+-- Declarations
+
+END serialPortReceiver ;
+

Libs/RS232/hds/.xrf/serialportreceiver_entity.xrf

@@ -0,0 +1,30 @@
+DESIGN serial@port@receiver
+VIEW symbol.sb
+NO_GRAPHIC 0
+DESIGN serial@port@receiver
+VIEW symbol.sb
+GRAPHIC 50,0 8 0 
+DESIGN serial@port@receiver
+VIEW symbol.sb
+GRAPHIC 13,0 13 1 
+DESIGN serial@port@receiver
+VIEW symbol.sb
+GRAPHIC 168,0 18 0 
+DESIGN serial@port@receiver
+VIEW symbol.sb
+GRAPHIC 173,0 19 0 
+DESIGN serial@port@receiver
+VIEW symbol.sb
+GRAPHIC 178,0 20 0 
+DESIGN serial@port@receiver
+VIEW symbol.sb
+GRAPHIC 188,0 21 0 
+DESIGN serial@port@receiver
+VIEW symbol.sb
+GRAPHIC 193,0 22 0 
+DESIGN serial@port@receiver
+VIEW symbol.sb
+GRAPHIC 1,0 25 0 
+DESIGN serial@port@receiver
+VIEW symbol.sb
+GRAPHIC 1,0 26 0