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add encoding SM --not finish yet

This commit is contained in:
2024-04-10 14:22:10 +02:00
parent 7f4a0c615f
commit 8a64f5c04b
62 changed files with 19657 additions and 826 deletions

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-- VHDL Entity RS232.serialPortReceiver.symbol
--
-- Created:
-- by - francois.francois (Aphelia)
-- at - 13:45:48 08/28/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY serialPortReceiver IS
GENERIC(
dataBitNb : positive := 8;
baudRateDivide : positive := 2083
);
PORT(
RxD : IN std_ulogic;
clock : IN std_ulogic;
reset : IN std_ulogic;
dataOut : OUT std_ulogic_vector (dataBitNb-1 DOWNTO 0);
dataValid : OUT std_ulogic
);
-- Declarations
END serialPortReceiver ;