add encoding SM --not finish yet
This commit is contained in:
		
							
								
								
									
										29
									
								
								Libs/RS232/hdl/serialportreceiver_entity.vhg
									
									
									
									
									
										Normal file
									
								
							
							
						
						
									
										29
									
								
								Libs/RS232/hdl/serialportreceiver_entity.vhg
									
									
									
									
									
										Normal file
									
								
							| @@ -0,0 +1,29 @@ | ||||
| -- VHDL Entity RS232.serialPortReceiver.symbol | ||||
| -- | ||||
| -- Created: | ||||
| --          by - francois.francois (Aphelia) | ||||
| --          at - 13:45:48 08/28/19 | ||||
| -- | ||||
| -- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) | ||||
| -- | ||||
| LIBRARY ieee; | ||||
|   USE ieee.std_logic_1164.all; | ||||
|   USE ieee.numeric_std.all; | ||||
|  | ||||
| ENTITY serialPortReceiver IS | ||||
|     GENERIC(  | ||||
|         dataBitNb      : positive := 8; | ||||
|         baudRateDivide : positive := 2083 | ||||
|     ); | ||||
|     PORT(  | ||||
|         RxD       : IN     std_ulogic; | ||||
|         clock     : IN     std_ulogic; | ||||
|         reset     : IN     std_ulogic; | ||||
|         dataOut   : OUT    std_ulogic_vector (dataBitNb-1 DOWNTO 0); | ||||
|         dataValid : OUT    std_ulogic | ||||
|     ); | ||||
|  | ||||
| -- Declarations | ||||
|  | ||||
| END serialPortReceiver ; | ||||
|  | ||||
		Reference in New Issue
	
	Block a user