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add encoding SM --not finish yet

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This commit is contained in:
Rémi Heredero
2024-04-10 14:22:10 +02:00
parent 7f4a0c615f
commit 8a64f5c04b
62 changed files with 19657 additions and 826 deletions
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164
zz-solutions/04-Lissajous/Board/concat/concatenated.vhd
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@@ -1,8 +1,8 @@
-- VHDL Entity Board.lissajousGenerator_circuit_EBS3.symbol
-- VHDL Entity Board.lissajousGenerator_circuit_EBS2.symbol
--
-- Created:
-- by - axel.amand.UNKNOWN (WE7860)
-- at - 17:45:49 01.05.2023
-- by - francois.francois (Aphelia)
-- at - 13:07:18 02/19/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
@@ -10,7 +10,10 @@ LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY lissajousGenerator_circuit_EBS3 IS
ENTITY lissajousGenerator_circuit_EBS2 IS
GENERIC(
bitNb : positive := 16
);
PORT(
clock : IN std_ulogic;
reset_N : IN std_ulogic;
@@ -21,7 +24,7 @@ ENTITY lissajousGenerator_circuit_EBS3 IS
-- Declarations
END lissajousGenerator_circuit_EBS3 ;
END lissajousGenerator_circuit_EBS2 ;
@@ -1340,109 +1343,12 @@ END struct;
-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454
-- Module Version: 5.7
--C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n pll -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00 -type pll -fin 100.00 -fclkop 60 -fclkop_tol 10.0 -fclkos 75 -fclkos_tol 10.0 -phases 0 -fclkos2 50 -fclkos2_tol 10.0 -phases2 0 -fclkos3 10 -fclkos3_tol 10.0 -phases3 0 -phase_cntl STATIC -enable_s -enable_s2 -enable_s3 -pllLocked -fb_mode 1 -fdc C:/temp/clocker/pll/pll.fdc
-- Offers 10MHz, 50MHz, 60MHz and 75MHz clocks
library IEEE;
use IEEE.std_logic_1164.all;
library ECP5U;
use ECP5U.components.all;
ENTITY pll IS
PORT(
clkIn100M : IN std_ulogic;
en75M : IN std_ulogic;
en50M : IN std_ulogic;
en10M : IN std_ulogic;
clk60MHz : OUT std_ulogic;
clk75MHz : OUT std_ulogic;
clk50MHz : OUT std_ulogic;
clk10MHz : OUT std_ulogic;
pllLocked : OUT std_ulogic
);
-- Declarations
END pll ;
architecture rtl of pll is
-- internal signal declarations
signal REFCLK: std_logic;
signal CLKOS3_t: std_logic;
signal CLKOS2_t: std_logic;
signal CLKOS_t: std_logic;
signal CLKOP_t: std_logic;
signal scuba_vhi: std_logic;
signal scuba_vlo: std_logic;
attribute FREQUENCY_PIN_CLKOS3 : string;
attribute FREQUENCY_PIN_CLKOS2 : string;
attribute FREQUENCY_PIN_CLKOS : string;
attribute FREQUENCY_PIN_CLKOP : string;
attribute FREQUENCY_PIN_CLKI : string;
attribute ICP_CURRENT : string;
attribute LPF_RESISTOR : string;
attribute FREQUENCY_PIN_CLKOS3 of PLLInst_0 : label is "10.000000";
attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "50.000000";
attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "75.000000";
attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "60.000000";
attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "100.000000";
attribute ICP_CURRENT of PLLInst_0 : label is "5";
attribute LPF_RESISTOR of PLLInst_0 : label is "16";
attribute syn_keep : boolean;
attribute NGD_DRC_MASK : integer;
attribute NGD_DRC_MASK of rtl : architecture is 1;
begin
-- component instantiation statements
scuba_vhi_inst: VHI
port map (Z=>scuba_vhi);
scuba_vlo_inst: VLO
port map (Z=>scuba_vlo);
PLLInst_0: EHXPLLL
generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED",
STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED",
CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 59, CLKOS2_FPHASE=> 0,
CLKOS2_CPHASE=> 11, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 7,
CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 9, PLL_LOCK_MODE=> 0,
CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING",
CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING",
OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED",
OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "DISABLED",
OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "DISABLED",
OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 60,
CLKOS2_DIV=> 12, CLKOS_DIV=> 8, CLKOP_DIV=> 10, CLKFB_DIV=> 3,
CLKI_DIV=> 5, FEEDBK_PATH=> "CLKOP")
port map (CLKI=>clkIn100M, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo,
PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo,
PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo,
STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo,
ENCLKOP=>scuba_vlo, ENCLKOS=>en75M, ENCLKOS2=>en50M,
ENCLKOS3=>en10M, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t,
CLKOS2=>CLKOS2_t, CLKOS3=>CLKOS3_t, LOCK=>pllLocked,
INTLOCK=>open, REFCLK=>REFCLK, CLKINTFB=>open);
clk10MHz <= CLKOS3_t;
clk50MHz <= CLKOS2_t;
clk75MHz <= CLKOS_t;
clk60MHz <= CLKOP_t;
end rtl;
--
-- VHDL Architecture Board.lissajousGenerator_circuit_EBS3.masterVersion
-- VHDL Architecture Board.lissajousGenerator_circuit_EBS2.masterVersion
--
-- Created:
-- by - axel.amand.UNKNOWN (WE7860)
-- at - 17:45:49 01.05.2023
-- at - 14:46:55 28.04.2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
@@ -1451,10 +1357,9 @@ LIBRARY ieee;
USE ieee.numeric_std.all;
LIBRARY Board;
LIBRARY Lattice;
LIBRARY Lissajous;
ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS3 IS
ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS2 IS
-- Architecture declarations
constant signalBitNb: positive := 16;
@@ -1463,12 +1368,10 @@ ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS3 IS
constant stepY: positive := 4;
-- Internal signal declarations
SIGNAL clkSys : std_ulogic;
SIGNAL logic0 : std_ulogic;
SIGNAL logic1 : std_uLogic;
SIGNAL reset : std_ulogic;
SIGNAL resetSynch : std_ulogic;
SIGNAL resetSynch_N : std_ulogic;
SIGNAL logic1 : std_uLogic;
SIGNAL reset : std_ulogic;
SIGNAL resetSnch_N : std_ulogic;
SIGNAL resetSynch : std_ulogic;
-- Component Declarations
@@ -1486,19 +1389,6 @@ ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS3 IS
out1 : OUT std_uLogic
);
END COMPONENT;
COMPONENT pll
PORT (
clkIn100M : IN std_ulogic ;
en75M : IN std_ulogic ;
en50M : IN std_ulogic ;
en10M : IN std_ulogic ;
clk60MHz : OUT std_ulogic ;
clk75MHz : OUT std_ulogic ;
clk50MHz : OUT std_ulogic ;
clk10MHz : OUT std_ulogic ;
pllLocked : OUT std_ulogic
);
END COMPONENT;
COMPONENT lissajousGenerator
GENERIC (
signalBitNb : positive := 16;
@@ -1520,18 +1410,14 @@ ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS3 IS
FOR ALL : DFF USE ENTITY Board.DFF;
FOR ALL : inverterIn USE ENTITY Board.inverterIn;
FOR ALL : lissajousGenerator USE ENTITY Lissajous.lissajousGenerator;
FOR ALL : pll USE ENTITY Lattice.pll;
-- pragma synthesis_on
BEGIN
-- Architecture concurrent statements
-- HDL Embedded Text Block 5 eb5
-- HDL Embedded Text Block 4 eb4
logic1 <= '1';
-- HDL Embedded Text Block 6 eb6
logic0 <= '0';
-- Instance port mappings.
I_dff : DFF
@@ -1539,7 +1425,7 @@ BEGIN
CLK => clock,
CLR => reset,
D => logic1,
Q => resetSynch_N
Q => resetSnch_N
);
I_inv1 : inverterIn
PORT MAP (
@@ -1548,21 +1434,9 @@ BEGIN
);
I_inv2 : inverterIn
PORT MAP (
in1 => resetSynch_N,
in1 => resetSnch_N,
out1 => resetSynch
);
U_pll : pll
PORT MAP (
clkIn100M => clock,
en75M => logic0,
en50M => logic0,
en10M => logic0,
clk60MHz => clkSys,
clk75MHz => OPEN,
clk50MHz => OPEN,
clk10MHz => OPEN,
pllLocked => OPEN
);
I_main : lissajousGenerator
GENERIC MAP (
signalBitNb => signalBitNb,
@@ -1571,7 +1445,7 @@ BEGIN
stepY => stepY
)
PORT MAP (
clock => clkSys,
clock => clock,
reset => resetSynch,
triggerOut => triggerOut,
xOut => xOut,

164
zz-solutions/04-Lissajous/Board/concat/lissajous.vhd
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@@ -1,8 +1,8 @@
-- VHDL Entity Board.lissajousGenerator_circuit_EBS3.symbol
-- VHDL Entity Board.lissajousGenerator_circuit_EBS2.symbol
--
-- Created:
-- by - axel.amand.UNKNOWN (WE7860)
-- at - 17:45:49 01.05.2023
-- by - francois.francois (Aphelia)
-- at - 13:07:18 02/19/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
@@ -10,7 +10,10 @@ LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY lissajousGenerator_circuit_EBS3 IS
ENTITY lissajousGenerator_circuit_EBS2 IS
GENERIC(
bitNb : positive := 16
);
PORT(
clock : IN std_ulogic;
reset_N : IN std_ulogic;
@@ -21,7 +24,7 @@ ENTITY lissajousGenerator_circuit_EBS3 IS
-- Declarations
END lissajousGenerator_circuit_EBS3 ;
END lissajousGenerator_circuit_EBS2 ;
@@ -1340,109 +1343,12 @@ END struct;
-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454
-- Module Version: 5.7
--C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n pll -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00 -type pll -fin 100.00 -fclkop 60 -fclkop_tol 10.0 -fclkos 75 -fclkos_tol 10.0 -phases 0 -fclkos2 50 -fclkos2_tol 10.0 -phases2 0 -fclkos3 10 -fclkos3_tol 10.0 -phases3 0 -phase_cntl STATIC -enable_s -enable_s2 -enable_s3 -pllLocked -fb_mode 1 -fdc C:/temp/clocker/pll/pll.fdc
-- Offers 10MHz, 50MHz, 60MHz and 75MHz clocks
library IEEE;
use IEEE.std_logic_1164.all;
library ECP5U;
use ECP5U.components.all;
ENTITY pll IS
PORT(
clkIn100M : IN std_ulogic;
en75M : IN std_ulogic;
en50M : IN std_ulogic;
en10M : IN std_ulogic;
clk60MHz : OUT std_ulogic;
clk75MHz : OUT std_ulogic;
clk50MHz : OUT std_ulogic;
clk10MHz : OUT std_ulogic;
pllLocked : OUT std_ulogic
);
-- Declarations
END pll ;
architecture rtl of pll is
-- internal signal declarations
signal REFCLK: std_logic;
signal CLKOS3_t: std_logic;
signal CLKOS2_t: std_logic;
signal CLKOS_t: std_logic;
signal CLKOP_t: std_logic;
signal scuba_vhi: std_logic;
signal scuba_vlo: std_logic;
attribute FREQUENCY_PIN_CLKOS3 : string;
attribute FREQUENCY_PIN_CLKOS2 : string;
attribute FREQUENCY_PIN_CLKOS : string;
attribute FREQUENCY_PIN_CLKOP : string;
attribute FREQUENCY_PIN_CLKI : string;
attribute ICP_CURRENT : string;
attribute LPF_RESISTOR : string;
attribute FREQUENCY_PIN_CLKOS3 of PLLInst_0 : label is "10.000000";
attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "50.000000";
attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "75.000000";
attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "60.000000";
attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "100.000000";
attribute ICP_CURRENT of PLLInst_0 : label is "5";
attribute LPF_RESISTOR of PLLInst_0 : label is "16";
attribute syn_keep : boolean;
attribute NGD_DRC_MASK : integer;
attribute NGD_DRC_MASK of rtl : architecture is 1;
begin
-- component instantiation statements
scuba_vhi_inst: VHI
port map (Z=>scuba_vhi);
scuba_vlo_inst: VLO
port map (Z=>scuba_vlo);
PLLInst_0: EHXPLLL
generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED",
STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED",
CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 59, CLKOS2_FPHASE=> 0,
CLKOS2_CPHASE=> 11, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 7,
CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 9, PLL_LOCK_MODE=> 0,
CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING",
CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING",
OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED",
OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "DISABLED",
OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "DISABLED",
OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 60,
CLKOS2_DIV=> 12, CLKOS_DIV=> 8, CLKOP_DIV=> 10, CLKFB_DIV=> 3,
CLKI_DIV=> 5, FEEDBK_PATH=> "CLKOP")
port map (CLKI=>clkIn100M, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo,
PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo,
PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo,
STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo,
ENCLKOP=>scuba_vlo, ENCLKOS=>en75M, ENCLKOS2=>en50M,
ENCLKOS3=>en10M, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t,
CLKOS2=>CLKOS2_t, CLKOS3=>CLKOS3_t, LOCK=>pllLocked,
INTLOCK=>open, REFCLK=>REFCLK, CLKINTFB=>open);
clk10MHz <= CLKOS3_t;
clk50MHz <= CLKOS2_t;
clk75MHz <= CLKOS_t;
clk60MHz <= CLKOP_t;
end rtl;
--
-- VHDL Architecture Board.lissajousGenerator_circuit_EBS3.masterVersion
-- VHDL Architecture Board.lissajousGenerator_circuit_EBS2.masterVersion
--
-- Created:
-- by - axel.amand.UNKNOWN (WE7860)
-- at - 17:45:49 01.05.2023
-- at - 14:46:55 28.04.2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
@@ -1451,10 +1357,9 @@ LIBRARY ieee;
USE ieee.numeric_std.all;
-- LIBRARY Board;
-- LIBRARY Lattice;
-- LIBRARY Lissajous;
ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS3 IS
ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS2 IS
-- Architecture declarations
constant signalBitNb: positive := 16;
@@ -1463,12 +1368,10 @@ ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS3 IS
constant stepY: positive := 4;
-- Internal signal declarations
SIGNAL clkSys : std_ulogic;
SIGNAL logic0 : std_ulogic;
SIGNAL logic1 : std_uLogic;
SIGNAL reset : std_ulogic;
SIGNAL resetSynch : std_ulogic;
SIGNAL resetSynch_N : std_ulogic;
SIGNAL logic1 : std_uLogic;
SIGNAL reset : std_ulogic;
SIGNAL resetSnch_N : std_ulogic;
SIGNAL resetSynch : std_ulogic;
-- Component Declarations
@@ -1486,19 +1389,6 @@ ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS3 IS
out1 : OUT std_uLogic
);
END COMPONENT;
COMPONENT pll
PORT (
clkIn100M : IN std_ulogic ;
en75M : IN std_ulogic ;
en50M : IN std_ulogic ;
en10M : IN std_ulogic ;
clk60MHz : OUT std_ulogic ;
clk75MHz : OUT std_ulogic ;
clk50MHz : OUT std_ulogic ;
clk10MHz : OUT std_ulogic ;
pllLocked : OUT std_ulogic
);
END COMPONENT;
COMPONENT lissajousGenerator
GENERIC (
signalBitNb : positive := 16;
@@ -1520,18 +1410,14 @@ ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS3 IS
-- FOR ALL : DFF USE ENTITY Board.DFF;
-- FOR ALL : inverterIn USE ENTITY Board.inverterIn;
-- FOR ALL : lissajousGenerator USE ENTITY Lissajous.lissajousGenerator;
-- FOR ALL : pll USE ENTITY Lattice.pll;
-- pragma synthesis_on
BEGIN
-- Architecture concurrent statements
-- HDL Embedded Text Block 5 eb5
-- HDL Embedded Text Block 4 eb4
logic1 <= '1';
-- HDL Embedded Text Block 6 eb6
logic0 <= '0';
-- Instance port mappings.
I_dff : DFF
@@ -1539,7 +1425,7 @@ BEGIN
CLK => clock,
CLR => reset,
D => logic1,
Q => resetSynch_N
Q => resetSnch_N
);
I_inv1 : inverterIn
PORT MAP (
@@ -1548,21 +1434,9 @@ BEGIN
);
I_inv2 : inverterIn
PORT MAP (
in1 => resetSynch_N,
in1 => resetSnch_N,
out1 => resetSynch
);
U_pll : pll
PORT MAP (
clkIn100M => clock,
en75M => logic0,
en50M => logic0,
en10M => logic0,
clk60MHz => clkSys,
clk75MHz => OPEN,
clk50MHz => OPEN,
clk10MHz => OPEN,
pllLocked => OPEN
);
I_main : lissajousGenerator
GENERIC MAP (
signalBitNb => signalBitNb,
@@ -1571,7 +1445,7 @@ BEGIN
stepY => stepY
)
PORT MAP (
clock => clkSys,
clock => clock,
reset => resetSynch,
triggerOut => triggerOut,
xOut => xOut,

23
zz-solutions/04-Lissajous/Board/hdl/dff_entity.vhg Normal file
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@@ -0,0 +1,23 @@
-- VHDL Entity Board.DFF.symbol
--
-- Created:
-- by - francois.francois (Aphelia)
-- at - 13:07:05 02/19/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY DFF IS
PORT(
CLK : IN std_uLogic;
CLR : IN std_uLogic;
D : IN std_uLogic;
Q : OUT std_uLogic
);
-- Declarations
END DFF ;

21
zz-solutions/04-Lissajous/Board/hdl/inverterin_entity.vhg Normal file
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@@ -0,0 +1,21 @@
-- VHDL Entity Board.inverterIn.symbol
--
-- Created:
-- by - francois.francois (Aphelia)
-- at - 13:07:14 02/19/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY inverterIn IS
PORT(
in1 : IN std_uLogic;
out1 : OUT std_uLogic
);
-- Declarations
END inverterIn ;

28
zz-solutions/04-Lissajous/Board/hdl/lissajousgenerator_circuit_ebs2_entity.vhg Normal file
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@@ -0,0 +1,28 @@
-- VHDL Entity Board.lissajousGenerator_circuit_EBS2.symbol
--
-- Created:
-- by - francois.francois (Aphelia)
-- at - 13:07:18 02/19/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY lissajousGenerator_circuit_EBS2 IS
GENERIC(
bitNb : positive := 16
);
PORT(
clock : IN std_ulogic;
reset_N : IN std_ulogic;
triggerOut : OUT std_ulogic;
xOut : OUT std_ulogic;
yOut : OUT std_ulogic
);
-- Declarations
END lissajousGenerator_circuit_EBS2 ;

110
zz-solutions/04-Lissajous/Board/hdl/lissajousgenerator_circuit_ebs2_masterversion.vhg Normal file
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@@ -0,0 +1,110 @@
--
-- VHDL Architecture Board.lissajousGenerator_circuit_EBS2.masterVersion
--
-- Created:
-- by - axel.amand.UNKNOWN (WE7860)
-- at - 14:46:55 28.04.2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY Board;
LIBRARY Lissajous;
ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS2 IS
-- Architecture declarations
constant signalBitNb: positive := 16;
constant phaseBitNb: positive := 17;
constant stepX: positive := 3;
constant stepY: positive := 4;
-- Internal signal declarations
SIGNAL logic1 : std_uLogic;
SIGNAL reset : std_ulogic;
SIGNAL resetSnch_N : std_ulogic;
SIGNAL resetSynch : std_ulogic;
-- Component Declarations
COMPONENT DFF
PORT (
CLK : IN std_uLogic ;
CLR : IN std_uLogic ;
D : IN std_uLogic ;
Q : OUT std_uLogic
);
END COMPONENT;
COMPONENT inverterIn
PORT (
in1 : IN std_uLogic ;
out1 : OUT std_uLogic
);
END COMPONENT;
COMPONENT lissajousGenerator
GENERIC (
signalBitNb : positive := 16;
phaseBitNb : positive := 16;
stepX : positive := 1;
stepY : positive := 1
);
PORT (
clock : IN std_ulogic ;
reset : IN std_ulogic ;
triggerOut : OUT std_ulogic ;
xOut : OUT std_ulogic ;
yOut : OUT std_ulogic
);
END COMPONENT;
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : DFF USE ENTITY Board.DFF;
FOR ALL : inverterIn USE ENTITY Board.inverterIn;
FOR ALL : lissajousGenerator USE ENTITY Lissajous.lissajousGenerator;
-- pragma synthesis_on
BEGIN
-- Architecture concurrent statements
-- HDL Embedded Text Block 4 eb4
logic1 <= '1';
-- Instance port mappings.
I_dff : DFF
PORT MAP (
CLK => clock,
CLR => reset,
D => logic1,
Q => resetSnch_N
);
I_inv1 : inverterIn
PORT MAP (
in1 => reset_N,
out1 => reset
);
I_inv2 : inverterIn
PORT MAP (
in1 => resetSnch_N,
out1 => resetSynch
);
I_main : lissajousGenerator
GENERIC MAP (
signalBitNb => signalBitNb,
phaseBitNb => phaseBitNb,
stepX => stepX,
stepY => stepY
)
PORT MAP (
clock => clock,
reset => resetSynch,
triggerOut => triggerOut,
xOut => xOut,
yOut => yOut
);
END masterVersion;

25
zz-solutions/04-Lissajous/Board/hdl/lissajousgenerator_circuit_ebs3_entity.vhg Normal file
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@@ -0,0 +1,25 @@
-- VHDL Entity Board.lissajousGenerator_circuit_EBS3.symbol
--
-- Created:
-- by - axel.amand.UNKNOWN (WE7860)
-- at - 17:45:49 01.05.2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY lissajousGenerator_circuit_EBS3 IS
PORT(
clock : IN std_ulogic;
reset_N : IN std_ulogic;
triggerOut : OUT std_ulogic;
xOut : OUT std_ulogic;
yOut : OUT std_ulogic
);
-- Declarations
END lissajousGenerator_circuit_EBS3 ;

142
zz-solutions/04-Lissajous/Board/hdl/lissajousgenerator_circuit_ebs3_masterversion.vhg Normal file
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--
-- VHDL Architecture Board.lissajousGenerator_circuit_EBS3.masterVersion
--
-- Created:
-- by - axel.amand.UNKNOWN (WE7860)
-- at - 17:45:49 01.05.2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY Board;
LIBRARY Lattice;
LIBRARY Lissajous;
ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS3 IS
-- Architecture declarations
constant signalBitNb: positive := 16;
constant phaseBitNb: positive := 17;
constant stepX: positive := 3;
constant stepY: positive := 4;
-- Internal signal declarations
SIGNAL clkSys : std_ulogic;
SIGNAL logic0 : std_ulogic;
SIGNAL logic1 : std_uLogic;
SIGNAL reset : std_ulogic;
SIGNAL resetSynch : std_ulogic;
SIGNAL resetSynch_N : std_ulogic;
-- Component Declarations
COMPONENT DFF
PORT (
CLK : IN std_uLogic ;
CLR : IN std_uLogic ;
D : IN std_uLogic ;
Q : OUT std_uLogic
);
END COMPONENT;
COMPONENT inverterIn
PORT (
in1 : IN std_uLogic ;
out1 : OUT std_uLogic
);
END COMPONENT;
COMPONENT pll
PORT (
clkIn100M : IN std_ulogic;
en10M : IN std_ulogic;
en50M : IN std_ulogic;
en75M : IN std_ulogic;
clk10MHz : OUT std_ulogic;
clk50MHz : OUT std_ulogic;
clk60MHz : OUT std_ulogic;
clk75MHz : OUT std_ulogic;
pllLocked : OUT std_ulogic
);
END COMPONENT;
COMPONENT lissajousGenerator
GENERIC (
signalBitNb : positive := 16;
phaseBitNb : positive := 16;
stepX : positive := 1;
stepY : positive := 1
);
PORT (
clock : IN std_ulogic ;
reset : IN std_ulogic ;
triggerOut : OUT std_ulogic ;
xOut : OUT std_ulogic ;
yOut : OUT std_ulogic
);
END COMPONENT;
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : DFF USE ENTITY Board.DFF;
FOR ALL : inverterIn USE ENTITY Board.inverterIn;
FOR ALL : lissajousGenerator USE ENTITY Lissajous.lissajousGenerator;
FOR ALL : pll USE ENTITY Lattice.pll;
-- pragma synthesis_on
BEGIN
-- Architecture concurrent statements
-- HDL Embedded Text Block 5 eb5
logic1 <= '1';
-- HDL Embedded Text Block 6 eb6
logic0 <= '0';
-- Instance port mappings.
I_dff : DFF
PORT MAP (
CLK => clock,
CLR => reset,
D => logic1,
Q => resetSynch_N
);
I_inv1 : inverterIn
PORT MAP (
in1 => reset_N,
out1 => reset
);
I_inv2 : inverterIn
PORT MAP (
in1 => resetSynch_N,
out1 => resetSynch
);
U_pll : pll
PORT MAP (
clkIn100M => clock,
en75M => logic0,
en50M => logic0,
en10M => logic0,
clk60MHz => clkSys,
clk75MHz => OPEN,
clk50MHz => OPEN,
clk10MHz => OPEN,
pllLocked => OPEN
);
I_main : lissajousGenerator
GENERIC MAP (
signalBitNb => signalBitNb,
phaseBitNb => phaseBitNb,
stepX => stepX,
stepY => stepY
)
PORT MAP (
clock => clkSys,
reset => resetSynch,
triggerOut => triggerOut,
xOut => xOut,
yOut => yOut
);
END masterVersion;

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zz-solutions/04-Lissajous/Board/hds/.cache.dat Normal file
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zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_lissajousgenerator_circuit_ebs2_entity.vhg._fpf Normal file
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DIALECT atom VHDL_2008

1
zz-solutions/04-Lissajous/Board/hds/.hdlsidedata/_lissajousgenerator_circuit_ebs2_masterversion.vhg._fpf Normal file
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DIALECT atom VHDL_2008

24
zz-solutions/04-Lissajous/Board/hds/.xrf/dff_entity.xrf Normal file
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DESIGN @d@f@f
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DESIGN @d@f@f
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DESIGN @d@f@f
VIEW symbol.sb
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DESIGN @d@f@f
VIEW symbol.sb
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DESIGN @d@f@f
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DESIGN @d@f@f
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DESIGN @d@f@f
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DESIGN @d@f@f
VIEW symbol.sb
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18
zz-solutions/04-Lissajous/Board/hds/.xrf/inverterin_entity.xrf Normal file
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@@ -0,0 +1,18 @@
DESIGN inverter@in
VIEW symbol.sb
NO_GRAPHIC 0
DESIGN inverter@in
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DESIGN inverter@in
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DESIGN inverter@in
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DESIGN inverter@in
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DESIGN inverter@in
VIEW symbol.sb
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30
zz-solutions/04-Lissajous/Board/hds/.xrf/lissajousgenerator_circuit_ebs2_entity.xrf Normal file
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@@ -0,0 +1,30 @@
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DESIGN lissajous@generator_circuit_@e@b@s2
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DESIGN lissajous@generator_circuit_@e@b@s2
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DESIGN lissajous@generator_circuit_@e@b@s2
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DESIGN lissajous@generator_circuit_@e@b@s2
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DESIGN lissajous@generator_circuit_@e@b@s2
VIEW symbol.sb
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DESIGN lissajous@generator_circuit_@e@b@s2
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DESIGN lissajous@generator_circuit_@e@b@s2
VIEW symbol.sb
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165
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DESIGN lissajous@generator_circuit_@e@b@s2
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DESIGN lissajous@generator_circuit_@e@b@s2
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DESIGN lissajous@generator_circuit_@e@b@s2
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DESIGN lissajous@generator_circuit_@e@b@s2
VIEW master@version.bd
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DESIGN lissajous@generator_circuit_@e@b@s2
VIEW master@version.bd
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DESIGN lissajous@generator_circuit_@e@b@s2
VIEW master@version.bd
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LIBRARY Board
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DESIGN @d@f@f
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DESIGN @d@f@f
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DESIGN lissajous@generator_circuit_@e@b@s2
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LIBRARY Lissajous
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DESIGN lissajous@generator
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DESIGN lissajous@generator
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DESIGN lissajous@generator
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DESIGN lissajous@generator
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LIBRARY Board
DESIGN lissajous@generator_circuit_@e@b@s2
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DESIGN lissajous@generator_circuit_@e@b@s2
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DESIGN lissajous@generator_circuit_@e@b@s2
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DESIGN lissajous@generator_circuit_@e@b@s2
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DESIGN lissajous@generator_circuit_@e@b@s2
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DESIGN lissajous@generator_circuit_@e@b@s2
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DESIGN lissajous@generator_circuit_@e@b@s2
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27
zz-solutions/04-Lissajous/Board/hds/.xrf/lissajousgenerator_circuit_ebs3_entity.xrf Normal file
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@@ -0,0 +1,27 @@
DESIGN lissajous@generator_circuit_@e@b@s3
VIEW symbol.sb
NO_GRAPHIC 0
DESIGN lissajous@generator_circuit_@e@b@s3
VIEW symbol.sb
GRAPHIC 50,0 8 0
DESIGN lissajous@generator_circuit_@e@b@s3
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DESIGN lissajous@generator_circuit_@e@b@s3
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DESIGN lissajous@generator_circuit_@e@b@s3
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DESIGN lissajous@generator_circuit_@e@b@s3
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DESIGN lissajous@generator_circuit_@e@b@s3
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DESIGN lissajous@generator_circuit_@e@b@s3
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DESIGN lissajous@generator_circuit_@e@b@s3
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205
zz-solutions/04-Lissajous/Board/hds/.xrf/lissajousgenerator_circuit_ebs3_masterversion.xrf Normal file
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@@ -0,0 +1,205 @@
DESIGN lissajous@generator_circuit_@e@b@s3
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LIBRARY Board
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DESIGN lissajous@generator_circuit_@e@b@s3
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DESIGN lissajous@generator
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DESIGN lissajous@generator
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DESIGN lissajous@generator
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LIBRARY Board
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VIEW master@version.bd
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DESIGN lissajous@generator_circuit_@e@b@s3
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DESIGN lissajous@generator_circuit_@e@b@s3
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DESIGN lissajous@generator_circuit_@e@b@s3
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DESIGN lissajous@generator_circuit_@e@b@s3
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