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-- VHDL Entity Lissajous.lissajousGenerator.symbol
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--
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-- Created:
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-- by - francois.francois (Aphelia)
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-- at - 13:07:53 02/19/19
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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ENTITY lissajousGenerator IS
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GENERIC(
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signalBitNb : positive := 16;
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phaseBitNb : positive := 16;
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stepX : positive := 1;
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stepY : positive := 1
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);
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PORT(
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clock : IN std_ulogic;
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reset : IN std_ulogic;
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triggerOut : OUT std_ulogic;
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xOut : OUT std_ulogic;
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yOut : OUT std_ulogic
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);
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-- Declarations
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END lissajousGenerator ;
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--
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-- VHDL Architecture Lissajous.lissajousGenerator.struct
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--
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-- Created:
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-- by - axel.amand.UNKNOWN (WE7860)
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-- at - 14:47:09 28.04.2023
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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LIBRARY DigitalToAnalogConverter;
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LIBRARY SplineInterpolator;
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ARCHITECTURE struct OF lissajousGenerator IS
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-- Architecture declarations
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-- Internal signal declarations
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SIGNAL sineX : unsigned(signalBitNb-1 DOWNTO 0);
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SIGNAL sineY : unsigned(signalBitNb-1 DOWNTO 0);
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SIGNAL squareY : unsigned(signalBitNb-1 DOWNTO 0);
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SIGNAL stepXUnsigned : unsigned(phaseBitNb-1 DOWNTO 0);
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SIGNAL stepYUnsigned : unsigned(phaseBitNb-1 DOWNTO 0);
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-- Component Declarations
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COMPONENT DAC
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GENERIC (
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signalBitNb : positive := 16
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);
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PORT (
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serialOut : OUT std_ulogic ;
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parallelIn : IN unsigned (signalBitNb-1 DOWNTO 0);
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clock : IN std_ulogic ;
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reset : IN std_ulogic
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);
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END COMPONENT;
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COMPONENT sineGen
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GENERIC (
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signalBitNb : positive := 16;
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phaseBitNb : positive := 10
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);
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PORT (
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clock : IN std_ulogic ;
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reset : IN std_ulogic ;
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step : IN unsigned (phaseBitNb-1 DOWNTO 0);
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sawtooth : OUT unsigned (signalBitNb-1 DOWNTO 0);
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sine : OUT unsigned (signalBitNb-1 DOWNTO 0);
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square : OUT unsigned (signalBitNb-1 DOWNTO 0);
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triangle : OUT unsigned (signalBitNb-1 DOWNTO 0)
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);
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END COMPONENT;
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-- Optional embedded configurations
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-- pragma synthesis_off
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FOR ALL : DAC USE ENTITY DigitalToAnalogConverter.DAC;
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FOR ALL : sineGen USE ENTITY SplineInterpolator.sineGen;
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-- pragma synthesis_on
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BEGIN
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-- Architecture concurrent statements
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-- HDL Embedded Text Block 1 eb1
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triggerOut <= squareY(squareY'high);
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-- HDL Embedded Text Block 2 eb2
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stepXUnsigned <= to_unsigned(stepX, stepXUnsigned'length);
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-- HDL Embedded Text Block 3 eb3
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stepYUnsigned <= to_unsigned(stepY, stepYUnsigned'length);
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-- Instance port mappings.
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I_dacX : DAC
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GENERIC MAP (
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signalBitNb => signalBitNb
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)
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PORT MAP (
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serialOut => xOut,
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parallelIn => sineX,
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clock => clock,
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reset => reset
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);
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I_dacY : DAC
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GENERIC MAP (
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signalBitNb => signalBitNb
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)
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PORT MAP (
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serialOut => yOut,
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parallelIn => sineY,
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clock => clock,
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reset => reset
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);
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I_sinX : sineGen
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GENERIC MAP (
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signalBitNb => signalBitNb,
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phaseBitNb => phaseBitNb
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)
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PORT MAP (
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clock => clock,
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reset => reset,
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step => stepXUnsigned,
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sawtooth => OPEN,
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sine => sineX,
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square => OPEN,
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triangle => OPEN
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);
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I_sinY : sineGen
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GENERIC MAP (
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signalBitNb => signalBitNb,
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phaseBitNb => phaseBitNb
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)
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PORT MAP (
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clock => clock,
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reset => reset,
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step => stepYUnsigned,
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sawtooth => OPEN,
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sine => sineY,
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square => squareY,
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triangle => OPEN
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);
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END struct;
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BIN
zz-solutions/04-Lissajous/Lissajous/hds/.cache.dat
Normal file
BIN
zz-solutions/04-Lissajous/Lissajous/hds/.cache.dat
Normal file
Binary file not shown.
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DESIGN lissajous@generator
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VIEW symbol.sb
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NO_GRAPHIC 0
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DESIGN lissajous@generator
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VIEW symbol.sb
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GRAPHIC 50,0 8 0
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DESIGN lissajous@generator
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VIEW symbol.sb
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GRAPHIC 13,0 13 1
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DESIGN lissajous@generator
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VIEW symbol.sb
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GRAPHIC 52,0 20 0
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DESIGN lissajous@generator
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VIEW symbol.sb
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GRAPHIC 428,0 21 0
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DESIGN lissajous@generator
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VIEW symbol.sb
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GRAPHIC 88,0 22 0
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DESIGN lissajous@generator
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VIEW symbol.sb
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GRAPHIC 93,0 23 0
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DESIGN lissajous@generator
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VIEW symbol.sb
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GRAPHIC 98,0 24 0
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DESIGN lissajous@generator
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VIEW symbol.sb
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GRAPHIC 1,0 27 0
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DESIGN lissajous@generator
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VIEW symbol.sb
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GRAPHIC 1,0 28 0
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DESIGN lissajous@generator
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VIEW struct.bd
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NO_GRAPHIC 0
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DESIGN lissajous@generator
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VIEW struct.bd
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GRAPHIC 84,0 9 0
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DESIGN lissajous@generator
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VIEW struct.bd
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NO_GRAPHIC 12
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DESIGN lissajous@generator
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VIEW struct.bd
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GRAPHIC 0,0 16 2
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DESIGN lissajous@generator
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VIEW struct.bd
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GRAPHIC 617,0 21 0
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DESIGN lissajous@generator
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VIEW struct.bd
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GRAPHIC 1631,0 22 0
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DESIGN lissajous@generator
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VIEW struct.bd
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GRAPHIC 1652,0 23 0
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DESIGN lissajous@generator
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VIEW struct.bd
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GRAPHIC 2512,0 24 0
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DESIGN lissajous@generator
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VIEW struct.bd
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GRAPHIC 2510,0 25 0
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DESIGN lissajous@generator
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VIEW struct.bd
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NO_GRAPHIC 26
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DESIGN lissajous@generator
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VIEW struct.bd
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NO_GRAPHIC 27
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LIBRARY DigitalToAnalogConverter
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DESIGN @d@a@c
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VIEW master@version
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GRAPHIC 2187,0 29 0
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DESIGN @d@a@c
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VIEW symbol.sb
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GRAPHIC 14,0 30 1
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DESIGN @d@a@c
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VIEW symbol.sb
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GRAPHIC 67,0 34 0
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DESIGN @d@a@c
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VIEW symbol.sb
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GRAPHIC 57,0 35 0
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DESIGN @d@a@c
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VIEW symbol.sb
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GRAPHIC 52,0 36 0
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DESIGN @d@a@c
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VIEW symbol.sb
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GRAPHIC 76,0 37 0
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LIBRARY SplineInterpolator
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DESIGN sine@gen
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VIEW struct
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GRAPHIC 2090,0 40 0
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DESIGN sine@gen
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VIEW symbol.sb
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GRAPHIC 14,0 41 1
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DESIGN sine@gen
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VIEW symbol.sb
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GRAPHIC 52,0 46 0
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DESIGN sine@gen
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VIEW symbol.sb
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GRAPHIC 88,0 47 0
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DESIGN sine@gen
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VIEW symbol.sb
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GRAPHIC 128,0 48 0
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DESIGN sine@gen
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VIEW symbol.sb
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GRAPHIC 98,0 49 0
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DESIGN sine@gen
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VIEW symbol.sb
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GRAPHIC 103,0 50 0
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DESIGN sine@gen
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VIEW symbol.sb
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GRAPHIC 108,0 51 0
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DESIGN sine@gen
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VIEW symbol.sb
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GRAPHIC 118,0 52 0
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LIBRARY Lissajous
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DESIGN lissajous@generator
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VIEW struct.bd
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NO_GRAPHIC 55
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DESIGN lissajous@generator
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VIEW struct.bd
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GRAPHIC 2187,0 58 0
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DESIGN lissajous@generator
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GRAPHIC 2090,0 59 0
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DESIGN lissajous@generator
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VIEW struct.bd
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NO_GRAPHIC 62
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DESIGN lissajous@generator
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GRAPHIC 443,0 65 0
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DESIGN lissajous@generator
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VIEW struct.bd
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NO_GRAPHIC 67
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DESIGN lissajous@generator
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GRAPHIC 1324,0 68 0
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DESIGN lissajous@generator
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VIEW struct.bd
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NO_GRAPHIC 70
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GRAPHIC 1637,0 71 0
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VIEW struct.bd
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NO_GRAPHIC 74
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DESIGN lissajous@generator
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VIEW struct.bd
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GRAPHIC 2187,0 76 0
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DESIGN lissajous@generator
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VIEW struct.bd
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GRAPHIC 2194,0 77 1
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DESIGN lissajous@generator
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GRAPHIC 575,0 81 0
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GRAPHIC 579,0 82 0
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DESIGN lissajous@generator
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GRAPHIC 583,0 83 0
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DESIGN lissajous@generator
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VIEW struct.bd
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GRAPHIC 589,0 84 0
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DESIGN lissajous@generator
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VIEW struct.bd
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GRAPHIC 2162,0 86 0
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DESIGN lissajous@generator
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VIEW struct.bd
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GRAPHIC 2169,0 87 1
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DESIGN lissajous@generator
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VIEW struct.bd
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GRAPHIC 29,0 91 0
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DESIGN lissajous@generator
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VIEW struct.bd
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GRAPHIC 1613,0 92 0
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DESIGN lissajous@generator
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VIEW struct.bd
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GRAPHIC 1617,0 93 0
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DESIGN lissajous@generator
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VIEW struct.bd
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GRAPHIC 1623,0 94 0
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DESIGN lissajous@generator
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VIEW struct.bd
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GRAPHIC 2090,0 96 0
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DESIGN lissajous@generator
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VIEW struct.bd
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GRAPHIC 2097,0 97 1
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VIEW struct.bd
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GRAPHIC 2349,0 102 0
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DESIGN lissajous@generator
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VIEW struct.bd
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GRAPHIC 2341,0 103 0
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DESIGN lissajous@generator
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VIEW struct.bd
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GRAPHIC 1335,0 104 0
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DESIGN lissajous@generator
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VIEW struct.bd
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GRAPHIC 579,0 106 0
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DESIGN lissajous@generator
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VIEW struct.bd
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GRAPHIC 2053,0 110 0
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DESIGN lissajous@generator
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VIEW struct.bd
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GRAPHIC 2060,0 111 1
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DESIGN lissajous@generator
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VIEW struct.bd
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GRAPHIC 15,0 116 0
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DESIGN lissajous@generator
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VIEW struct.bd
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GRAPHIC 2357,0 117 0
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DESIGN lissajous@generator
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VIEW struct.bd
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GRAPHIC 1341,0 118 0
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DESIGN lissajous@generator
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VIEW struct.bd
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GRAPHIC 1613,0 120 0
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DESIGN lissajous@generator
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VIEW struct.bd
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GRAPHIC 450,0 121 0
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DESIGN lissajous@generator
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VIEW struct.bd
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NO_GRAPHIC 125
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