add encoding SM --not finish yet
This commit is contained in:
@@ -0,0 +1,31 @@
|
||||
-- VHDL Entity Lissajous.lissajousGenerator.symbol
|
||||
--
|
||||
-- Created:
|
||||
-- by - francois.francois (Aphelia)
|
||||
-- at - 13:07:53 02/19/19
|
||||
--
|
||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.numeric_std.all;
|
||||
|
||||
ENTITY lissajousGenerator IS
|
||||
GENERIC(
|
||||
signalBitNb : positive := 16;
|
||||
phaseBitNb : positive := 16;
|
||||
stepX : positive := 1;
|
||||
stepY : positive := 1
|
||||
);
|
||||
PORT(
|
||||
clock : IN std_ulogic;
|
||||
reset : IN std_ulogic;
|
||||
triggerOut : OUT std_ulogic;
|
||||
xOut : OUT std_ulogic;
|
||||
yOut : OUT std_ulogic
|
||||
);
|
||||
|
||||
-- Declarations
|
||||
|
||||
END lissajousGenerator ;
|
||||
|
||||
@@ -0,0 +1,126 @@
|
||||
--
|
||||
-- VHDL Architecture Lissajous.lissajousGenerator.struct
|
||||
--
|
||||
-- Created:
|
||||
-- by - axel.amand.UNKNOWN (WE7860)
|
||||
-- at - 14:47:09 28.04.2023
|
||||
--
|
||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.numeric_std.all;
|
||||
|
||||
LIBRARY DigitalToAnalogConverter;
|
||||
LIBRARY SplineInterpolator;
|
||||
|
||||
ARCHITECTURE struct OF lissajousGenerator IS
|
||||
|
||||
-- Architecture declarations
|
||||
|
||||
-- Internal signal declarations
|
||||
SIGNAL sineX : unsigned(signalBitNb-1 DOWNTO 0);
|
||||
SIGNAL sineY : unsigned(signalBitNb-1 DOWNTO 0);
|
||||
SIGNAL squareY : unsigned(signalBitNb-1 DOWNTO 0);
|
||||
SIGNAL stepXUnsigned : unsigned(phaseBitNb-1 DOWNTO 0);
|
||||
SIGNAL stepYUnsigned : unsigned(phaseBitNb-1 DOWNTO 0);
|
||||
|
||||
|
||||
-- Component Declarations
|
||||
COMPONENT DAC
|
||||
GENERIC (
|
||||
signalBitNb : positive := 16
|
||||
);
|
||||
PORT (
|
||||
serialOut : OUT std_ulogic ;
|
||||
parallelIn : IN unsigned (signalBitNb-1 DOWNTO 0);
|
||||
clock : IN std_ulogic ;
|
||||
reset : IN std_ulogic
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT sineGen
|
||||
GENERIC (
|
||||
signalBitNb : positive := 16;
|
||||
phaseBitNb : positive := 10
|
||||
);
|
||||
PORT (
|
||||
clock : IN std_ulogic ;
|
||||
reset : IN std_ulogic ;
|
||||
step : IN unsigned (phaseBitNb-1 DOWNTO 0);
|
||||
sawtooth : OUT unsigned (signalBitNb-1 DOWNTO 0);
|
||||
sine : OUT unsigned (signalBitNb-1 DOWNTO 0);
|
||||
square : OUT unsigned (signalBitNb-1 DOWNTO 0);
|
||||
triangle : OUT unsigned (signalBitNb-1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
-- Optional embedded configurations
|
||||
-- pragma synthesis_off
|
||||
FOR ALL : DAC USE ENTITY DigitalToAnalogConverter.DAC;
|
||||
FOR ALL : sineGen USE ENTITY SplineInterpolator.sineGen;
|
||||
-- pragma synthesis_on
|
||||
|
||||
|
||||
BEGIN
|
||||
-- Architecture concurrent statements
|
||||
-- HDL Embedded Text Block 1 eb1
|
||||
triggerOut <= squareY(squareY'high);
|
||||
|
||||
-- HDL Embedded Text Block 2 eb2
|
||||
stepXUnsigned <= to_unsigned(stepX, stepXUnsigned'length);
|
||||
|
||||
-- HDL Embedded Text Block 3 eb3
|
||||
stepYUnsigned <= to_unsigned(stepY, stepYUnsigned'length);
|
||||
|
||||
|
||||
-- Instance port mappings.
|
||||
I_dacX : DAC
|
||||
GENERIC MAP (
|
||||
signalBitNb => signalBitNb
|
||||
)
|
||||
PORT MAP (
|
||||
serialOut => xOut,
|
||||
parallelIn => sineX,
|
||||
clock => clock,
|
||||
reset => reset
|
||||
);
|
||||
I_dacY : DAC
|
||||
GENERIC MAP (
|
||||
signalBitNb => signalBitNb
|
||||
)
|
||||
PORT MAP (
|
||||
serialOut => yOut,
|
||||
parallelIn => sineY,
|
||||
clock => clock,
|
||||
reset => reset
|
||||
);
|
||||
I_sinX : sineGen
|
||||
GENERIC MAP (
|
||||
signalBitNb => signalBitNb,
|
||||
phaseBitNb => phaseBitNb
|
||||
)
|
||||
PORT MAP (
|
||||
clock => clock,
|
||||
reset => reset,
|
||||
step => stepXUnsigned,
|
||||
sawtooth => OPEN,
|
||||
sine => sineX,
|
||||
square => OPEN,
|
||||
triangle => OPEN
|
||||
);
|
||||
I_sinY : sineGen
|
||||
GENERIC MAP (
|
||||
signalBitNb => signalBitNb,
|
||||
phaseBitNb => phaseBitNb
|
||||
)
|
||||
PORT MAP (
|
||||
clock => clock,
|
||||
reset => reset,
|
||||
step => stepYUnsigned,
|
||||
sawtooth => OPEN,
|
||||
sine => sineY,
|
||||
square => squareY,
|
||||
triangle => OPEN
|
||||
);
|
||||
|
||||
END struct;
|
||||
BIN
zz-solutions/04-Lissajous/Lissajous/hds/.cache.dat
Normal file
BIN
zz-solutions/04-Lissajous/Lissajous/hds/.cache.dat
Normal file
Binary file not shown.
@@ -0,0 +1,30 @@
|
||||
DESIGN lissajous@generator
|
||||
VIEW symbol.sb
|
||||
NO_GRAPHIC 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 50,0 8 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 13,0 13 1
|
||||
DESIGN lissajous@generator
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 52,0 20 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 428,0 21 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 88,0 22 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 93,0 23 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 98,0 24 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 27 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 28 0
|
||||
@@ -0,0 +1,192 @@
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 84,0 9 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 12
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 0,0 16 2
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 617,0 21 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1631,0 22 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1652,0 23 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2512,0 24 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2510,0 25 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 26
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 27
|
||||
LIBRARY DigitalToAnalogConverter
|
||||
DESIGN @d@a@c
|
||||
VIEW master@version
|
||||
GRAPHIC 2187,0 29 0
|
||||
DESIGN @d@a@c
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 14,0 30 1
|
||||
DESIGN @d@a@c
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 67,0 34 0
|
||||
DESIGN @d@a@c
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 57,0 35 0
|
||||
DESIGN @d@a@c
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 52,0 36 0
|
||||
DESIGN @d@a@c
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 76,0 37 0
|
||||
LIBRARY SplineInterpolator
|
||||
DESIGN sine@gen
|
||||
VIEW struct
|
||||
GRAPHIC 2090,0 40 0
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 14,0 41 1
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 52,0 46 0
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 88,0 47 0
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 128,0 48 0
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 98,0 49 0
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 103,0 50 0
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 108,0 51 0
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 118,0 52 0
|
||||
LIBRARY Lissajous
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 55
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2187,0 58 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2090,0 59 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 62
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 443,0 65 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 67
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1324,0 68 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 70
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1637,0 71 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 73
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 74
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2187,0 76 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2194,0 77 1
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 575,0 81 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 579,0 82 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 583,0 83 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 589,0 84 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2162,0 86 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2169,0 87 1
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 29,0 91 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1613,0 92 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1617,0 93 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1623,0 94 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2090,0 96 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2097,0 97 1
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2349,0 102 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2341,0 103 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1335,0 104 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 579,0 106 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2053,0 110 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2060,0 111 1
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 15,0 116 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2357,0 117 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1341,0 118 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1613,0 120 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
GRAPHIC 450,0 121 0
|
||||
DESIGN lissajous@generator
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 125
|
||||
Reference in New Issue
Block a user