add encoding SM --not finish yet

zz-solutions/04-Lissajous/Lissajous/hdl/lissajousgenerator_entity.vhg

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+-- VHDL Entity Lissajous.lissajousGenerator.symbol
+--
+-- Created:
+--          by - francois.francois (Aphelia)
+--          at - 13:07:53 02/19/19
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.all;
+
+ENTITY lissajousGenerator IS
+    GENERIC( 
+        signalBitNb : positive := 16;
+        phaseBitNb  : positive := 16;
+        stepX       : positive := 1;
+        stepY       : positive := 1
+    );
+    PORT( 
+        clock      : IN     std_ulogic;
+        reset      : IN     std_ulogic;
+        triggerOut : OUT    std_ulogic;
+        xOut       : OUT    std_ulogic;
+        yOut       : OUT    std_ulogic
+    );
+
+-- Declarations
+
+END lissajousGenerator ;
+

zz-solutions/04-Lissajous/Lissajous/hdl/lissajousgenerator_struct.vhg

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+--
+-- VHDL Architecture Lissajous.lissajousGenerator.struct
+--
+-- Created:
+--          by - axel.amand.UNKNOWN (WE7860)
+--          at - 14:47:09 28.04.2023
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.all;
+
+LIBRARY DigitalToAnalogConverter;
+LIBRARY SplineInterpolator;
+
+ARCHITECTURE struct OF lissajousGenerator IS
+
+    -- Architecture declarations
+
+    -- Internal signal declarations
+    SIGNAL sineX         : unsigned(signalBitNb-1 DOWNTO 0);
+    SIGNAL sineY         : unsigned(signalBitNb-1 DOWNTO 0);
+    SIGNAL squareY       : unsigned(signalBitNb-1 DOWNTO 0);
+    SIGNAL stepXUnsigned : unsigned(phaseBitNb-1 DOWNTO 0);
+    SIGNAL stepYUnsigned : unsigned(phaseBitNb-1 DOWNTO 0);
+
+
+    -- Component Declarations
+    COMPONENT DAC
+    GENERIC (
+        signalBitNb : positive := 16
+    );
+    PORT (
+        serialOut  : OUT    std_ulogic ;
+        parallelIn : IN     unsigned (signalBitNb-1 DOWNTO 0);
+        clock      : IN     std_ulogic ;
+        reset      : IN     std_ulogic 
+    );
+    END COMPONENT;
+    COMPONENT sineGen
+    GENERIC (
+        signalBitNb : positive := 16;
+        phaseBitNb  : positive := 10
+    );
+    PORT (
+        clock    : IN     std_ulogic ;
+        reset    : IN     std_ulogic ;
+        step     : IN     unsigned (phaseBitNb-1 DOWNTO 0);
+        sawtooth : OUT    unsigned (signalBitNb-1 DOWNTO 0);
+        sine     : OUT    unsigned (signalBitNb-1 DOWNTO 0);
+        square   : OUT    unsigned (signalBitNb-1 DOWNTO 0);
+        triangle : OUT    unsigned (signalBitNb-1 DOWNTO 0)
+    );
+    END COMPONENT;
+
+    -- Optional embedded configurations
+    -- pragma synthesis_off
+    FOR ALL : DAC USE ENTITY DigitalToAnalogConverter.DAC;
+    FOR ALL : sineGen USE ENTITY SplineInterpolator.sineGen;
+    -- pragma synthesis_on
+
+
+BEGIN
+    -- Architecture concurrent statements
+    -- HDL Embedded Text Block 1 eb1
+    triggerOut <= squareY(squareY'high);
+
+    -- HDL Embedded Text Block 2 eb2
+    stepXUnsigned <= to_unsigned(stepX, stepXUnsigned'length);
+
+    -- HDL Embedded Text Block 3 eb3
+    stepYUnsigned <= to_unsigned(stepY, stepYUnsigned'length);
+
+
+    -- Instance port mappings.
+    I_dacX : DAC
+        GENERIC MAP (
+            signalBitNb => signalBitNb
+        )
+        PORT MAP (
+            serialOut  => xOut,
+            parallelIn => sineX,
+            clock      => clock,
+            reset      => reset
+        );
+    I_dacY : DAC
+        GENERIC MAP (
+            signalBitNb => signalBitNb
+        )
+        PORT MAP (
+            serialOut  => yOut,
+            parallelIn => sineY,
+            clock      => clock,
+            reset      => reset
+        );
+    I_sinX : sineGen
+        GENERIC MAP (
+            signalBitNb => signalBitNb,
+            phaseBitNb  => phaseBitNb
+        )
+        PORT MAP (
+            clock    => clock,
+            reset    => reset,
+            step     => stepXUnsigned,
+            sawtooth => OPEN,
+            sine     => sineX,
+            square   => OPEN,
+            triangle => OPEN
+        );
+    I_sinY : sineGen
+        GENERIC MAP (
+            signalBitNb => signalBitNb,
+            phaseBitNb  => phaseBitNb
+        )
+        PORT MAP (
+            clock    => clock,
+            reset    => reset,
+            step     => stepYUnsigned,
+            sawtooth => OPEN,
+            sine     => sineY,
+            square   => squareY,
+            triangle => OPEN
+        );
+
+END struct;