add solutions

zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hdl/waveformGen_tester_test.vhd

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+ARCHITECTURE test OF waveformGen_tester IS
+
+  constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
+  signal sClock: std_uLogic := '1';
+
+begin
+  ------------------------------------------------------------------------------
+                                                              -- clock and reset
+  sClock <= not sClock after clockPeriod/2;
+  clock <= transport sClock after clockPeriod*9/10;
+  reset <= '1', '0' after 2*clockPeriod;
+
+  ------------------------------------------------------------------------------
+                                                                       -- enable
+  en <= '0', '1' after 100 us;
+
+  ------------------------------------------------------------------------------
+                                                            -- frequency control
+  step <= to_unsigned(2**(step'length-13), step'length);
+
+END ARCHITECTURE test;
+

zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hdl/waveformgen_tb_entity.vhg

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+-- VHDL Entity WaveformGenerator_test.waveformGen_tb.symbol
+--
+-- Created:
+--          by - francois.corthay.UNKNOWN (WEA30906)
+--          at - 14:48:16 25.02.2019
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+
+
+ENTITY waveformGen_tb IS
+-- Declarations
+
+END waveformGen_tb ;
+

zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hdl/waveformgen_tb_struct.vhg

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+--
+-- VHDL Architecture WaveformGenerator_test.waveformGen_tb.struct
+--
+-- Created:
+--          by - axel.amand.UNKNOWN (WE7860)
+--          at - 14:39:46 28.04.2023
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.ALL;
+
+LIBRARY WaveformGenerator;
+LIBRARY WaveformGenerator_test;
+
+ARCHITECTURE struct OF waveformGen_tb IS
+
+    -- Architecture declarations
+    constant bitNb: positive := 16;
+    constant clockFrequency: real := 60.0E6;
+    --constant clockFrequency: real := 66.0E6;
+
+    -- Internal signal declarations
+    SIGNAL clock : std_ulogic;
+    SIGNAL en    : std_ulogic;
+    SIGNAL reset : std_ulogic;
+    SIGNAL step  : unsigned(bitNb-1 DOWNTO 0);
+
+
+    -- Component Declarations
+    COMPONENT waveformGen
+    GENERIC (
+        phaseBitNb  : positive := 16;
+        signalBitNb : positive := 16
+    );
+    PORT (
+        clock    : IN     std_ulogic ;
+        en       : IN     std_ulogic ;
+        reset    : IN     std_ulogic ;
+        step     : IN     unsigned (phaseBitNb-1 DOWNTO 0);
+        polygon  : OUT    unsigned (signalBitNb-1 DOWNTO 0);
+        sawtooth : OUT    unsigned (phaseBitNb-1 DOWNTO 0);
+        sine     : OUT    unsigned (signalBitNb-1 DOWNTO 0);
+        square   : OUT    unsigned (signalBitNb-1 DOWNTO 0);
+        triangle : OUT    unsigned (signalBitNb-1 DOWNTO 0)
+    );
+    END COMPONENT;
+    COMPONENT waveformGen_tester
+    GENERIC (
+        bitNb          : positive := 16;
+        clockFrequency : real     := 60.0E6
+    );
+    PORT (
+        clock : OUT    std_ulogic ;
+        en    : OUT    std_ulogic ;
+        reset : OUT    std_ulogic ;
+        step  : OUT    unsigned (bitNb-1 DOWNTO 0)
+    );
+    END COMPONENT;
+
+    -- Optional embedded configurations
+    -- pragma synthesis_off
+    FOR ALL : waveformGen USE ENTITY WaveformGenerator.waveformGen;
+    FOR ALL : waveformGen_tester USE ENTITY WaveformGenerator_test.waveformGen_tester;
+    -- pragma synthesis_on
+
+
+BEGIN
+
+    -- Instance port mappings.
+    I_DUT : waveformGen
+        GENERIC MAP (
+            phaseBitNb  => bitNb,
+            signalBitNb => bitNb
+        )
+        PORT MAP (
+            clock    => clock,
+            en       => en,
+            reset    => reset,
+            step     => step,
+            polygon  => OPEN,
+            sawtooth => OPEN,
+            sine     => OPEN,
+            square   => OPEN,
+            triangle => OPEN
+        );
+    I_tb : waveformGen_tester
+        GENERIC MAP (
+            bitNb          => bitNb,
+            clockFrequency => clockFrequency
+        )
+        PORT MAP (
+            clock => clock,
+            en    => en,
+            reset => reset,
+            step  => step
+        );
+
+END struct;

zz-solutions/01-WaveformGenerator/WaveformGenerator_test/hdl/waveformgen_tester_entity.vhg

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+-- VHDL Entity WaveformGenerator_test.waveformGen_tester.interface
+--
+-- Created:
+--          by - axel.amand.UNKNOWN (WE7860)
+--          at - 14:39:31 28.04.2023
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.ALL;
+
+ENTITY waveformGen_tester IS
+    GENERIC( 
+        bitNb          : positive := 16;
+        clockFrequency : real     := 60.0E6
+    );
+    PORT( 
+        clock : OUT    std_ulogic;
+        en    : OUT    std_ulogic;
+        reset : OUT    std_ulogic;
+        step  : OUT    unsigned (bitNb-1 DOWNTO 0)
+    );
+
+-- Declarations
+
+END waveformGen_tester ;
+