add solutions
This commit is contained in:
@ -0,0 +1,56 @@
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ARCHITECTURE masterVersion OF interpolatorCalculatePolynom IS
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constant additionalBitNb: positive := 1;
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constant internalsBitNb: positive := signalBitNb + 3*oversamplingBitNb + 1
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+ additionalBitNb;
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signal x: signed(internalsBitNb-1 downto 0);
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signal u: signed(internalsBitNb-1 downto 0);
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signal v: signed(internalsBitNb-1 downto 0);
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signal w: signed(internalsBitNb-1 downto 0);
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BEGIN
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iterativePolynom: process(reset, clock)
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begin
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if reset = '1' then
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x <= (others => '0');
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u <= (others => '0');
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v <= (others => '0');
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w <= (others => '0');
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sampleOut <= (others => '0');
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elsif rising_edge(clock) then
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if en = '1' then
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if restartPolynom = '1' then
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x <= shift_left(resize(2*d, x'length), 3*oversamplingBitNb);
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u <= resize(a, u'length)
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+ shift_left(resize(b, u'length), oversamplingBitNb)
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+ shift_left(resize(c, u'length), 2*oversamplingBitNb);
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v <= resize(6*a, v'length)
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+ shift_left(resize(2*b, v'length), oversamplingBitNb);
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w <= resize(6*a, w'length);
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sampleOut <= resize(d, sampleOut'length);
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else
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x <= x + u;
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u <= u + v;
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v <= v + w;
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sampleOut <= resize(
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shift_right(x, 3*oversamplingBitNb+1), sampleOut'length
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);
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-- limit overflow
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if x(x'high downto x'high-additionalBitNb) = "01" then
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sampleOut <= not shift_left(
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resize("10", sampleOut'length), sampleOut'length-2
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);
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end if;
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-- limit underflow
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if x(x'high downto x'high-additionalBitNb) = "10" then
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sampleOut <= shift_left(
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resize("10", sampleOut'length), sampleOut'length-2
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);
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end if;
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end if;
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end if;
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end if;
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end process iterativePolynom;
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END ARCHITECTURE masterVersion;
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@ -0,0 +1,4 @@
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ARCHITECTURE studentVersion OF interpolatorCalculatePolynom IS
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BEGIN
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sampleOut <= (others => '0');
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END ARCHITECTURE studentVersion;
|
@ -0,0 +1,28 @@
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ARCHITECTURE masterVersion OF interpolatorCoefficients IS
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BEGIN
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calcCoeffs: process(interpolateLinear, sample1, sample2, sample3, sample4)
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begin
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if interpolateLinear = '1' then
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a <= (others => '0');
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b <= (others => '0');
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c <= resize(2*sample3, c'length)
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- resize(2*sample2, c'length);
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d <= resize( sample2, d'length);
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else
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a <= resize( sample4, a'length)
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- resize(3*sample3, a'length)
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+ resize(3*sample2, a'length)
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- resize( sample1, a'length);
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b <= resize(2*sample1, b'length)
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- resize(5*sample2, b'length)
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+ resize(4*sample3, b'length)
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- resize( sample4, b'length);
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c <= resize( sample3, c'length)
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- resize( sample1, c'length);
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d <= resize( sample2, d'length);
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end if;
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end process calcCoeffs;
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END ARCHITECTURE masterVersion;
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|
@ -0,0 +1,7 @@
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ARCHITECTURE studentVersion OF interpolatorCoefficients IS
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BEGIN
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a <= (others => '0');
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b <= (others => '0');
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c <= (others => '0');
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d <= (others => '0');
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END ARCHITECTURE studentVersion;
|
@ -0,0 +1,40 @@
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ARCHITECTURE masterVersion OF interpolatorShiftRegister IS
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-- signal sample4_int: signed(sampleIn'range);
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-- signal sample3_int: signed(sampleIn'range);
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-- signal sample2_int: signed(sampleIn'range);
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-- signal sample1_int: signed(sampleIn'range);
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type samplesArray is array(3 downto 0) of signed(sampleIn'range);
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signal samples: samplesArray;
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begin
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shiftThem: process(reset, clock)
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begin
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if reset = '1' then
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samples <= (others=>(others=>'0'));
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-- sample1_int <= (others => '0');
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-- sample2_int <= (others => '0');
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-- sample3_int <= (others => '0');
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-- sample4_int <= (others => '0');
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elsif rising_edge(clock) then
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if shiftSamples = '1' then
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-- sample1_int <= sample2_int;
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-- sample2_int <= sample3_int;
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-- sample3_int <= sample4_int;
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-- sample4_int <= sampleIn;
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samples(0) <= samples(1);
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samples(1) <= samples(2);
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samples(2) <= samples(3);
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samples(3) <= sampleIn;
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end if;
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end if;
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end process shiftThem;
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sample4 <= samples(3);
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sample3 <= samples(2);
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sample2 <= samples(1);
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sample1 <= samples(0);
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END ARCHITECTURE masterVersion;
|
@ -0,0 +1,7 @@
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ARCHITECTURE studentVersion OF interpolatorShiftRegister IS
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BEGIN
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sample1 <= (others => '0');
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sample2 <= (others => '0');
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sample3 <= (others => '0');
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sample4 <= (others => '0');
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END ARCHITECTURE studentVersion;
|
@ -0,0 +1,27 @@
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ARCHITECTURE masterVersion OF interpolatorTrigger IS
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signal triggerCounter: unsigned(counterBitNb-1 downto 0);
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BEGIN
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count: process(reset, clock)
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begin
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if reset = '1' then
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triggerCounter <= (others => '0');
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elsif rising_edge(clock) then
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if en = '1' then
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triggerCounter <= triggerCounter + 1;
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end if;
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end if;
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end process count;
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trig: process(triggerCounter, en)
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begin
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if triggerCounter = 0 then
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triggerOut <= en;
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else
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triggerOut <= '0';
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end if;
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end process trig;
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END ARCHITECTURE masterVersion;
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@ -0,0 +1,4 @@
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ARCHITECTURE studentVersion OF interpolatorTrigger IS
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BEGIN
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triggerOut <= '0';
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END ARCHITECTURE studentVersion;
|
@ -0,0 +1,34 @@
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-- VHDL Entity SplineInterpolator.interpolatorCalculatePolynom.symbol
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--
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-- Created:
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-- by - francois.francois (Aphelia)
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-- at - 13:00:14 02/19/19
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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ENTITY interpolatorCalculatePolynom IS
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GENERIC(
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signalBitNb : positive := 16;
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coeffBitNb : positive := 16;
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oversamplingBitNb : positive := 8
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);
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PORT(
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clock : IN std_ulogic;
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reset : IN std_ulogic;
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restartPolynom : IN std_ulogic;
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d : IN signed (coeffBitNb-1 DOWNTO 0);
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sampleOut : OUT signed (signalBitNb-1 DOWNTO 0);
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c : IN signed (coeffBitNb-1 DOWNTO 0);
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b : IN signed (coeffBitNb-1 DOWNTO 0);
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a : IN signed (coeffBitNb-1 DOWNTO 0);
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en : IN std_ulogic
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);
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-- Declarations
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END interpolatorCalculatePolynom ;
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@ -0,0 +1,33 @@
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-- VHDL Entity SplineInterpolator.interpolatorCoefficients.symbol
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--
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-- Created:
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-- by - francois.francois (Aphelia)
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-- at - 13:00:20 02/19/19
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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ENTITY interpolatorCoefficients IS
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GENERIC(
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bitNb : positive := 16;
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coeffBitNb : positive := 16
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);
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PORT(
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sample1 : IN signed (bitNb-1 DOWNTO 0);
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sample2 : IN signed (bitNb-1 DOWNTO 0);
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sample3 : IN signed (bitNb-1 DOWNTO 0);
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sample4 : IN signed (bitNb-1 DOWNTO 0);
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a : OUT signed (coeffBitNb-1 DOWNTO 0);
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b : OUT signed (coeffBitNb-1 DOWNTO 0);
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c : OUT signed (coeffBitNb-1 DOWNTO 0);
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d : OUT signed (coeffBitNb-1 DOWNTO 0);
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interpolateLinear : IN std_ulogic
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);
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-- Declarations
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END interpolatorCoefficients ;
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@ -0,0 +1,31 @@
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-- VHDL Entity SplineInterpolator.interpolatorShiftRegister.symbol
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--
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-- Created:
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-- by - francois.francois (Aphelia)
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-- at - 13:00:24 02/19/19
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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ENTITY interpolatorShiftRegister IS
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GENERIC(
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signalBitNb : positive := 16
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);
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PORT(
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clock : IN std_ulogic;
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reset : IN std_ulogic;
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shiftSamples : IN std_ulogic;
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sampleIn : IN signed (signalBitNb-1 DOWNTO 0);
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sample1 : OUT signed (signalBitNb-1 DOWNTO 0);
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sample2 : OUT signed (signalBitNb-1 DOWNTO 0);
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sample3 : OUT signed (signalBitNb-1 DOWNTO 0);
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sample4 : OUT signed (signalBitNb-1 DOWNTO 0)
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);
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-- Declarations
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END interpolatorShiftRegister ;
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|
@ -0,0 +1,27 @@
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-- VHDL Entity SplineInterpolator.interpolatorTrigger.symbol
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--
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-- Created:
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-- by - francois.francois (Aphelia)
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-- at - 13:00:28 02/19/19
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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ENTITY interpolatorTrigger IS
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GENERIC(
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counterBitNb : positive := 4
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);
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PORT(
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triggerOut : OUT std_ulogic;
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clock : IN std_ulogic;
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reset : IN std_ulogic;
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en : IN std_ulogic
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);
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-- Declarations
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END interpolatorTrigger ;
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|
@ -0,0 +1,7 @@
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ARCHITECTURE masterVersion OF offsetToUnsigned IS
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BEGIN
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unsignedOut <= not(signedIn(signedIn'high)) & unsigned(signedIn(signedIn'high-1 downto 0));
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END ARCHITECTURE masterVersion;
|
@ -0,0 +1,4 @@
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ARCHITECTURE studentVersion OF offsetToUnsigned IS
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BEGIN
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unsignedOut <= (others => '0');
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END ARCHITECTURE studentVersion;
|
@ -0,0 +1,25 @@
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-- VHDL Entity SplineInterpolator.offsetToUnsigned.symbol
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--
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-- Created:
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-- by - francois.francois (Aphelia)
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-- at - 13:00:32 02/19/19
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--
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||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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ENTITY offsetToUnsigned IS
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GENERIC(
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bitNb : positive := 16
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);
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PORT(
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unsignedOut : OUT unsigned (bitNb-1 DOWNTO 0);
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signedIn : IN signed (bitNb-1 DOWNTO 0)
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);
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-- Declarations
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END offsetToUnsigned ;
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|
@ -0,0 +1,26 @@
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-- VHDL Entity SplineInterpolator.resizer.symbol
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--
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-- Created:
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||||
-- by - francois.francois (Aphelia)
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||||
-- at - 13:00:36 02/19/19
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||||
--
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||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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ENTITY resizer IS
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GENERIC(
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inputBitNb : positive := 16;
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outputBitNb : positive := 16
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);
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PORT(
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resizeOut : OUT unsigned (outputBitNb-1 DOWNTO 0);
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resizeIn : IN unsigned (inputBitNb-1 DOWNTO 0)
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||||
);
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-- Declarations
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END resizer ;
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|
@ -0,0 +1,33 @@
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ARCHITECTURE masterVersion OF resizer IS
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BEGIN
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outGtIn: if resizeOut'length > resizeIn'length generate
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begin
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resizeOut <= shift_left(
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resize(
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resizeIn,
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resizeOut'length
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),
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resizeOut'length-resizeIn'length
|
||||
);
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end generate outGtIn;
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outEqIn: if resizeOut'length = resizeIn'length generate
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begin
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resizeOut <= resizeIn;
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end generate outEqIn;
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||||
|
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outLtIn: if resizeOut'length < resizeIn'length generate
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begin
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resizeOut <= resize(
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shift_right(
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resizeIn,
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resizeIn'length-resizeOut'length
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||||
),
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||||
resizeOut'length
|
||||
);
|
||||
end generate outLtIn;
|
||||
|
||||
END ARCHITECTURE masterVersion;
|
||||
|
@ -0,0 +1,4 @@
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ARCHITECTURE studentVersion OF resizer IS
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BEGIN
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resizeOut <= (others => '0');
|
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END ARCHITECTURE studentVersion;
|
@ -0,0 +1,57 @@
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ARCHITECTURE masterVersion OF sineTable IS
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||||
|
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signal changeSign : std_uLogic;
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||||
signal flipPhase : std_uLogic;
|
||||
signal phaseTableAddress1 : unsigned(tableAddressBitNb-1 downto 0);
|
||||
signal phaseTableAddress2 : unsigned(phaseTableAddress1'range);
|
||||
signal quarterSine : signed(sine'range);
|
||||
|
||||
signal shiftPhase : std_uLogic := '0'; -- can be used to build a cosine
|
||||
|
||||
begin
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||||
|
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changeSign <= phase(phase'high);
|
||||
flipPhase <= phase(phase'high-1);
|
||||
|
||||
phaseTableAddress1 <= phase(phase'high-2 downto phase'high-2-tableAddressBitNb+1);
|
||||
|
||||
checkPhase: process(flipPhase, shiftPhase, phaseTableAddress1)
|
||||
begin
|
||||
if (flipPhase xor shiftPhase) = '0' then
|
||||
phaseTableAddress2 <= phaseTableAddress1;
|
||||
else
|
||||
phaseTableAddress2 <= 0 - phaseTableAddress1;
|
||||
end if;
|
||||
end process checkPhase;
|
||||
|
||||
|
||||
quarterTable: process(phaseTableAddress2, flipPhase, shiftPhase)
|
||||
begin
|
||||
case to_integer(phaseTableAddress2) is
|
||||
when 0 => if (flipPhase xor shiftPhase) = '0' then
|
||||
quarterSine <= to_signed(16#0000#, quarterSine'length);
|
||||
else
|
||||
quarterSine <= to_signed(16#7FFF#, quarterSine'length);
|
||||
end if;
|
||||
when 1 => quarterSine <= to_signed(16#18F9#, quarterSine'length);
|
||||
when 2 => quarterSine <= to_signed(16#30FB#, quarterSine'length);
|
||||
when 3 => quarterSine <= to_signed(16#471C#, quarterSine'length);
|
||||
when 4 => quarterSine <= to_signed(16#5A82#, quarterSine'length);
|
||||
when 5 => quarterSine <= to_signed(16#6A6D#, quarterSine'length);
|
||||
when 6 => quarterSine <= to_signed(16#7641#, quarterSine'length);
|
||||
when 7 => quarterSine <= to_signed(16#7D89#, quarterSine'length);
|
||||
when others => quarterSine <= (others => '-');
|
||||
end case;
|
||||
end process quarterTable;
|
||||
|
||||
checkSign: process(changeSign, flipPhase, shiftPhase, quarterSine)
|
||||
begin
|
||||
if (changeSign xor (flipPhase and shiftPhase)) = '0' then
|
||||
sine <= quarterSine;
|
||||
else
|
||||
sine <= 0 - quarterSine;
|
||||
end if;
|
||||
end process checkSign;
|
||||
|
||||
END ARCHITECTURE masterVersion;
|
||||
|
@ -0,0 +1,27 @@
|
||||
ARCHITECTURE studentVersion OF sineTable IS
|
||||
|
||||
signal phaseTableAddress : unsigned(tableAddressBitNb-1 downto 0);
|
||||
signal quarterSine : signed(sine'range);
|
||||
|
||||
BEGIN
|
||||
|
||||
phaseTableAddress <= phase(phase'high-2 downto phase'high-2-tableAddressBitNb+1);
|
||||
|
||||
quarterTable: process(phaseTableAddress)
|
||||
begin
|
||||
case to_integer(phaseTableAddress) is
|
||||
when 0 => quarterSine <= to_signed(16#0000#, quarterSine'length);
|
||||
when 1 => quarterSine <= to_signed(16#18F9#, quarterSine'length);
|
||||
when 2 => quarterSine <= to_signed(16#30FB#, quarterSine'length);
|
||||
when 3 => quarterSine <= to_signed(16#471C#, quarterSine'length);
|
||||
when 4 => quarterSine <= to_signed(16#5A82#, quarterSine'length);
|
||||
when 5 => quarterSine <= to_signed(16#6A6D#, quarterSine'length);
|
||||
when 6 => quarterSine <= to_signed(16#7641#, quarterSine'length);
|
||||
when 7 => quarterSine <= to_signed(16#7D89#, quarterSine'length);
|
||||
when others => quarterSine <= (others => '-');
|
||||
end case;
|
||||
end process quarterTable;
|
||||
|
||||
sine <= (others => '0');
|
||||
|
||||
END ARCHITECTURE studentVersion;
|
@ -0,0 +1,31 @@
|
||||
-- VHDL Entity SplineInterpolator.sineGen.symbol
|
||||
--
|
||||
-- Created:
|
||||
-- by - francois.francois (Aphelia)
|
||||
-- at - 13:00:40 02/19/19
|
||||
--
|
||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.numeric_std.all;
|
||||
|
||||
ENTITY sineGen IS
|
||||
GENERIC(
|
||||
signalBitNb : positive := 16;
|
||||
phaseBitNb : positive := 10
|
||||
);
|
||||
PORT(
|
||||
clock : IN std_ulogic;
|
||||
reset : IN std_ulogic;
|
||||
step : IN unsigned (phaseBitNb-1 DOWNTO 0);
|
||||
sawtooth : OUT unsigned (signalBitNb-1 DOWNTO 0);
|
||||
sine : OUT unsigned (signalBitNb-1 DOWNTO 0);
|
||||
square : OUT unsigned (signalBitNb-1 DOWNTO 0);
|
||||
triangle : OUT unsigned (signalBitNb-1 DOWNTO 0)
|
||||
);
|
||||
|
||||
-- Declarations
|
||||
|
||||
END sineGen ;
|
||||
|
@ -0,0 +1,307 @@
|
||||
--
|
||||
-- VHDL Architecture SplineInterpolator.sineGen.struct
|
||||
--
|
||||
-- Created:
|
||||
-- by - axel.amand.UNKNOWN (WE7860)
|
||||
-- at - 14:42:04 28.04.2023
|
||||
--
|
||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.numeric_std.all;
|
||||
|
||||
LIBRARY SplineInterpolator;
|
||||
LIBRARY WaveformGenerator;
|
||||
|
||||
ARCHITECTURE struct OF sineGen IS
|
||||
|
||||
-- Architecture declarations
|
||||
constant tableAddressBitNb : positive := 3;
|
||||
constant sampleCountBitNb : positive := phaseBitNb-2-tableAddressBitNb;
|
||||
constant coeffBitNb : positive := signalBitNb+4;
|
||||
|
||||
-- Internal signal declarations
|
||||
SIGNAL a : signed(coeffBitNb-1 DOWNTO 0);
|
||||
SIGNAL b : signed(coeffBitNb-1 DOWNTO 0);
|
||||
SIGNAL c : signed(coeffBitNb-1 DOWNTO 0);
|
||||
SIGNAL d : signed(coeffBitNb-1 DOWNTO 0);
|
||||
SIGNAL logic0 : std_ulogic;
|
||||
SIGNAL logic1 : std_ulogic;
|
||||
SIGNAL newPolynom : std_ulogic;
|
||||
SIGNAL phase : unsigned(phaseBitNb-1 DOWNTO 0);
|
||||
SIGNAL sample1 : signed(signalBitNb-1 DOWNTO 0);
|
||||
SIGNAL sample2 : signed(signalBitNb-1 DOWNTO 0);
|
||||
SIGNAL sample3 : signed(signalBitNb-1 DOWNTO 0);
|
||||
SIGNAL sample4 : signed(signalBitNb-1 DOWNTO 0);
|
||||
SIGNAL sineSamples : signed(signalBitNb-1 DOWNTO 0);
|
||||
SIGNAL sineSigned : signed(signalBitNb-1 DOWNTO 0);
|
||||
|
||||
-- Implicit buffer signal declarations
|
||||
SIGNAL sawtooth_internal : unsigned (signalBitNb-1 DOWNTO 0);
|
||||
|
||||
|
||||
-- Component Declarations
|
||||
COMPONENT interpolatorCalculatePolynom
|
||||
GENERIC (
|
||||
signalBitNb : positive := 16;
|
||||
coeffBitNb : positive := 16;
|
||||
oversamplingBitNb : positive := 8
|
||||
);
|
||||
PORT (
|
||||
clock : IN std_ulogic ;
|
||||
reset : IN std_ulogic ;
|
||||
restartPolynom : IN std_ulogic ;
|
||||
d : IN signed (coeffBitNb-1 DOWNTO 0);
|
||||
sampleOut : OUT signed (signalBitNb-1 DOWNTO 0);
|
||||
c : IN signed (coeffBitNb-1 DOWNTO 0);
|
||||
b : IN signed (coeffBitNb-1 DOWNTO 0);
|
||||
a : IN signed (coeffBitNb-1 DOWNTO 0);
|
||||
en : IN std_ulogic
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT interpolatorCoefficients
|
||||
GENERIC (
|
||||
bitNb : positive := 16;
|
||||
coeffBitNb : positive := 16
|
||||
);
|
||||
PORT (
|
||||
sample1 : IN signed (bitNb-1 DOWNTO 0);
|
||||
sample2 : IN signed (bitNb-1 DOWNTO 0);
|
||||
sample3 : IN signed (bitNb-1 DOWNTO 0);
|
||||
sample4 : IN signed (bitNb-1 DOWNTO 0);
|
||||
a : OUT signed (coeffBitNb-1 DOWNTO 0);
|
||||
b : OUT signed (coeffBitNb-1 DOWNTO 0);
|
||||
c : OUT signed (coeffBitNb-1 DOWNTO 0);
|
||||
d : OUT signed (coeffBitNb-1 DOWNTO 0);
|
||||
interpolateLinear : IN std_ulogic
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT interpolatorShiftRegister
|
||||
GENERIC (
|
||||
signalBitNb : positive := 16
|
||||
);
|
||||
PORT (
|
||||
clock : IN std_ulogic ;
|
||||
reset : IN std_ulogic ;
|
||||
shiftSamples : IN std_ulogic ;
|
||||
sampleIn : IN signed (signalBitNb-1 DOWNTO 0);
|
||||
sample1 : OUT signed (signalBitNb-1 DOWNTO 0);
|
||||
sample2 : OUT signed (signalBitNb-1 DOWNTO 0);
|
||||
sample3 : OUT signed (signalBitNb-1 DOWNTO 0);
|
||||
sample4 : OUT signed (signalBitNb-1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT interpolatorTrigger
|
||||
GENERIC (
|
||||
counterBitNb : positive := 4
|
||||
);
|
||||
PORT (
|
||||
triggerOut : OUT std_ulogic ;
|
||||
clock : IN std_ulogic ;
|
||||
reset : IN std_ulogic ;
|
||||
en : IN std_ulogic
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT offsetToUnsigned
|
||||
GENERIC (
|
||||
bitNb : positive := 16
|
||||
);
|
||||
PORT (
|
||||
unsignedOut : OUT unsigned (bitNb-1 DOWNTO 0);
|
||||
signedIn : IN signed (bitNb-1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT resizer
|
||||
GENERIC (
|
||||
inputBitNb : positive := 16;
|
||||
outputBitNb : positive := 16
|
||||
);
|
||||
PORT (
|
||||
resizeOut : OUT unsigned (outputBitNb-1 DOWNTO 0);
|
||||
resizeIn : IN unsigned (inputBitNb-1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT sineTable
|
||||
GENERIC (
|
||||
inputBitNb : positive := 16;
|
||||
outputBitNb : positive := 16;
|
||||
tableAddressBitNb : positive := 3
|
||||
);
|
||||
PORT (
|
||||
sine : OUT signed (outputBitNb-1 DOWNTO 0);
|
||||
phase : IN unsigned (inputBitNb-1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT sawtoothGen
|
||||
GENERIC (
|
||||
bitNb : positive := 16
|
||||
);
|
||||
PORT (
|
||||
sawtooth : OUT unsigned (bitNb-1 DOWNTO 0);
|
||||
clock : IN std_ulogic ;
|
||||
reset : IN std_ulogic ;
|
||||
step : IN unsigned (bitNb-1 DOWNTO 0);
|
||||
en : IN std_ulogic
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT sawtoothToSquare
|
||||
GENERIC (
|
||||
bitNb : positive := 16
|
||||
);
|
||||
PORT (
|
||||
square : OUT unsigned (bitNb-1 DOWNTO 0);
|
||||
sawtooth : IN unsigned (bitNb-1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT sawtoothToTriangle
|
||||
GENERIC (
|
||||
bitNb : positive := 16
|
||||
);
|
||||
PORT (
|
||||
triangle : OUT unsigned (bitNb-1 DOWNTO 0);
|
||||
sawtooth : IN unsigned (bitNb-1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
-- Optional embedded configurations
|
||||
-- pragma synthesis_off
|
||||
FOR ALL : interpolatorCalculatePolynom USE ENTITY SplineInterpolator.interpolatorCalculatePolynom;
|
||||
FOR ALL : interpolatorCoefficients USE ENTITY SplineInterpolator.interpolatorCoefficients;
|
||||
FOR ALL : interpolatorShiftRegister USE ENTITY SplineInterpolator.interpolatorShiftRegister;
|
||||
FOR ALL : interpolatorTrigger USE ENTITY SplineInterpolator.interpolatorTrigger;
|
||||
FOR ALL : offsetToUnsigned USE ENTITY SplineInterpolator.offsetToUnsigned;
|
||||
FOR ALL : resizer USE ENTITY SplineInterpolator.resizer;
|
||||
FOR ALL : sawtoothGen USE ENTITY WaveformGenerator.sawtoothGen;
|
||||
FOR ALL : sawtoothToSquare USE ENTITY WaveformGenerator.sawtoothToSquare;
|
||||
FOR ALL : sawtoothToTriangle USE ENTITY WaveformGenerator.sawtoothToTriangle;
|
||||
FOR ALL : sineTable USE ENTITY SplineInterpolator.sineTable;
|
||||
-- pragma synthesis_on
|
||||
|
||||
|
||||
BEGIN
|
||||
-- Architecture concurrent statements
|
||||
-- HDL Embedded Text Block 2 eb2
|
||||
logic1 <= '1';
|
||||
|
||||
-- HDL Embedded Text Block 3 eb3
|
||||
logic0 <= '0';
|
||||
|
||||
|
||||
-- Instance port mappings.
|
||||
I_spline : interpolatorCalculatePolynom
|
||||
GENERIC MAP (
|
||||
signalBitNb => signalBitNb,
|
||||
coeffBitNb => coeffBitNb,
|
||||
oversamplingBitNb => sampleCountBitNb
|
||||
)
|
||||
PORT MAP (
|
||||
clock => clock,
|
||||
reset => reset,
|
||||
restartPolynom => newPolynom,
|
||||
d => d,
|
||||
sampleOut => sineSigned,
|
||||
c => c,
|
||||
b => b,
|
||||
a => a,
|
||||
en => logic1
|
||||
);
|
||||
I_coeffs : interpolatorCoefficients
|
||||
GENERIC MAP (
|
||||
bitNb => signalBitNb,
|
||||
coeffBitNb => coeffBitNb
|
||||
)
|
||||
PORT MAP (
|
||||
sample1 => sample1,
|
||||
sample2 => sample2,
|
||||
sample3 => sample3,
|
||||
sample4 => sample4,
|
||||
a => a,
|
||||
b => b,
|
||||
c => c,
|
||||
d => d,
|
||||
interpolateLinear => logic0
|
||||
);
|
||||
I_shReg : interpolatorShiftRegister
|
||||
GENERIC MAP (
|
||||
signalBitNb => signalBitNb
|
||||
)
|
||||
PORT MAP (
|
||||
clock => clock,
|
||||
reset => reset,
|
||||
shiftSamples => newPolynom,
|
||||
sampleIn => sineSamples,
|
||||
sample1 => sample1,
|
||||
sample2 => sample2,
|
||||
sample3 => sample3,
|
||||
sample4 => sample4
|
||||
);
|
||||
I_trig : interpolatorTrigger
|
||||
GENERIC MAP (
|
||||
counterBitNb => sampleCountBitNb
|
||||
)
|
||||
PORT MAP (
|
||||
triggerOut => newPolynom,
|
||||
clock => clock,
|
||||
reset => reset,
|
||||
en => logic1
|
||||
);
|
||||
I_unsigned : offsetToUnsigned
|
||||
GENERIC MAP (
|
||||
bitNb => signalBitNb
|
||||
)
|
||||
PORT MAP (
|
||||
unsignedOut => sine,
|
||||
signedIn => sineSigned
|
||||
);
|
||||
I_size : resizer
|
||||
GENERIC MAP (
|
||||
inputBitNb => phaseBitNb,
|
||||
outputBitNb => signalBitNb
|
||||
)
|
||||
PORT MAP (
|
||||
resizeOut => sawtooth_internal,
|
||||
resizeIn => phase
|
||||
);
|
||||
I_sin : sineTable
|
||||
GENERIC MAP (
|
||||
inputBitNb => phaseBitNb,
|
||||
outputBitNb => signalBitNb,
|
||||
tableAddressBitNb => tableAddressBitNb
|
||||
)
|
||||
PORT MAP (
|
||||
sine => sineSamples,
|
||||
phase => phase
|
||||
);
|
||||
I_saw : sawtoothGen
|
||||
GENERIC MAP (
|
||||
bitNb => phaseBitNb
|
||||
)
|
||||
PORT MAP (
|
||||
sawtooth => phase,
|
||||
clock => clock,
|
||||
reset => reset,
|
||||
step => step,
|
||||
en => logic1
|
||||
);
|
||||
I_square : sawtoothToSquare
|
||||
GENERIC MAP (
|
||||
bitNb => signalBitNb
|
||||
)
|
||||
PORT MAP (
|
||||
square => square,
|
||||
sawtooth => sawtooth_internal
|
||||
);
|
||||
I_tri : sawtoothToTriangle
|
||||
GENERIC MAP (
|
||||
bitNb => signalBitNb
|
||||
)
|
||||
PORT MAP (
|
||||
triangle => triangle,
|
||||
sawtooth => sawtooth_internal
|
||||
);
|
||||
|
||||
-- Implicit buffered output assignments
|
||||
sawtooth <= sawtooth_internal;
|
||||
|
||||
END struct;
|
@ -0,0 +1,27 @@
|
||||
-- VHDL Entity SplineInterpolator.sineTable.symbol
|
||||
--
|
||||
-- Created:
|
||||
-- by - francois.francois (Aphelia)
|
||||
-- at - 13:00:46 02/19/19
|
||||
--
|
||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.numeric_std.all;
|
||||
|
||||
ENTITY sineTable IS
|
||||
GENERIC(
|
||||
inputBitNb : positive := 16;
|
||||
outputBitNb : positive := 16;
|
||||
tableAddressBitNb : positive := 3
|
||||
);
|
||||
PORT(
|
||||
sine : OUT signed (outputBitNb-1 DOWNTO 0);
|
||||
phase : IN unsigned (inputBitNb-1 DOWNTO 0)
|
||||
);
|
||||
|
||||
-- Declarations
|
||||
|
||||
END sineTable ;
|
||||
|
Binary file not shown.
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
@ -0,0 +1,42 @@
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
NO_GRAPHIC 0
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 50,0 8 0
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 13,0 13 1
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 83,0 19 0
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 89,0 20 0
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 94,0 21 0
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 104,0 22 0
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 109,0 23 0
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 125,0 24 0
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 130,0 25 0
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 135,0 26 0
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 141,0 27 0
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 30 0
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 31 0
|
@ -0,0 +1,42 @@
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
NO_GRAPHIC 0
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 50,0 8 0
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 13,0 13 1
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 104,0 18 0
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 109,0 19 0
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 114,0 20 0
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 119,0 21 0
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 125,0 22 0
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 130,0 23 0
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 140,0 24 0
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 135,0 25 0
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 149,0 26 0
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 29 0
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 30 0
|
@ -0,0 +1,39 @@
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
NO_GRAPHIC 0
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 50,0 8 0
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 13,0 13 1
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 83,0 17 0
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 89,0 18 0
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 94,0 19 0
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 99,0 20 0
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 104,0 21 0
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 109,0 22 0
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 114,0 23 0
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 119,0 24 0
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 27 0
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 28 0
|
@ -0,0 +1,27 @@
|
||||
DESIGN interpolator@trigger
|
||||
VIEW symbol.sb
|
||||
NO_GRAPHIC 0
|
||||
DESIGN interpolator@trigger
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 50,0 8 0
|
||||
DESIGN interpolator@trigger
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 13,0 13 1
|
||||
DESIGN interpolator@trigger
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 57,0 17 0
|
||||
DESIGN interpolator@trigger
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 83,0 18 0
|
||||
DESIGN interpolator@trigger
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 89,0 19 0
|
||||
DESIGN interpolator@trigger
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 94,0 20 0
|
||||
DESIGN interpolator@trigger
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 23 0
|
||||
DESIGN interpolator@trigger
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 24 0
|
@ -0,0 +1,21 @@
|
||||
DESIGN offset@to@unsigned
|
||||
VIEW symbol.sb
|
||||
NO_GRAPHIC 0
|
||||
DESIGN offset@to@unsigned
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 50,0 8 0
|
||||
DESIGN offset@to@unsigned
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 13,0 13 1
|
||||
DESIGN offset@to@unsigned
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 57,0 17 0
|
||||
DESIGN offset@to@unsigned
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 83,0 18 0
|
||||
DESIGN offset@to@unsigned
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 21 0
|
||||
DESIGN offset@to@unsigned
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 22 0
|
@ -0,0 +1,21 @@
|
||||
DESIGN resizer
|
||||
VIEW symbol.sb
|
||||
NO_GRAPHIC 0
|
||||
DESIGN resizer
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 50,0 8 0
|
||||
DESIGN resizer
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 13,0 13 1
|
||||
DESIGN resizer
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 57,0 18 0
|
||||
DESIGN resizer
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 83,0 19 0
|
||||
DESIGN resizer
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 22 0
|
||||
DESIGN resizer
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 23 0
|
@ -0,0 +1,36 @@
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
NO_GRAPHIC 0
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 50,0 8 0
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 13,0 13 1
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 52,0 18 0
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 88,0 19 0
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 128,0 20 0
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 98,0 21 0
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 103,0 22 0
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 108,0 23 0
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 118,0 24 0
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 27 0
|
||||
DESIGN sine@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 28 0
|
@ -0,0 +1,519 @@
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 84,0 9 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 12
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 0,0 16 2
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1,0 19 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 19
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1701,0 24 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1709,0 25 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1717,0 26 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1725,0 27 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2579,0 28 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2447,0 29 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1658,0 30 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 726,0 31 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1277,0 32 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1285,0 33 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1293,0 34 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1301,0 35 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1102,0 36 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2227,0 37 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 38
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 887,0 40 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 42
|
||||
LIBRARY SplineInterpolator
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW master@version
|
||||
GRAPHIC 3829,0 44 0
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 14,0 45 1
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 83,0 51 0
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 89,0 52 0
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 94,0 53 0
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 104,0 54 0
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 109,0 55 0
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 125,0 56 0
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 130,0 57 0
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 135,0 58 0
|
||||
DESIGN interpolator@calculate@polynom
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 141,0 59 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3784,0 62 0
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 14,0 63 1
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 104,0 68 0
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 109,0 69 0
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 114,0 70 0
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 119,0 71 0
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 125,0 72 0
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 130,0 73 0
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 140,0 74 0
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 135,0 75 0
|
||||
DESIGN interpolator@coefficients
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 149,0 76 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3739,0 79 0
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 14,0 80 1
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 83,0 84 0
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 89,0 85 0
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 94,0 86 0
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 99,0 87 0
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 104,0 88 0
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 109,0 89 0
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 114,0 90 0
|
||||
DESIGN interpolator@shift@register
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 119,0 91 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3698,0 94 0
|
||||
DESIGN interpolator@trigger
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 14,0 95 1
|
||||
DESIGN interpolator@trigger
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 57,0 99 0
|
||||
DESIGN interpolator@trigger
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 83,0 100 0
|
||||
DESIGN interpolator@trigger
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 89,0 101 0
|
||||
DESIGN interpolator@trigger
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 94,0 102 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3846,0 105 0
|
||||
DESIGN offset@to@unsigned
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 14,0 106 1
|
||||
DESIGN offset@to@unsigned
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 57,0 110 0
|
||||
DESIGN offset@to@unsigned
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 83,0 111 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3584,0 114 0
|
||||
DESIGN resizer
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 14,0 115 1
|
||||
DESIGN resizer
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 57,0 120 0
|
||||
DESIGN resizer
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 83,0 121 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3601,0 124 0
|
||||
DESIGN sine@table
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 14,0 125 1
|
||||
DESIGN sine@table
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 57,0 131 0
|
||||
DESIGN sine@table
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 83,0 132 0
|
||||
LIBRARY WaveformGenerator
|
||||
DESIGN sawtooth@gen
|
||||
VIEW master@version
|
||||
GRAPHIC 3673,0 135 0
|
||||
DESIGN sawtooth@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 14,0 136 1
|
||||
DESIGN sawtooth@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 57,0 140 0
|
||||
DESIGN sawtooth@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 52,0 141 0
|
||||
DESIGN sawtooth@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 76,0 142 0
|
||||
DESIGN sawtooth@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 83,0 143 0
|
||||
DESIGN sawtooth@gen
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 89,0 144 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2908,0 147 0
|
||||
DESIGN sawtooth@to@square
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 14,0 148 1
|
||||
DESIGN sawtooth@to@square
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 57,0 152 0
|
||||
DESIGN sawtooth@to@square
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 83,0 153 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2925,0 156 0
|
||||
DESIGN sawtooth@to@triangle
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 14,0 157 1
|
||||
DESIGN sawtooth@to@triangle
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 57,0 161 0
|
||||
DESIGN sawtooth@to@triangle
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 83,0 162 0
|
||||
LIBRARY SplineInterpolator
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 165
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3829,0 168 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3784,0 169 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3739,0 170 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3698,0 171 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3846,0 172 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3584,0 173 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3673,0 174 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2908,0 175 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2925,0 176 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3601,0 177 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 180
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2375,0 183 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 185
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2562,0 186 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 188
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 189
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3829,0 191 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3836,0 192 1
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1814,0 198 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1822,0 199 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1830,0 200 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1727,0 201 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2219,0 202 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1719,0 203 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1711,0 204 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1703,0 205 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2394,0 206 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3784,0 208 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3791,0 209 1
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1279,0 214 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1287,0 215 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1295,0 216 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1303,0 217 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1703,0 218 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1711,0 219 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1719,0 220 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1727,0 221 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2571,0 222 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3739,0 224 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3746,0 225 1
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1228,0 229 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1220,0 230 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1106,0 231 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1096,0 232 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1279,0 233 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1287,0 234 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1295,0 235 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1303,0 236 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3698,0 238 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3705,0 239 1
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1106,0 243 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 985,0 244 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 993,0 245 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2386,0 246 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3846,0 248 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3853,0 249 1
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 562,0 253 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2219,0 254 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3584,0 256 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3591,0 257 1
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 601,0 262 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 414,0 263 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3601,0 265 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3608,0 266 1
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 1096,0 272 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 472,0 273 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3673,0 275 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 3680,0 276 1
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 414,0 280 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 15,0 281 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 237,0 282 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 781,0 283 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2449,0 284 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2908,0 286 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2915,0 287 1
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 480,0 291 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 887,0 292 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2925,0 294 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 2932,0 295 1
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 424,0 299 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 858,0 300 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
GRAPHIC 887,0 304 0
|
||||
DESIGN sine@gen
|
||||
VIEW struct.bd
|
||||
NO_GRAPHIC 306
|
@ -0,0 +1,21 @@
|
||||
DESIGN sine@table
|
||||
VIEW symbol.sb
|
||||
NO_GRAPHIC 0
|
||||
DESIGN sine@table
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 50,0 8 0
|
||||
DESIGN sine@table
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 13,0 13 1
|
||||
DESIGN sine@table
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 57,0 19 0
|
||||
DESIGN sine@table
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 83,0 20 0
|
||||
DESIGN sine@table
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 23 0
|
||||
DESIGN sine@table
|
||||
VIEW symbol.sb
|
||||
GRAPHIC 1,0 24 0
|
@ -0,0 +1,2 @@
|
||||
DEFAULT_ARCHITECTURE atom masterVersion
|
||||
DEFAULT_FILE atom interpolatorCalculatePolynom_masterVersion.vhd
|
@ -0,0 +1,2 @@
|
||||
DEFAULT_ARCHITECTURE atom masterVersion
|
||||
DEFAULT_FILE atom interpolatorCoefficients_masterVersion.vhd
|
@ -0,0 +1,2 @@
|
||||
DEFAULT_ARCHITECTURE atom masterVersion
|
||||
DEFAULT_FILE atom interpolatorShiftRegister_masterVersion.vhd
|
@ -0,0 +1,2 @@
|
||||
DEFAULT_ARCHITECTURE atom masterVersion
|
||||
DEFAULT_FILE atom interpolatorTrigger_masterVersion.vhd
|
@ -0,0 +1,2 @@
|
||||
DEFAULT_ARCHITECTURE atom masterVersion
|
||||
DEFAULT_FILE atom offsetToUnsigned_masterVersion.vhd
|
@ -0,0 +1,2 @@
|
||||
DEFAULT_ARCHITECTURE atom masterVersion
|
||||
DEFAULT_FILE atom resizer_masterVersion.vhd
|
@ -0,0 +1,3 @@
|
||||
DEFAULT_FILE atom sine@gen/struct.bd
|
||||
DEFAULT_ARCHITECTURE atom struct
|
||||
TOP_MARKER atom 1
|
@ -0,0 +1,2 @@
|
||||
DEFAULT_ARCHITECTURE atom masterVersion
|
||||
DEFAULT_FILE atom sineTable_masterVersion.vhd
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user