add solutions

zz-solutions/04-Lissajous/Board/hdl/DFF_sim.vhd

@@ -0,0 +1,14 @@
+ARCHITECTURE sim OF DFF IS
+BEGIN
+
+  process(clk, clr)
+  begin
+    if clr = '1' then
+      q <= '0';
+    elsif rising_edge(clk) then
+      q <= d;
+    end if;
+  end process;
+
+END ARCHITECTURE sim;
+

zz-solutions/04-Lissajous/Board/hdl/buff_sim.vhd

@@ -0,0 +1,7 @@
+ARCHITECTURE sim OF buff IS
+BEGIN
+
+  out1 <= in1;
+
+END ARCHITECTURE sim;
+

zz-solutions/04-Lissajous/Board/hdl/inverterIn_sim.vhd

@@ -0,0 +1,7 @@
+ARCHITECTURE sim OF inverterIn IS
+BEGIN
+
+  out1 <= NOT in1;
+
+END ARCHITECTURE sim;
+

zz-solutions/04-Lissajous/Board/hdl/inverter_sim.vhd

@@ -0,0 +1,7 @@
+ARCHITECTURE sim OF inverter IS
+BEGIN
+
+  out1 <= NOT in1;
+
+END ARCHITECTURE sim;
+

zz-solutions/04-Lissajous/Board/hdl/lissajousgenerator_circuit_EBS2_masterversion.vhd

@@ -0,0 +1,110 @@
+--
+-- VHDL Architecture Board.lissajousGenerator_circuit.masterVersion
+--
+-- Created:
+--          by - zas.UNKNOWN (ZELL)
+--          at - 14:16:11 02/20/2020
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2019.3 (Build 4)
+--
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+  USE ieee.numeric_std.all;
+
+LIBRARY Board;
+LIBRARY Lissajous;
+
+ARCHITECTURE masterVersion OF lissajousGenerator_circuit_EBS2 IS
+
+   -- Architecture declarations
+   constant signalBitNb: positive := 16;
+   constant phaseBitNb: positive := 17;
+   constant stepX: positive := 3;
+   constant stepY: positive := 4;
+
+   -- Internal signal declarations
+   SIGNAL logic1      : std_uLogic;
+   SIGNAL reset       : std_ulogic;
+   SIGNAL resetSnch_N : std_ulogic;
+   SIGNAL resetSynch  : std_ulogic;
+
+
+   -- Component Declarations
+   COMPONENT DFF
+   PORT (
+      CLK : IN     std_uLogic ;
+      CLR : IN     std_uLogic ;
+      D   : IN     std_uLogic ;
+      Q   : OUT    std_uLogic 
+   );
+   END COMPONENT;
+   COMPONENT inverterIn
+   PORT (
+      in1  : IN     std_uLogic ;
+      out1 : OUT    std_uLogic 
+   );
+   END COMPONENT;
+   COMPONENT lissajousGenerator
+   GENERIC (
+      signalBitNb : positive := 16;
+      phaseBitNb  : positive := 16;
+      stepX       : positive := 1;
+      stepY       : positive := 1
+   );
+   PORT (
+      clock      : IN     std_ulogic ;
+      reset      : IN     std_ulogic ;
+      triggerOut : OUT    std_ulogic ;
+      xOut       : OUT    std_ulogic ;
+      yOut       : OUT    std_ulogic 
+   );
+   END COMPONENT;
+
+   -- Optional embedded configurations
+   -- pragma synthesis_off
+   FOR ALL : DFF USE ENTITY Board.DFF;
+   FOR ALL : inverterIn USE ENTITY Board.inverterIn;
+   FOR ALL : lissajousGenerator USE ENTITY Lissajous.lissajousGenerator;
+   -- pragma synthesis_on
+
+
+BEGIN
+   -- Architecture concurrent statements
+   -- HDL Embedded Text Block 4 eb4
+   logic1 <= '1';
+
+
+   -- Instance port mappings.
+   I_dff : DFF
+      PORT MAP (
+         CLK => clock,
+         CLR => reset,
+         D   => logic1,
+         Q   => resetSnch_N
+      );
+   I_inv1 : inverterIn
+      PORT MAP (
+         in1  => reset_N,
+         out1 => reset
+      );
+   I_inv2 : inverterIn
+      PORT MAP (
+         in1  => resetSnch_N,
+         out1 => resetSynch
+      );
+   I_main : lissajousGenerator
+      GENERIC MAP (
+         signalBitNb => signalBitNb,
+         phaseBitNb  => phaseBitNb,
+         stepX       => stepX,
+         stepY       => stepY
+      )
+      PORT MAP (
+         clock      => clock,
+         reset      => resetSynch,
+         triggerOut => triggerOut,
+         xOut       => xOut,
+         yOut       => yOut
+      );
+
+END masterVersion;