add solutions

2024-03-15 15:03:34 +01:00
parent 3095603e39
commit 9ceb15c0ff
612 changed files with 272868 additions and 0 deletions
--- a/zz-solutions/04-Lissajous/Lissajous_test/hdl/lissajousGenerator_tester_test.vhd
+++ b/zz-solutions/04-Lissajous/Lissajous_test/hdl/lissajousGenerator_tester_test.vhd
@ -0,0 +1,13 @@
+ARCHITECTURE test OF lissajousGenerator_tester IS
+
+  constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
+  signal sClock: std_uLogic := '1';
+
+BEGIN
+  ------------------------------------------------------------------------------
+                                                              -- clock and reset
+  sClock <= not sClock after clockPeriod/2;
+  clock <= transport sClock after clockPeriod*9/10;
+  reset <= '1', '0' after 2*clockPeriod;
+
+END ARCHITECTURE test;