add trigger + shift register + coeff

02-SplineInterpolator/SplineInterpolator/hdl/interpolatorCoefficients_studentVersion.vhd

@@ -1,7 +1,27 @@
 ARCHITECTURE studentVersion OF interpolatorCoefficients IS
+
+subtype sample is signed(bitNb-1 DOWNTO 0);
+subtype coeff is signed(coeffBitNb-1 DOWNTO 0);
+
+type samples_type is array (1 to 4) of coeff;
+signal samples: samples_type;
+
 BEGIN
-  a <= (others => '0');
-  b <= (others => '0');
-  c <= (others => '0');
-  d <= (others => '0');
+-- a = - sample1 +3·sample2 -3·sample3 + sample4
+-- b = 2·sample1 -5·sample2 +4·sample3 - sample4
+-- c = - sample1 + sample3
+-- d = sample2 
+
+  process(sample1, sample2, sample3, sample4) begin
+    samples(4) <= resize(sample1, coeff'high+1);
+    samples(3) <= resize(sample2, coeff'high+1);
+    samples(2) <= resize(sample3, coeff'high+1);
+    samples(1) <= resize(sample4, coeff'high+1);
+  end process;
+
+
+  a <= samples(4) - samples(1) + resize( 3*(samples(2) - samples(3)), coeff'high+1);
+  b <= resize(2*samples(1), coeff'high+1) - resize(5*samples(2), coeff'high+1) + resize(4*samples(3), coeff'high+1) - samples(4);
+  c <= samples(3) - samples(1);
+  d <= samples(4);
 END ARCHITECTURE studentVersion;

02-SplineInterpolator/SplineInterpolator/hdl/interpolatorShiftRegister_studentVersion.vhd

@@ -1,7 +1,26 @@
 ARCHITECTURE studentVersion OF interpolatorShiftRegister IS
+
+subtype sample_type is signed(sampleIn'range);
+type samples_type is array (1 to 4) of sample_type;
+signal samples: samples_type;
+
 BEGIN
-  sample1 <= (others => '0');
-  sample2 <= (others => '0');
-  sample3 <= (others => '0');
-  sample4 <= (others => '0');
+
+  process(clock, reset) begin
+    if reset = '1' then
+      samples <= (others => (others => '0'));
+    elsif rising_edge(clock) then
+      if shiftSamples then
+        for i in samples_type'low to samples_type'high-1 loop
+          samples(i+1) <= samples(i);
+        end loop;
+        samples(1) <= sampleIn;
+      end if;
+    end if;
+  end process;
+
+  sample1 <= samples(1);
+  sample2 <= samples(2);
+  sample3 <= samples(3);
+  sample4 <= samples(4);
 END ARCHITECTURE studentVersion;

02-SplineInterpolator/SplineInterpolator/hdl/interpolatorTrigger_studentVersion.vhd

@@ -1,4 +1,27 @@
 ARCHITECTURE studentVersion OF interpolatorTrigger IS
+
+  signal counter : unsigned(counterBitNb-1 downto 0);
+
 BEGIN
-  triggerOut <= '0';
+
+  process(clock, reset)
+  begin
+    if reset = '1' then
+      counter <= (others => '1');
+    elsif rising_edge(clock) then
+      if en = '1' then
+        counter <= counter - 1;
+      end if;
+    end if;
+  end process;
+
+  process(counter)
+  begin
+    if counter = 0 then
+      triggerOut <= '1';
+    else
+      triggerOut <= '0';
+    end if;
+  end process;
+        
 END ARCHITECTURE studentVersion;

02-SplineInterpolator/SplineInterpolator/hdl/sineTable_studentVersion.vhd

@@ -8,7 +8,7 @@ BEGIN
 
   phaseTableAddress <= phase(phase'high-2 downto phase'high-2-tableAddressBitNb+1);
 
-  sequenceTable: process(phase)
+  sequenceTable: process(phaseTableAddress)
   begin
     if phase(phase'high-1) = '1' then
       phaseTableAddress2 <= 8 - phaseTableAddress;
@@ -30,9 +30,14 @@ BEGIN
       when 7 => quarterSine <= to_signed(16#7D89#, quarterSine'length);
       when others => quarterSine <= (others => '-');
     end case;
+    if phaseTableAddress2 = 0 then
+      if phase(phase'high-1) = '1' then
+        quarterSine <= to_signed(16#7FFF#, quarterSine'length);
+      end if;
+    end if;
   end process quarterTable;
 
-  invert: process(quarterSine)
+  invert: process(quarterSine, phase(phase'high))
   begin
     if phase(phase'high) = '1' then
       sine <= NOT quarterSine;
@@ -40,7 +45,5 @@ BEGIN
       sine <= quarterSine;
     end if;
   end process invert;
-  
-  --sine <= quarterSine;
 
 END ARCHITECTURE studentVersion;