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github-classroom[bot]
2024-02-23 13:01:05 +00:00
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commit d212040c30
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64
01-WaveformGenerator/Prefs/dp_user/v2_72/dp_user_prefs Normal file
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[LexParser.LexVHDL2008]
[LexParser]
[Editor]
recentFile0=/usr/opt/HDS/hdl_libs/ieee/hdl/std_logic_1164.vhdl
lastFilter=.vhdl
mark.lineImage=blueball
[Printer]
ENSCRIPT_LIBRARY=/usr/opt/HDS/resources/enscript/share/enscript
[ToolbarFrames]
geom0Group1=top H
geom0Group2=top H
geom0Group3=top H
state0Search=1
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state0VersionManagement=1
state0Tasks=1
state0View=1
state0Standard=1
state0Edit=1
Group1=Standard Search
Group2=Edit Bookmarks View Macros DocumentTools Windows
Group3=VersionManagement Tasks
state0Macros=1
state0Bookmarks=1
state0Windows=1
state0DocumentTools=1
[LexParser.LexPSL]
[DND]
TrackerBg=#c3c3c3
signalAcceptDropBg=white
signalRefuseDropBg=red
[General]
[Browser]
normalTextBg=white
normalTextFg=black
[Replace]
historyMax=4
atomicReplaceAll=No
[Console]
[Templates]
Visibility=No
[SearchInFiles]
SearchAsRegExp=0
MatchCase=0
LookInSubfolders=0
historyMax=4
[VDiff]
[R72]
indentType=spaces
indentString=\#\#\#
[TCOM]
logTCOMActivity=No
afterIdleHandlerTimeSlice=300
[Menus]
DocAndVis=
[Help]
default=te_guide
[Plugins]
userLanguages=
[Search]
historyMax=4
[Geometry]
TopWindow0=1286x981+317+1103
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19
01-WaveformGenerator/Prefs/hds.hdp Normal file
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[Concat]
[ModelSim]
WaveformGenerator = $SCRATCH_DIR/WaveformGenerator
WaveformGenerator_test = $SCRATCH_DIR/WaveformGenerator_test
[hdl]
ieee = $HDS_HOME/hdl_libs/ieee/hdl
std = $HDS_HOME/hdl_libs/std/hdl
WaveformGenerator = $HDS_PROJECT_DIR/../WaveformGenerator/hdl
WaveformGenerator_test = $HDS_PROJECT_DIR/../WaveformGenerator_test/hdl
[hds]
ieee = $HDS_HOME/hdl_libs/ieee/hds
std = $HDS_HOME/hdl_libs/std/hds
WaveformGenerator = $HDS_PROJECT_DIR/../WaveformGenerator/hds
WaveformGenerator_test = $HDS_PROJECT_DIR/../WaveformGenerator_test/hds
[library_type]
ieee = standard
std = standard
[shared]
others = $HDS_TEAM_HOME/shared.hdp

23
01-WaveformGenerator/Prefs/hds_team/shared.hdp Normal file
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[hds_settings]
version = 1
project_description = The standard HDS shared project
[hds]
ieee = $HDS_HOME/hdl_libs/ieee/hds
std = $HDS_HOME/hdl_libs/std/hds
synopsys = $HDS_HOME/hdl_libs/synopsys/hds
verilog = $HDS_HOME/hdl_libs/verilog/hds
vital2000 = $HDS_HOME/hdl_libs/vital2000/hds
[hdl]
ieee = $HDS_HOME/hdl_libs/ieee/hdl
std = $HDS_HOME/hdl_libs/std/hdl
synopsys = $HDS_HOME/hdl_libs/synopsys/hdl
verilog = $HDS_HOME/hdl_libs/verilog/hdl
vital2000 = $HDS_HOME/hdl_libs/vital2000/hdl
[library_type]
ieee = standard
std = standard
synopsys = standard
verilog = standard
vital2000 = standard

55
01-WaveformGenerator/Prefs/hds_team/v2018.1/hds_team_prefs Normal file
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VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm"
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VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository"
VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm"
VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm"
VMDsHdsRepository "sync://<host_name>:<port>/hds_scratch/hds_repository/hds_vm"
VMDsHdlRepository "sync://<host_name>:<port>/hds_scratch/hds_repository/hdl_vm"
VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm"
VMSvnHdlRepository ""
VMDefaultView 1
VMCurrentDesignHierarchyOnly 0
VMUserData 1
VMGeneratedHDL 0
VMVerboseMode 0
VMAlwaysEmpty 0
VMSetTZ 1
VMSymbol 1
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backupNameClashes 1
clearCaseMaster 0
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273
01-WaveformGenerator/Prefs/hds_team/v2018.1/title_block.tmpl Normal file
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55
01-WaveformGenerator/Prefs/hds_team/v2019.2/hds_team_prefs Normal file
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version "8.0"
RenoirTeamPreferences [
(BaseTeamPreferences
version "1.1"
verConcat 0
ttDGProps [
]
fcDGProps [
]
smDGProps [
]
asmDGProps [
]
bdDGProps [
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syDGProps [
]
)
(VersionControlTeamPreferences
version "1.1"
VMPlugin ""
VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository"
VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm"
VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm"
VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm"
VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository"
VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm"
VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm"
VMDsHdsRepository "sync://<host_name>:<port>/hds_scratch/hds_repository/hds_vm"
VMDsHdlRepository "sync://<host_name>:<port>/hds_scratch/hds_repository/hdl_vm"
VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm"
VMSvnHdlRepository ""
VMDefaultView 1
VMCurrentDesignHierarchyOnly 0
VMUserData 1
VMGeneratedHDL 0
VMVerboseMode 0
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273
01-WaveformGenerator/Prefs/hds_team/v2019.2/title_block.tmpl Normal file
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55
01-WaveformGenerator/Prefs/hds_team/v2019.3/hds_team_prefs Normal file
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273
01-WaveformGenerator/Prefs/hds_team/v2019.3/title_block.tmpl Normal file
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41
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01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/tasks/modelsim_simulate.tsk Normal file
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01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/tasks/prepare_for_synthesis.tsk Normal file
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114
01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/tasks/xilinx_project_navigator.tsk Normal file
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13
01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/text_files/new_document.txt Normal file
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FILE_NAMING_RULE: new_document.txt
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15
01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_architecture/architecture.vhd Normal file
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FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd
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17
01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_combined/combined.vhd Normal file
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FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd
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19
01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_configuration/configuration.vhd Normal file
View File

@ -0,0 +1,19 @@
FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd
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15
01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_entity/entity.vhd Normal file
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FILE_NAMING_RULE: %(entity_name)_entity.vhd
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16
01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_body/package_body.vhd Normal file
View File

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FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd
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18
01-WaveformGenerator/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_header/package_header.vhd Normal file
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@ -0,0 +1,18 @@
FILE_NAMING_RULE: %(entity_name)_pkg.vhd
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LIBRARY ieee;
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PACKAGE %(entity_name) IS
END %(entity_name);

6831
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41
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01-WaveformGenerator/Prefs/hds_user/v2018.1/tasks/modelsim_flow.tsk Normal file
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reffedTaskName "USER:ModelSim Compile"
)
(HDSTaskRef
TaskName "ModelSim Simulate"
bitmap ""
hasBitmap 1
tooltip ""
taskSettings [
]
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]
onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 3
reffedTaskName "USER:ModelSim Simulate"
)
]
)

96
01-WaveformGenerator/Prefs/hds_user/v2018.1/tasks/modelsim_simulate.tsk Normal file
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@ -0,0 +1,96 @@
version "1.1"
HDSTool (HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "ModelSim Simulate"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp"
hasBitmap 1
tooltip "Invokes the ModelSim Simulator"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"additionalToolArgs"
""
"captureOutput"
"0"
"customPrompt"
""
"initialDir"
""
"promptForRunSettings"
"1"
"runMethod"
"gui"
"runnableObject"
"ModelSimSimulator"
"runnableObjectType"
"tcl_plugin"
"useViewSpecific"
"0"
]
)
"TaskSetting"
(SettingsMap
settingsMap [
"Arguments"
""
"Arguments1"
"do controller.do"
"Arguments2"
"controller.do"
"Communication"
"1"
"DelaySelection"
"typ"
"GlitchGeneration"
"1"
"InitCmd"
"$SIMULATION_DIR\\IND.do"
"LogFile"
""
"RemoteHost"
""
"Resolution"
"ps"
"SdfDelay"
"typ"
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"UseGUI"
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"95"
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onShortcutBar 1
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 3
)

162
01-WaveformGenerator/Prefs/hds_user/v2018.1/tasks/prepare_for_synthesis.tsk Normal file
View File

@ -0,0 +1,162 @@
version "1.1"
HDSFlow (HDSFlow
TaskName "Prepare for Synthesis"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp"
hasBitmap 1
tooltip "generates a single file"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"flowSettingsDlg"
""
"taskInvocationScript"
""
]
)
]
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]
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onPulldownMenu 0
onToolbar 1
enabled 1
hierDepth 1
subTasks [
(HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "Generate"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp"
hasBitmap 1
tooltip "Performs generation of graphics files"
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"InternalTaskSetting"
(SettingsMap
settingsMap [
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""
"captureOutput"
"0"
"customPrompt"
""
"initialDir"
""
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"0"
"runMethod"
"gui"
"runnableObject"
"Generator"
"runnableObjectType"
"tcl_plugin"
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]
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]
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]
onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 1
)
(HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "Concatenate HDL"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_concatenate.bmp"
hasBitmap 1
tooltip "Appends all HDL files together"
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"InternalTaskSetting"
(SettingsMap
settingsMap [
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""
"captureOutput"
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"runnableObject"
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"TaskSetting"
(SettingsMap
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"%(concat_file)"
"outputVerilogFileExtension"
"v"
"outputVhdlFileExtension"
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""
]
)
]
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]
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enabled 1
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(HDSTool
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associatedFileExt ""
TaskName "Trim libraries"
bitmap "tool_default_tool.bmp"
hasBitmap 1
tooltip "comment out library declarations for singles file"
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)

163
01-WaveformGenerator/Prefs/hds_user/v2018.1/tasks/xilinx_project_navigator.tsk Normal file
View File

@ -0,0 +1,163 @@
version "1.1"
HDSFlow (HDSFlow
TaskName "Xilinx Project Navigator"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp"
hasBitmap 1
tooltip "Xilinx Flow"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"flowSettingsDlg"
""
"taskInvocationScript"
""
]
)
]
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]
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onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 1
subTasks [
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hasAssociatedFileExt 0
associatedFileExt ""
TaskName "Update.xise"
bitmap "tool_default_tool.bmp"
hasBitmap 1
tooltip "Update file references in the Xilnx project .xise file"
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"InternalTaskSetting"
(SettingsMap
settingsMap [
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"$CONCAT_DIR\\..\\..\\Scripts\\update_ise.pl $DESIGN_NAME.xise $CONCAT_DIR\\$DESIGN_NAME.vhd $CONCAT_DIR\\$DESIGN_NAME.ucf"
"captureOutput"
"1"
"customPrompt"
""
"initialDir"
"$ISE_WORK_DIR"
"promptForRunSettings"
"0"
"runMethod"
"gui"
"runnableObject"
"$HDS_HOME\\resources\\perl\\bin\\perl.exe"
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]
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(SettingsMap
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"FPGA Technology Setup Plug-in v2.0
For additional information, exceptions, compatibility issues and updates, visit SupportNet."
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(SettingsMap
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"False"
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"Standard"
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"True"
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"fg456"
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"-7"
"synthTool"
"Xilinx XST"
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""
"vendor"
"xilinx"
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]
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onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 3
)
]
)

13
01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/text_files/new_document.txt Normal file
View File

@ -0,0 +1,13 @@
FILE_NAMING_RULE: new_document.txt
DESCRIPTION_START
This is the default template used for the creation of Text Document files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
#
# Created:
# by - %(user).%(group) (%(host))
# at - %(time) %(date)
#
# using Mentor Graphics HDL Designer(TM) %(version)
#

15
01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_architecture/architecture.vhd Normal file
View File

@ -0,0 +1,15 @@
FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Architecture files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Architecture %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
%(architecture)

17
01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_combined/combined.vhd Normal file
View File

@ -0,0 +1,17 @@
FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd
DESCRIPTION_START
This is the default template used for the creation of combined VHDL Architecture and Entity files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Architecture %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
%(entity)
--
%(architecture)

19
01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_configuration/configuration.vhd Normal file
View File

@ -0,0 +1,19 @@
FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Configuration files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Configuration %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
CONFIGURATION %(entity_name)_config OF %(entity_name) IS
FOR %(arch_name)
END FOR;
END %(entity_name)_config;

15
01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_entity/entity.vhd Normal file
View File

@ -0,0 +1,15 @@
FILE_NAMING_RULE: %(entity_name)_entity.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Entity files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Entity %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
%(entity)

16
01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_package_body/package_body.vhd Normal file
View File

@ -0,0 +1,16 @@
FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Package Body files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Package Body %(library).%(unit)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
PACKAGE BODY %(entity_name) IS
END %(entity_name);

18
01-WaveformGenerator/Prefs/hds_user/v2018.1/templates/vhdl_package_header/package_header.vhd Normal file
View File

@ -0,0 +1,18 @@
FILE_NAMING_RULE: %(entity_name)_pkg.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Package Header files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Package Header %(library).%(unit)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE %(entity_name) IS
END %(entity_name);

6841
01-WaveformGenerator/Prefs/hds_user/v2019.2/hds_user_prefs Normal file
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File diff suppressed because it is too large Load Diff

162
01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/diamond_project_navigator.tsk Normal file
View File

@ -0,0 +1,162 @@
version "1.1"
HDSFlow (HDSFlow
TaskName "Diamond Project Navigator"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_lattice.bmp"
hasBitmap 1
tooltip "Diamond synthesis Flow"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"flowSettingsDlg"
""
"taskInvocationScript"
""
]
)
]
PreferedTasks [
]
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onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 1
subTasks [
(HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "Update.ldf"
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hasBitmap 1
tooltip "Update file references in the Diamond project .prjx file"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
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"$CONCAT_DIR\\..\\..\\Scripts\\update_diamond.pl $DESIGN_NAME.ldf $CONCAT_DIR\\$DESIGN_NAME.vhd $CONCAT_DIR\\$DESIGN_NAME.lpf"
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"1"
"customPrompt"
""
"initialDir"
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"gui"
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"$HDS_HOME\\resources\\perl\\bin\\perl.exe"
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onPulldownMenu 0
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)
(HDSTool
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associatedFileExt ""
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bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_lattice.bmp"
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(SettingsMap
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]
)

41
01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/generate.tsk Normal file
View File

@ -0,0 +1,41 @@
version "1.1"
HDSTool (HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "Generate"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp"
hasBitmap 1
tooltip "Performs generation of graphics files"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"additionalToolArgs"
""
"captureOutput"
"0"
"customPrompt"
""
"initialDir"
""
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"0"
"runMethod"
"gui"
"runnableObject"
"Generator"
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"tcl_plugin"
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]
onShortcutBar 1
onPulldownMenu 1
onToolbar 1
enabled 1
hierDepth 2
)

98
01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk Normal file
View File

@ -0,0 +1,98 @@
version "1.1"
HDSTool (HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "ModelSim Compile"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp"
hasBitmap 1
tooltip "Runs ModelSim compilation"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"additionalToolArgs"
""
"captureOutput"
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"tcl_plugin"
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"TaskSetting"
(SettingsMap
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""
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"$MODELSIM_HOME"
"logFile"
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onToolbar 0
enabled 1
hierDepth 1
)

83
01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk Normal file
View File

@ -0,0 +1,83 @@
version "1.1"
HDSFlow (HDSFlow
TaskName "ModelSim Flow"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp"
hasBitmap 1
tooltip "Generate and run entire ModelSim flow"
taskSettings [
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(SettingsMap
settingsMap [
"flowSettingsDlg"
""
"taskInvocationScript"
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preferedEnum 0
preferedSetting "$MODELSIM_HOME"
)
(preferedMap
preferedEnum 2
preferedSetting "ModelSim"
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onPulldownMenu 1
onToolbar 1
enabled 1
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taskSettings [
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]
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onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 1
reffedTaskName "USER:Generate"
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(HDSTaskRef
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hasBitmap 1
tooltip ""
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onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 1
reffedTaskName "USER:ModelSim Compile"
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(HDSTaskRef
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bitmap ""
hasBitmap 1
tooltip ""
taskSettings [
]
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]
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onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 3
reffedTaskName "USER:ModelSim Simulate"
)
]
)

98
01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk Normal file
View File

@ -0,0 +1,98 @@
version "1.1"
HDSTool (HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "ModelSim Simulate"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp"
hasBitmap 1
tooltip "Invokes the ModelSim Simulator"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"additionalToolArgs"
""
"captureOutput"
"0"
"customPrompt"
""
"initialDir"
""
"promptForRunSettings"
"1"
"runMethod"
"gui"
"runnableObject"
"ModelSimSimulator"
"runnableObjectType"
"tcl_plugin"
"useViewSpecific"
"0"
]
)
"TaskSetting"
(SettingsMap
settingsMap [
"Arguments"
""
"Arguments1"
"do controller.do"
"Arguments2"
"controller.do"
"Communication"
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"DelaySelection"
"typ"
"GlitchGeneration"
"1"
"InitCmd"
"$SIMULATION_DIR/waveformGen.do"
"LogFile"
""
"RemoteHost"
""
"Resolution"
"ps"
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"typ"
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"latest"
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"95"
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"$MODELSIM_HOME"
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]
)
]
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]
onShortcutBar 1
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 3
)

162
01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/prepare_for_synthesis.tsk Normal file
View File

@ -0,0 +1,162 @@
version "1.1"
HDSFlow (HDSFlow
TaskName "Prepare for Synthesis"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp"
hasBitmap 1
tooltip "generates a single file"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"flowSettingsDlg"
""
"taskInvocationScript"
""
]
)
]
PreferedTasks [
]
onShortcutBar 0
onPulldownMenu 0
onToolbar 1
enabled 1
hierDepth 1
subTasks [
(HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "Generate"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp"
hasBitmap 1
tooltip "Performs generation of graphics files"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"additionalToolArgs"
""
"captureOutput"
"0"
"customPrompt"
""
"initialDir"
""
"promptForRunSettings"
"0"
"runMethod"
"gui"
"runnableObject"
"Generator"
"runnableObjectType"
"tcl_plugin"
"useViewSpecific"
"0"
]
)
]
PreferedTasks [
]
onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 1
)
(HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "Concatenate HDL"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_concatenate.bmp"
hasBitmap 1
tooltip "Appends all HDL files together"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"additionalToolArgs"
""
"captureOutput"
"0"
"customPrompt"
""
"initialDir"
""
"promptForRunSettings"
"0"
"runMethod"
"gui"
"runnableObject"
"Concatenation"
"runnableObjectType"
"tcl_plugin"
"useViewSpecific"
"1"
]
)
"TaskSetting"
(SettingsMap
settingsMap [
"outputFileNameRoot"
"%(concat_file)"
"outputVerilogFileExtension"
"v"
"outputVhdlFileExtension"
"vhd"
"place"
"0"
"specifyDir"
""
]
)
]
PreferedTasks [
]
onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 1
)
(HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "Trim libraries"
bitmap "tool_default_tool.bmp"
hasBitmap 1
tooltip "comment out library declarations for singles file"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"additionalToolArgs"
".\\..\\..\\Scripts\\trimLibs.pl %(concat_file).vhd $DESIGN_NAME.vhd"
"captureOutput"
"1"
"customPrompt"
""
"initialDir"
"$CONCAT_DIR"
"promptForRunSettings"
"0"
"runMethod"
"gui"
"runnableObject"
"$HDS_HOME\\resources\\perl\\bin\\perl.exe"
"runnableObjectType"
"executable"
"useViewSpecific"
"0"
]
)
]
PreferedTasks [
]
onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 3
)
]
)

163
01-WaveformGenerator/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk Normal file
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@ -0,0 +1,163 @@
version "1.1"
HDSFlow (HDSFlow
TaskName "Xilinx Project Navigator"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp"
hasBitmap 1
tooltip "Xilinx Flow"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"flowSettingsDlg"
""
"taskInvocationScript"
""
]
)
]
PreferedTasks [
]
onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 1
subTasks [
(HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "Update.xise"
bitmap "tool_default_tool.bmp"
hasBitmap 1
tooltip "Update file references in the Xilnx project .xise file"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"additionalToolArgs"
"$CONCAT_DIR\\..\\..\\Scripts\\update_ise.pl $DESIGN_NAME.xise $CONCAT_DIR\\$DESIGN_NAME.vhd $CONCAT_DIR\\$DESIGN_NAME.ucf"
"captureOutput"
"1"
"customPrompt"
""
"initialDir"
"$ISE_WORK_DIR"
"promptForRunSettings"
"0"
"runMethod"
"gui"
"runnableObject"
"$HDS_HOME\\resources\\perl\\bin\\perl.exe"
"runnableObjectType"
"executable"
"useViewSpecific"
"0"
]
)
]
PreferedTasks [
]
onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 3
)
(HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "Xilinx Project navigator"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp"
hasBitmap 1
tooltip "Invokes the Xilinx ISE tool"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"additionalToolArgs"
"$DESIGN_NAME.xise"
"captureOutput"
"0"
"customPrompt"
""
"descriptiveName"
"FPGA Technology Setup Plugin"
"initialDir"
"$ISE_WORK_DIR"
"isHierarchical"
"0"
"needsSave"
"0"
"pluginInfo"
"FPGA Technology Setup Plug-in v2.0
For additional information, exceptions, compatibility issues and updates, visit SupportNet."
"pluginVersion"
"2.0"
"promptForRunSettings"
"0"
"runMethod"
"gui"
"runnableObject"
"$ISE_HOME\\bin\\nt64\\ise.exe"
"runnableObjectType"
"executable"
"useViewSpecific"
"0"
]
)
"TaskSetting"
(SettingsMap
settingsMap [
"InputFile"
"U:/ELN_board/Board/concat/cursor.vhd"
"RunFromPlugin"
"False"
"RunInteractiveFromPlugIn"
"True"
"createAsciiFile"
"False"
"createBinaryFile"
"False"
"createFiles"
"True"
"createScriptFile"
"False"
"device"
"xc2vp7"
"edifngcPath"
"U:/ELN_board/Board/concat/cursor.vhd"
"effortLevel"
"Standard"
"family"
"virtex2p"
"familyName"
"virtex2p"
"netlist"
"other"
"netlistDefaultView"
"True"
"package"
"fg456"
"simulationModelLanguage"
"Modelsim_VHDL"
"speed"
"-7"
"synthTool"
"Xilinx XST"
"ucfPath"
""
"vendor"
"xilinx"
]
)
]
PreferedTasks [
]
onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 3
)
]
)

13
01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/text_files/new_document.txt Normal file
View File

@ -0,0 +1,13 @@
FILE_NAMING_RULE: new_document.txt
DESCRIPTION_START
This is the default template used for the creation of Text Document files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
#
# Created:
# by - %(user).%(group) (%(host))
# at - %(time) %(date)
#
# using Mentor Graphics HDL Designer(TM) %(version)
#

15
01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd Normal file
View File

@ -0,0 +1,15 @@
FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Architecture files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Architecture %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
%(architecture)

17
01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd Normal file
View File

@ -0,0 +1,17 @@
FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd
DESCRIPTION_START
This is the default template used for the creation of combined VHDL Architecture and Entity files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Architecture %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
%(entity)
--
%(architecture)

19
01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd Normal file
View File

@ -0,0 +1,19 @@
FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Configuration files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Configuration %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
CONFIGURATION %(entity_name)_config OF %(entity_name) IS
FOR %(arch_name)
END FOR;
END %(entity_name)_config;

15
01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd Normal file
View File

@ -0,0 +1,15 @@
FILE_NAMING_RULE: %(entity_name)_entity.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Entity files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Entity %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
%(entity)

16
01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd Normal file
View File

@ -0,0 +1,16 @@
FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Package Body files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Package Body %(library).%(unit)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
PACKAGE BODY %(entity_name) IS
END %(entity_name);

18
01-WaveformGenerator/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd Normal file
View File

@ -0,0 +1,18 @@
FILE_NAMING_RULE: %(entity_name)_pkg.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Package Header files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Package Header %(library).%(unit)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE %(entity_name) IS
END %(entity_name);