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ARCHITECTURE studentVersion OF interpolatorCalculatePolynom IS
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BEGIN
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sampleOut <= (others => '0');
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END ARCHITECTURE studentVersion;
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ARCHITECTURE studentVersion OF interpolatorCoefficients IS
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BEGIN
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a <= (others => '0');
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b <= (others => '0');
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c <= (others => '0');
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d <= (others => '0');
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END ARCHITECTURE studentVersion;
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ARCHITECTURE studentVersion OF interpolatorShiftRegister IS
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BEGIN
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sample1 <= (others => '0');
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sample2 <= (others => '0');
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sample3 <= (others => '0');
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sample4 <= (others => '0');
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END ARCHITECTURE studentVersion;
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ARCHITECTURE studentVersion OF interpolatorTrigger IS
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BEGIN
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triggerOut <= '0';
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END ARCHITECTURE studentVersion;
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ARCHITECTURE studentVersion OF offsetToUnsigned IS
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BEGIN
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unsignedOut <= (others => '0');
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END ARCHITECTURE studentVersion;
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ARCHITECTURE studentVersion OF resizer IS
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BEGIN
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resizeOut <= (others => '0');
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END ARCHITECTURE studentVersion;
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ARCHITECTURE studentVersion OF sineTable IS
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signal phaseTableAddress : unsigned(tableAddressBitNb-1 downto 0);
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signal quarterSine : signed(sine'range);
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BEGIN
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phaseTableAddress <= phase(phase'high-2 downto phase'high-2-tableAddressBitNb+1);
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quarterTable: process(phaseTableAddress)
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begin
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case to_integer(phaseTableAddress) is
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when 0 => quarterSine <= to_signed(16#0000#, quarterSine'length);
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when 1 => quarterSine <= to_signed(16#18F9#, quarterSine'length);
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when 2 => quarterSine <= to_signed(16#30FB#, quarterSine'length);
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when 3 => quarterSine <= to_signed(16#471C#, quarterSine'length);
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when 4 => quarterSine <= to_signed(16#5A82#, quarterSine'length);
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when 5 => quarterSine <= to_signed(16#6A6D#, quarterSine'length);
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when 6 => quarterSine <= to_signed(16#7641#, quarterSine'length);
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when 7 => quarterSine <= to_signed(16#7D89#, quarterSine'length);
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when others => quarterSine <= (others => '-');
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end case;
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end process quarterTable;
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sine <= (others => '0');
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END ARCHITECTURE studentVersion;
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DIALECT atom VHDL_2008
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DIALECT atom VHDL_2008
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DIALECT atom VHDL_2008
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DIALECT atom VHDL_2008
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DIALECT atom VHDL_2008
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DIALECT atom VHDL_2008
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DIALECT atom VHDL_2008
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DIALECT atom VHDL_2008
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DIALECT atom VHDL_2008
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DIALECT atom VHDL_2008
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DIALECT atom VHDL_2008
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DIALECT atom VHDL_2008
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DIALECT atom VHDL_2008
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DIALECT atom VHDL_2008
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DIALECT atom VHDL_2008
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DIALECT atom VHDL_2008
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DIALECT atom VHDL_2008
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DIALECT atom VHDL_2008
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DIALECT atom VHDL_2008
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DIALECT atom VHDL_2008
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DIALECT atom VHDL_2008
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DIALECT atom VHDL_2008
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DIALECT atom VHDL_2008
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DIALECT atom VHDL_2008
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DIALECT atom VHDL_2008
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DEFAULT_ARCHITECTURE atom studentVersion
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DEFAULT_FILE atom interpolatorCalculatePolynom_studentVersion.vhd
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DEFAULT_ARCHITECTURE atom studentVersion
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DEFAULT_FILE atom interpolatorCoefficients_studentVersion.vhd
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DEFAULT_ARCHITECTURE atom studentVersion
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DEFAULT_FILE atom interpolatorShiftRegister_studentVersion.vhd
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DEFAULT_ARCHITECTURE atom studentVersion
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DEFAULT_FILE atom interpolatorTrigger_studentVersion.vhd
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DEFAULT_ARCHITECTURE atom studentVersion
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DEFAULT_FILE atom offsetToUnsigned_studentVersion.vhd
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DEFAULT_ARCHITECTURE atom studentVersion
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DEFAULT_FILE atom resizer_studentVersion.vhd
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DEFAULT_FILE atom sine@gen/struct.bd
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DEFAULT_ARCHITECTURE atom struct
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TOP_MARKER atom 1
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DEFAULT_ARCHITECTURE atom studentVersion
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DEFAULT_FILE atom sineTable_studentVersion.vhd
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1486
02-SplineInterpolator/SplineInterpolator/hds/resizer/symbol.sb
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02-SplineInterpolator/SplineInterpolator/hds/resizer/symbol.sb
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02-SplineInterpolator/SplineInterpolator/hds/sine@gen/struct.bd
Normal file
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02-SplineInterpolator/SplineInterpolator/hds/sine@gen/struct.bd
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02-SplineInterpolator/SplineInterpolator/hds/sine@gen/symbol.sb
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02-SplineInterpolator/SplineInterpolator/hds/sine@gen/symbol.sb
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02-SplineInterpolator/SplineInterpolator/hds/sine@table/symbol.sb
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02-SplineInterpolator/SplineInterpolator/hds/sine@table/symbol.sb
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Load Diff
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