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github-classroom[bot]
2024-02-23 13:01:05 +00:00
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commit d212040c30
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02-SplineInterpolator/SplineInterpolator_test/hdl/sineGen_tester_test.vhd Normal file
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ARCHITECTURE test OF sineGen_tester IS
constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
signal sClock: std_uLogic := '1';
BEGIN
------------------------------------------------------------------------------
-- clock and reset
sClock <= not sClock after clockPeriod/2;
clock <= transport sClock after clockPeriod*9/10;
reset <= '1', '0' after 2*clockPeriod;
------------------------------------------------------------------------------
-- controls
step <= to_unsigned(1, step'length);
END ARCHITECTURE test;

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02-SplineInterpolator/SplineInterpolator_test/hds/.hdlsidedata/_sineGen_tester_test.vhd._fpf Normal file
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DIALECT atom VHDL_2008

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02-SplineInterpolator/SplineInterpolator_test/hds/.hdlsidedata/_sinegen_tb_entity.vhg._fpf Normal file
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DIALECT atom VHDL_2008

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02-SplineInterpolator/SplineInterpolator_test/hds/.hdlsidedata/_sinegen_tb_struct.vhg._fpf Normal file
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DIALECT atom VHDL_2008

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02-SplineInterpolator/SplineInterpolator_test/hds/.hdlsidedata/_sinegen_tester_entity.vhg._fpf Normal file
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DIALECT atom VHDL_2008

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02-SplineInterpolator/SplineInterpolator_test/hds/_sinegen_tb._epf Normal file
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DEFAULT_FILE atom sine@gen_tb/struct.bd
DEFAULT_ARCHITECTURE atom struct
TOP_MARKER atom 1

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02-SplineInterpolator/SplineInterpolator_test/hds/_sinegen_tester._epf Normal file
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DEFAULT_ARCHITECTURE atom test
DEFAULT_FILE atom sineGen_tester_test.vhd

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02-SplineInterpolator/SplineInterpolator_test/hds/sine@gen_tb/struct.bd Normal file
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02-SplineInterpolator/SplineInterpolator_test/hds/sine@gen_tb/symbol.sb Normal file
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02-SplineInterpolator/SplineInterpolator_test/hds/sine@gen_tester/interface Normal file
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