Initial commit

02-SplineInterpolator/SplineInterpolator_test/hdl/sineGen_tester_test.vhd

@@ -0,0 +1,19 @@
+ARCHITECTURE test OF sineGen_tester IS
+
+  constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
+  signal sClock: std_uLogic := '1';
+
+BEGIN
+
+  ------------------------------------------------------------------------------
+                                                              -- clock and reset
+  sClock <= not sClock after clockPeriod/2;
+  clock <= transport sClock after clockPeriod*9/10;
+
+  reset <= '1', '0' after 2*clockPeriod;
+
+  ------------------------------------------------------------------------------
+                                                                     -- controls
+  step <= to_unsigned(1, step'length);
+
+END ARCHITECTURE test;