Initial commit
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github-classroom[bot]
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@ -0,0 +1,261 @@
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LIBRARY Common_test;
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USE Common_test.testUtils.all;
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ARCHITECTURE test OF ahbGpio_tester IS
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-- reset and clock
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constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
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signal clock_int: std_uLogic := '1';
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signal reset_int: std_uLogic;
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-- test information
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signal noteTopSeparator : string(1 to 80) := (others => '-');
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signal errorTopSeparator : string(1 to 80) := (others => '#');
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signal bottomSeparator : string(1 to 80) := (others => '.');
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signal indentation : string(1 to 2) := (others => ' ');
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signal noteInformation : string(1 to 9) := (others => ' ');
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signal errorInformation : string(1 to 10) := (others => ' ');
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signal failureInformation : string(1 to 12) := (others => ' ');
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signal testInformation : string(1 to 50) := (others => ' ');
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-- register definition
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constant peripheralBaseAddress: natural := 2**4;
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constant dataRegisterAddress: natural := 0;
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constant outputEnableRegisterAddress: natural := 1;
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-- AMBA bus access
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signal registerAddress: natural;
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signal registerData: integer;
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signal registerWrite: std_uLogic;
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signal registerRead: std_uLogic;
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signal writeFlag, readFlag, readFlag1: std_uLogic;
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signal writeData, readData: integer;
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-- GPIO access
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signal ioData: integer;
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signal ioMask: integer;
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BEGIN
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------------------------------------------------------------------------------
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-- reset and clock
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reset_int <= '1', '0' after 2*clockPeriod;
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hReset_n <= not(reset_int);
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clock_int <= not clock_int after clockPeriod/2;
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hClk <= transport clock_int after clockPeriod*9.0/10.0;
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------------------------------------------------------------------------------
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-- test sequence
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testSequence: process
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begin
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registerAddress <= 0;
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registerData <= 0;
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registerWrite <= '0';
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registerRead <= '0';
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ioData <= 0;
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ioMask <= 0;
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wait for 100 ns;
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----------------------------------------------------------------------------
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-- simple test
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-- write en mask
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testInformation <= pad("Writing data on the GPIO", testInformation'length);
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wait for 0 ns;
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assert false
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report
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noteTopSeparator & cr &
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noteInformation & indentation & testInformation & cr &
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noteInformation & bottomSeparator
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severity note;
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ioData <= 16#AA#;
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ioMask <= 16#0F#; wait for 0 ns;
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registerAddress <= outputEnableRegisterAddress;
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registerData <= ioMask;
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registerWrite <= '1', '0' after clockPeriod/2;
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wait for 4*clockPeriod;
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-- write output data 55h
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registerAddress <= dataRegisterAddress;
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registerData <= 16#55#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for 4*clockPeriod;
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assert io = x"A5"
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report
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errorTopSeparator & cr &
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noteInformation & indentation & "IO data not as expected" & cr &
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noteInformation & bottomSeparator
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severity error;
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-- read data
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testInformation <= pad("Reading data from the GPIO", testInformation'length);
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wait for 0 ns;
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assert false
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report
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noteTopSeparator & cr &
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noteInformation & indentation & testInformation & cr &
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noteInformation & bottomSeparator
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severity note;
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registerAddress <= dataRegisterAddress;
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registerRead <= '1', '0' after clockPeriod;
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for index in 1 to 4 loop
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wait until rising_edge(clock_int);
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end loop;
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assert readData = 16#A5#
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report
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errorTopSeparator & cr &
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noteInformation & indentation & "read data not as expected" & cr &
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noteInformation & bottomSeparator
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severity error;
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wait for 100 ns;
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----------------------------------------------------------------------------
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-- test with a different base address
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-- write en mask
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testInformation <= pad(
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"Writing data to a different base address", testInformation'length
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);
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wait for 0 ns;
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assert false
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report
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noteTopSeparator & cr &
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noteInformation & indentation & testInformation & cr &
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noteInformation & bottomSeparator
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severity note;
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ioData <= 16#AA#;
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ioMask <= 16#F0#; wait for 0 ns;
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registerAddress <= peripheralBaseAddress + outputEnableRegisterAddress;
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registerData <= ioMask;
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registerWrite <= '1', '0' after clockPeriod;
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wait for 4*clockPeriod;
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-- write output data 55h
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registerAddress <= peripheralBaseAddress + dataRegisterAddress;
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registerData <= 16#55#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for 4*clockPeriod;
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-- read data
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registerAddress <= peripheralBaseAddress + dataRegisterAddress;
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registerRead <= '1', '0' after clockPeriod;
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for index in 1 to 4 loop
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wait until rising_edge(clock_int);
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end loop;
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assert readData = 16#5A#
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report
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errorTopSeparator & cr &
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noteInformation & indentation & "read data not as expected" & cr &
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noteInformation & bottomSeparator
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severity error;
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wait for 4*clockPeriod;
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----------------------------------------------------------------------------
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-- access back to back
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-- write en mask
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testInformation <= pad("Accessing at full speed", testInformation'length);
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wait for 0 ns;
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assert false
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report
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noteTopSeparator & cr &
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noteInformation & indentation & testInformation & cr &
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noteInformation & bottomSeparator
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severity note;
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wait until rising_edge(clock_int);
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ioData <= 16#AA#;
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ioMask <= 16#0F#; wait for 0 ns;
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registerAddress <= outputEnableRegisterAddress;
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registerData <= ioMask;
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registerWrite <= '1' after clockPeriod/4, '0' after clockPeriod/2;
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-- write output data 55h
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wait until rising_edge(clock_int);
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registerAddress <= dataRegisterAddress;
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registerData <= 16#55#;
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registerWrite <= '1' after clockPeriod/4, '0' after clockPeriod/2;
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-- read data
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wait until rising_edge(clock_int);
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registerAddress <= dataRegisterAddress;
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registerRead <= '1' after clockPeriod/4, '0' after clockPeriod/2;
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for index in 1 to 4 loop
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wait until rising_edge(clock_int);
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end loop;
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assert readData = 16#A5#
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report
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errorTopSeparator & cr &
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noteInformation & indentation & "read data not as expected" & cr &
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noteInformation & bottomSeparator
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severity error;
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wait for 4*clockPeriod;
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-- end of simulation
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wait for 100 ns;
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testInformation <= pad("End of tests", testInformation'length);
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wait for 0 ns;
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assert false
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report
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noteTopSeparator & cr &
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failureInformation & indentation & testInformation & cr &
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failureInformation & bottomSeparator
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severity failure;
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wait;
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end process testSequence;
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------------------------------------------------------------------------------
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-- AMBA bus access
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-- phase 1: address and controls
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busAccess1: process
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variable writeAccess: boolean := false;
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begin
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wait on reset_int, registerWrite, registerRead;
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if falling_edge(reset_int) then
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hAddr <= (others => '-');
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hTrans <= transIdle;
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hSel <= '0';
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writeFlag <= '0';
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end if;
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if rising_edge(registerWrite) or rising_edge(registerRead) then
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writeAccess := false;
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if rising_edge(registerWrite) then
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writeAccess := true;
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end if;
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wait until rising_edge(clock_int);
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hAddr <= to_unsigned(registerAddress, hAddr'length),
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(others => '-') after clockPeriod + 1 ns;
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hTrans <= transNonSeq, transIdle after clockPeriod + 1 ns;
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hSel <= '1', '0' after clockPeriod + 1 ns;
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if writeAccess then
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writeFlag <= '1', '0' after clockPeriod + 1 ns;
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writeData <= registerData;
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else
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readFlag <= '1', '0' after clockPeriod + 1 ns;
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end if;
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end if;
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end process busAccess1;
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hWrite <= writeFlag;
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-- phase 2: data write
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busAccess2: process
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begin
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wait until rising_edge(clock_int);
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hWData <= (others => '-');
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readFlag1 <= '0';
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if writeFlag = '1' then
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hWData <= std_uLogic_vector(to_signed(writeData, hWData'length));
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end if;
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readFlag1 <= readFlag;
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end process busAccess2;
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-- phase 3: data read
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busAccess3: process
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begin
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wait until rising_edge(clock_int);
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if readFlag1 = '1' then
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readData <= to_integer(to_01(unsigned(hRData)));
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end if;
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end process busAccess3;
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------------------------------------------------------------------------------
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-- GPIO access
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linesAccess: process(ioData, ioMask)
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variable ioDataVector: unsigned(io'range);
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variable ioMaskVector: unsigned(io'range);
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begin
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ioDataVector := to_unsigned(ioData, ioDataVector'length);
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ioMaskVector := to_unsigned(ioMask, ioMaskVector'length);
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for index in io'range loop
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if ioMaskVector(index) = '1' then
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io(index) <= 'Z';
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else
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io(index) <= ioDataVector(index);
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end if;
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end loop;
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end process;
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END ARCHITECTURE test;
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@ -0,0 +1,330 @@
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LIBRARY Common_test;
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USE Common_test.testUtils.all;
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ARCHITECTURE test OF ahbUart_tester IS
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-- reset and clock
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constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
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signal clock_int: std_uLogic := '1';
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signal reset_int: std_uLogic;
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-- test information
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signal noteTopSeparator : string(1 to 80) := (others => '-');
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signal errorTopSeparator : string(1 to 80) := (others => '#');
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signal bottomSeparator : string(1 to 80) := (others => '.');
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signal indentation : string(1 to 2) := (others => ' ');
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signal noteInformation : string(1 to 9) := (others => ' ');
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signal errorInformation : string(1 to 10) := (others => ' ');
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signal failureInformation : string(1 to 12) := (others => ' ');
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signal testInformation : string(1 to 50) := (others => ' ');
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-- register definition
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constant dataRegisterAddress: natural := 0;
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constant controlRegisterAddress: natural := 1;
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constant scalerRegisterAddress: natural := 2;
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constant statusRegisterAddress: natural := 1;
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constant statusValidAddress: natural := 0;
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constant valueRegisterAddress: natural := 1;
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-- AMBA bus access
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signal registerAddress: natural;
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signal registerData: integer;
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signal registerWrite: std_uLogic;
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signal registerRead: std_uLogic;
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signal writeFlag, readFlag, readFlag1: std_uLogic;
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signal writeData, readData: integer;
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-- UART access
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constant baudPeriodNb: positive := 4;
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signal uartData: integer;
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signal uartSend: std_uLogic;
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BEGIN
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------------------------------------------------------------------------------
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-- reset and clock
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reset_int <= '1', '0' after 2*clockPeriod;
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hReset_n <= not(reset_int);
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clock_int <= not clock_int after clockPeriod/2;
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hClk <= transport clock_int after clockPeriod*9.0/10.0;
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------------------------------------------------------------------------------
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-- test sequence
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testSequence: process
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begin
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registerAddress <= 0;
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registerData <= 0;
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registerWrite <= '0';
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registerRead <= '0';
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uartSend <= '0';
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wait for 1 us;
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-- write baud rate
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testInformation <= pad("Writing baud rate", testInformation'length);
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wait for 0 ns;
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assert false
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report
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noteTopSeparator & cr &
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noteInformation & indentation & testInformation & cr &
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noteInformation & bottomSeparator
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severity note;
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registerAddress <= scalerRegisterAddress;
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registerData <= baudPeriodNb;
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registerWrite <= '1', '0' after clockPeriod;
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wait for 4*clockPeriod;
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-- write Tx data 55h
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testInformation <= pad("Writing Tx data", testInformation'length);
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wait for 0 ns;
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assert false
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report
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noteTopSeparator & cr &
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noteInformation & indentation & testInformation & cr &
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noteInformation & bottomSeparator
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severity note;
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registerAddress <= dataRegisterAddress;
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registerData <= 16#55#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for 20*baudPeriodNb*clockPeriod;
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-- write Tx data 0Fh
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testInformation <= (others => ' ');
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wait for 1 ns;
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testInformation <= pad("Writing Tx data", testInformation'length);
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wait for 0 ns;
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assert false
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report
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noteTopSeparator & cr &
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noteInformation & indentation & testInformation & cr &
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noteInformation & bottomSeparator
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severity note;
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registerAddress <= dataRegisterAddress;
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registerData <= 16#0F#;
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registerWrite <= '1', '0' after clockPeriod;
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wait for 4*clockPeriod;
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-- read status
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testInformation <= pad("Reading status", testInformation'length);
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wait for 0 ns;
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assert false
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report
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noteTopSeparator & cr &
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noteInformation & indentation & testInformation & cr &
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noteInformation & bottomSeparator
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severity note;
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registerAddress <= statusRegisterAddress;
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registerRead <= '1', '0' after clockPeriod;
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for index in 1 to 4 loop
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wait until rising_edge(clock_int);
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end loop;
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assert readData = 16#02#
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report
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errorTopSeparator & cr &
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errorInformation & indentation &
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"expected status sending flag" & cr &
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errorInformation & bottomSeparator
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severity error;
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wait for 12*baudPeriodNb*clockPeriod;
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-- read status
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testInformation <= (others => ' ');
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wait for 1 ns;
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testInformation <= pad("Reading status", testInformation'length);
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wait for 0 ns;
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assert false
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report
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noteTopSeparator & cr &
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noteInformation & indentation & testInformation & cr &
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noteInformation & bottomSeparator
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severity note;
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registerRead <= '1', '0' after clockPeriod;
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for index in 1 to 4 loop
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wait until rising_edge(clock_int);
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end loop;
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assert readData = 16#00#
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report
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errorTopSeparator & cr &
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errorInformation & indentation &
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"expected no flag" & cr &
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errorInformation & bottomSeparator
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severity error;
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wait for 20*baudPeriodNb*clockPeriod;
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-- receive AAh
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testInformation <= pad("Receiving Rx data", testInformation'length);
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wait for 0 ns;
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assert false
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report
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noteTopSeparator & cr &
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noteInformation & indentation & testInformation & cr &
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noteInformation & bottomSeparator
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severity note;
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uartData <= 16#AA#;
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uartSend <= '1', '0' after clockPeriod;
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wait for 4*clockPeriod;
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-- read status
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testInformation <= pad("Reading status", testInformation'length);
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wait for 0 ns;
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assert false
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report
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noteTopSeparator & cr &
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noteInformation & indentation & testInformation & cr &
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noteInformation & bottomSeparator
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severity note;
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registerAddress <= statusRegisterAddress;
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registerRead <= '1', '0' after clockPeriod;
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for index in 1 to 4 loop
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wait until rising_edge(clock_int);
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end loop;
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assert readData = 16#04#
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report
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errorTopSeparator & cr &
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errorInformation & indentation &
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"expected status receiving flag" & cr &
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errorInformation & bottomSeparator
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severity error;
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wait for 10*baudPeriodNb*clockPeriod;
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-- read status again
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testInformation <= (others => ' ');
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wait for 1 ns;
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testInformation <= pad("Reading status", testInformation'length);
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wait for 0 ns;
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assert false
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report
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noteTopSeparator & cr &
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noteInformation & indentation & testInformation & cr &
|
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noteInformation & bottomSeparator
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severity note;
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registerRead <= '1', '0' after clockPeriod;
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for index in 1 to 4 loop
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wait until rising_edge(clock_int);
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end loop;
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assert readData = 16#01#
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report
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errorTopSeparator & cr &
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errorInformation & indentation &
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"expected status data available flag" & cr &
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errorInformation & bottomSeparator
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severity error;
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wait for 4*clockPeriod;
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-- read data
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testInformation <= pad("Reading data", testInformation'length);
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wait for 0 ns;
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assert false
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report
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noteTopSeparator & cr &
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noteInformation & indentation & testInformation & cr &
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||||
noteInformation & bottomSeparator
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severity note;
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registerAddress <= dataRegisterAddress;
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registerRead <= '1', '0' after clockPeriod;
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for index in 1 to 4 loop
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wait until rising_edge(clock_int);
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end loop;
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assert readData = 16#AA#
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report
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errorTopSeparator & cr &
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errorInformation & indentation & "read data not as expected" & cr &
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errorInformation & bottomSeparator
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severity error;
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wait for 4*clockPeriod;
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-- read status
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testInformation <= pad("Reading status", testInformation'length);
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wait for 0 ns;
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assert false
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report
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noteTopSeparator & cr &
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noteInformation & indentation & testInformation & cr &
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||||
noteInformation & bottomSeparator
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||||
severity note;
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||||
registerAddress <= statusRegisterAddress;
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registerRead <= '1', '0' after clockPeriod;
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for index in 1 to 4 loop
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wait until rising_edge(clock_int);
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end loop;
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assert readData = 16#00#
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||||
report
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||||
errorTopSeparator & cr &
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||||
errorInformation & indentation &
|
||||
"expected no flag" & cr &
|
||||
errorInformation & bottomSeparator
|
||||
severity error;
|
||||
wait for 4*clockPeriod;
|
||||
-- end of simulation
|
||||
wait for 100 ns;
|
||||
testInformation <= pad("End of tests", testInformation'length);
|
||||
wait for 0 ns;
|
||||
assert false
|
||||
report
|
||||
noteTopSeparator & cr &
|
||||
failureInformation & indentation & testInformation & cr &
|
||||
failureInformation & bottomSeparator
|
||||
severity failure;
|
||||
wait;
|
||||
end process testSequence;
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
-- AMBA bus access
|
||||
-- phase 1: address and controls
|
||||
busAccess1: process
|
||||
variable writeAccess: boolean := false;
|
||||
begin
|
||||
wait on reset_int, registerWrite, registerRead;
|
||||
if falling_edge(reset_int) then
|
||||
hAddr <= (others => '-');
|
||||
hTrans <= transIdle;
|
||||
hSel <= '0';
|
||||
writeFlag <= '0';
|
||||
end if;
|
||||
if rising_edge(registerWrite) or rising_edge(registerRead) then
|
||||
writeAccess := false;
|
||||
if rising_edge(registerWrite) then
|
||||
writeAccess := true;
|
||||
end if;
|
||||
wait until rising_edge(clock_int);
|
||||
hAddr <= to_unsigned(registerAddress, hAddr'length),
|
||||
(others => '-') after clockPeriod + 1 ns;
|
||||
hTrans <= transNonSeq, transIdle after clockPeriod + 1 ns;
|
||||
hSel <= '1', '0' after clockPeriod + 1 ns;
|
||||
if writeAccess then
|
||||
writeFlag <= '1', '0' after clockPeriod + 1 ns;
|
||||
writeData <= registerData;
|
||||
else
|
||||
readFlag <= '1', '0' after clockPeriod + 1 ns;
|
||||
end if;
|
||||
end if;
|
||||
end process busAccess1;
|
||||
|
||||
hWrite <= writeFlag;
|
||||
-- phase 2: data write
|
||||
busAccess2: process
|
||||
begin
|
||||
wait until rising_edge(clock_int);
|
||||
hWData <= (others => '-');
|
||||
readFlag1 <= '0';
|
||||
if writeFlag = '1' then
|
||||
hWData <= std_uLogic_vector(to_signed(writeData, hWData'length));
|
||||
end if;
|
||||
readFlag1 <= readFlag;
|
||||
end process busAccess2;
|
||||
-- phase 3: data read
|
||||
busAccess3: process
|
||||
begin
|
||||
wait until rising_edge(clock_int);
|
||||
if readFlag1 = '1' then
|
||||
readData <= to_integer(to_01(unsigned(hRData)));
|
||||
end if;
|
||||
end process busAccess3;
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
-- UART access
|
||||
sendByte: process
|
||||
variable serialData: unsigned(7 downto 0);
|
||||
begin
|
||||
-- send stop bit
|
||||
RxD <= '1';
|
||||
-- get new word
|
||||
wait until rising_edge(uartSend);
|
||||
serialData := to_unsigned(uartData, serialData'length);
|
||||
-- send start bit
|
||||
RxD <= '0';
|
||||
wait for baudPeriodNb * clockPeriod;
|
||||
-- send data bits
|
||||
for index in serialData'reverse_range loop
|
||||
RxD <= serialData(index);
|
||||
wait for baudPeriodNb * clockPeriod;
|
||||
end loop;
|
||||
end process sendByte;
|
||||
|
||||
END ARCHITECTURE test;
|
||||
@ -0,0 +1,74 @@
|
||||
LIBRARY std;
|
||||
USE std.TEXTIO.all;
|
||||
LIBRARY Common_test;
|
||||
USE Common_test.testUtils.all;
|
||||
|
||||
ARCHITECTURE RTL OF uvmAhbDriver IS
|
||||
|
||||
constant flipflopDelay: time := 1 ns;
|
||||
|
||||
signal hAddr1, hWData1, hWData2: natural := 0;
|
||||
signal hWrite1, hWrite2, hRead1, hRead2: std_ulogic := '0';
|
||||
|
||||
BEGIN
|
||||
------------------------------------------------------------------------------
|
||||
-- reset and clock
|
||||
hReset_n <= not(reset);
|
||||
hClk <= clock;
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
-- interpret transaction
|
||||
interpretTransaction: process(driverTransaction)
|
||||
variable my_line : line;
|
||||
variable command_part : line;
|
||||
begin
|
||||
write(my_line, driverTransaction);
|
||||
read_first(my_line, command_part);
|
||||
if command_part.all = "write" then
|
||||
read_first(my_line, command_part);
|
||||
hAddr1 <= sscanf(command_part.all);
|
||||
read_first(my_line, command_part);
|
||||
hWData1 <= sscanf(command_part.all);
|
||||
hWrite1 <= '1', '0' after 1 ns;
|
||||
elsif command_part.all = "read" then
|
||||
read_first(my_line, command_part);
|
||||
hAddr1 <= sscanf(command_part.all);
|
||||
hRead1 <= '1', '0' after 1 ns;
|
||||
end if;
|
||||
deallocate(my_line);
|
||||
end process interpretTransaction;
|
||||
-- expand pulses to the next clock
|
||||
expandReadWrite: process
|
||||
begin
|
||||
hRead2 <= '0';
|
||||
hWrite2 <= '0';
|
||||
wait on hRead1, hWrite1;
|
||||
hRead2 <= hRead1;
|
||||
hWrite2 <= hWrite1;
|
||||
wait until rising_edge(clock);
|
||||
end process expandReadWrite;
|
||||
-- delay signals 1 or 2 clock periods
|
||||
synchAccess: process(reset, clock)
|
||||
begin
|
||||
if reset = '1' then
|
||||
hAddr <= (others => '0');
|
||||
hWData2 <= 0;
|
||||
hWData <= (others => '0');
|
||||
hWrite <= '0';
|
||||
hSel <= '0';
|
||||
hTrans <= transIdle;
|
||||
elsif rising_edge(clock) then
|
||||
hAddr <= to_unsigned(hAddr1, hAddr'length) after flipflopDelay;
|
||||
hWData2 <= hWData1;
|
||||
hWData <= std_ulogic_vector(to_unsigned(hWData2, hWData'length)) after flipflopDelay;
|
||||
hWrite <= hWrite2 after flipflopDelay;
|
||||
hSel <= hWrite2 or hRead2 after flipflopDelay;
|
||||
if (hWrite2 = '1') or (hRead2 = '1') then
|
||||
hTrans <= transNonSeq after flipflopDelay;
|
||||
else
|
||||
hTrans <= transIdle after flipflopDelay;
|
||||
end if;
|
||||
end if;
|
||||
end process synchAccess;
|
||||
|
||||
END ARCHITECTURE RTL;
|
||||
@ -0,0 +1,49 @@
|
||||
LIBRARY Common_test;
|
||||
USE Common_test.testUtils.all;
|
||||
|
||||
ARCHITECTURE RTL OF uvmAhbMonitor IS
|
||||
|
||||
signal addressReg: unsigned(hAddr'range);
|
||||
signal writeReg: std_ulogic;
|
||||
signal readReg: std_ulogic;
|
||||
|
||||
BEGIN
|
||||
------------------------------------------------------------------------------
|
||||
-- register address and controls
|
||||
storeControls: process(hReset_n, hClk)
|
||||
begin
|
||||
if not(hReset_n) = '1' then
|
||||
addressReg <= (others => '0');
|
||||
writeReg <= '0';
|
||||
readReg <= '0';
|
||||
elsif rising_edge(hClk) then
|
||||
writeReg <= '0';
|
||||
readReg <= '0';
|
||||
if (hSel = '1') and (hTrans = transNonSeq) then
|
||||
addressReg <= hAddr(addressReg'range);
|
||||
writeReg <= hWrite;
|
||||
readReg <= not hWrite;
|
||||
end if;
|
||||
end if;
|
||||
end process storeControls;
|
||||
-- monitor acesses
|
||||
reportBusAccess: process(hReset_n, hClk)
|
||||
begin
|
||||
if not(hReset_n) = '1' then
|
||||
monitorTransaction <= pad( false, ' ', monitorTransaction'length, "idle");
|
||||
elsif rising_edge(hClk) then
|
||||
if readReg = '1' then
|
||||
monitorTransaction <= pad(
|
||||
false, ' ', monitorTransaction'length,
|
||||
"read " & sprintf("%04X", addressReg) & ' ' & sprintf("%04X", hRData)
|
||||
);
|
||||
elsif writeReg = '1' then
|
||||
monitorTransaction <= pad(
|
||||
false, ' ', monitorTransaction'length,
|
||||
"written " & sprintf("%04X", addressReg) & ' ' & sprintf("%04X", hWData)
|
||||
);
|
||||
end if;
|
||||
end if;
|
||||
end process reportBusAccess;
|
||||
|
||||
END ARCHITECTURE RTL;
|
||||
Reference in New Issue
Block a user