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6031
06-07-08-09-SystemOnChip/Board/concat/concatenated.vhd
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6031
06-07-08-09-SystemOnChip/Board/concat/concatenated.vhd
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File diff suppressed because it is too large
Load Diff
334
06-07-08-09-SystemOnChip/Board/concat/systemOnChip.lpf
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334
06-07-08-09-SystemOnChip/Board/concat/systemOnChip.lpf
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@ -0,0 +1,334 @@
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### For reference, see TN1262 / FPGA-TN-02032
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# .lpf file format is not really documented by Lattice, normally generated through Diamond
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################
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#### sysCONFIG
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################
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# The BLOCK commands disable tracing of paths within clock domains (impacting overall timing score)
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# It can also be used on paths if the TRACE should not consider the clock domain crossing
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# like : BLOCK PATH FROM CLKNET "CLK_A" TO CLKNET "CLK_B" ;
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BLOCK RESETPATHS ;
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BLOCK ASYNCPATHS ;
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BLOCK JTAGPATHS ;
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BLOCK RD_DURING_WR_PATHS ;
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# Not comprehensive
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# dflt : CONFIG_IOVOLTAGE 1.2, 1.5, 1.8, 2.5(dflt), 3.3 voltage is 3.3V
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# dflt : COMPRESS_CONFIG OFF (dflt), ON no bitstream compression
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# mod : MCCLK_FREQ 2.4, 4.8, 9.7, 19.4, 38.8, 62 NOR program read @ 62MHz
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# mod : MASTER_SPI_PORT DISABLE (dflt), ENABLE master SPI port stays SPI and not GPIOs, other mods disabled by dflt
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# dflt : BACKGROUND_RECONFIG - no soft ERC when hot-loading bitstream (due to cosmic rays)
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# dflt : DONE_PULL ON (dflt), OFF IPU on DONE pin
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# dflt : DONE_EX OFF (dflt), ON not delaying end of the configuration (used for daisy chaining FPGAs)
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# mod : DONE_OD OFF (dflt), ON DONE pin as open-drain instead of push-pull
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# dflt : CONFIG_SECURE OFF (dflt), ON allows external access to current program
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# mod : CONFIG_MODE JTAG (dflt), SSPI, SPI_SERIAL, SPI_DUAL, SPI_QUAD, SLAVE_PARALLEL, SLAVE_SERIAL
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# which bus and mode is used to load configuration (for the Lattic IDE)
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# dflt : TRANSFR OFF (dflt), ON if using TransFR tool from Lattice
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# dflt : WAKE_UP 4 (set DONE=1 before starting user code, dflt for DONE_EX=ON)
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# 21 (set DONE=1 once FPGA is already running user code, dflt for DONE_EX=OFF)
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# mod : INBUF ON, OFF disable unused input buffers (not sure it impacts the ECP5 family)
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SYSCONFIG MCCLK_FREQ=62 MASTER_SPI_PORT=ENABLE DONE_OD=ON CONFIG_MODE=SPI_QUAD INBUF=OFF CONFIG_IOVOLTAGE=3.3 ;
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IOBUF ALLPORTS IO_TYPE=LVCMOS33 ;
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################
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#### Labs DB
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################
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### Clock and reset ###
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#INPUT_SETUP ALLPORTS 50.000000 ns HOLD 10.000000 ns CLKPORT "CLK" ;
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#INPUT_SETUP PORT "nRST" 50.000000 ns CLKPORT "CLK" ;
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FREQUENCY PORT "clock" 100.000000 MHz ;
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LOCATE COMP "clock" SITE "K16" ;
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IOBUF PORT "clock" PULLMODE=NONE ;
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LOCATE COMP "reset_n" SITE "E13" ;
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GSR_NET NET "resetSynch_n";
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### LEDs ###
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LOCATE COMP "LED1" SITE "T14" ;# red
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LOCATE COMP "LED2" SITE "R14" ;# green
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LOCATE COMP "LED3" SITE "T15" ;# blue
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################
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#### SODIMM-200
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################
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### PP2 ###
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LOCATE COMP "xOut" SITE "G3" ;
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LOCATE COMP "yOut" SITE "E1" ;
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LOCATE COMP "ampOut" SITE "F3" ;
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#LOCATE COMP "" SITE "D1" ;
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#LOCATE COMP "" SITE "F4" ;
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#LOCATE COMP "" SITE "C1" ;
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LOCATE COMP "morseIn" SITE "D7" ;
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#LOCATE COMP "" SITE "B6" ;
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LOCATE COMP "morseEnvelope" SITE "C7" ;
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#LOCATE COMP "" SITE "A6" ; # PP2 11
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#LOCATE COMP "" SITE "D8" ; # PP2 13
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#LOCATE COMP "" SITE "B7" ; # PP2 15
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#LOCATE COMP "" SITE "C8" ; # PP2 17
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#LOCATE COMP "" SITE "A7" ; # PP2 19
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#LOCATE COMP "" SITE "E9" ; # PP2 21
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LOCATE COMP "RxD_synch" SITE "A8" ; # PP2 23
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LOCATE COMP "morseOut" SITE "D9" ; # PP2 25
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### PP1 ###
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#LOCATE COMP "" SITE "A9" ;
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#LOCATE COMP "" SITE "D10" ;
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#LOCATE COMP "" SITE "A10" ;
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#LOCATE COMP "" SITE "C10" ;
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#LOCATE COMP "" SITE "B10" ;
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#LOCATE COMP "" SITE "C12" ;
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#LOCATE COMP "" SITE "B12" ;
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#LOCATE COMP "" SITE "D13" ;
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#LOCATE COMP "" SITE "A13" ;
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#LOCATE COMP "" SITE "M5" ; # PP1 11
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#LOCATE COMP "" SITE "L5" ; # PP1 13
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#LOCATE COMP "" SITE "K5" ; # PP1 15
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#LOCATE COMP "" SITE "H5" ; # PP1 17
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#LOCATE COMP "" SITE "E8" ; # PP1 19
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#LOCATE COMP "" SITE "E5" ; # PP1 21
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LOCATE COMP "selSinCos_n" SITE "E6" ; # PP1 23
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#LOCATE COMP "" SITE "E7" ; # PP1 25
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### USB (FTDI2232HL located on the daughterboard) ###
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LOCATE COMP "TxD" SITE "A14" ;
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IOBUF PORT "TxD" SLEWRATE=FAST ;
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LOCATE COMP "RxD" SITE "B14" ;
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IOBUF PORT "RxD" PULLMODE=UP ;
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#LOCATE COMP "USB_DB_RTS" SITE "B13" ;
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#IOBUF PORT "USB_DB_RTS" SLEWRATE=FAST ;
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#LOCATE COMP "USB_DB_CTS" SITE "C13" ;
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#IOBUF PORT "USB_DB_CTS" PULLMODE=UP ;
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################
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#### Extras
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################
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### SD Flash (External SD card) ###
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#LOCATE COMP "SD_DETECT" SITE "G12" ;
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#IOBUF PORT "SD_DETECT" PULLMODE=UP ;
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#LOCATE COMP "SD_CMD" SITE "C15" ;
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#IOBUF PORT "SD_CMD" SLEWRATE=FAST ;
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#LOCATE COMP "SD_CLK" SITE "B15" ;
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#IOBUF PORT "SD_CLK" SLEWRATE=FAST ;
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#LOCATE COMP "SD_DTA[0]" SITE "B16" ;
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##IOBUF PORT "SD_DTA[0]" SLEWRATE=FAST ;
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#LOCATE COMP "SD_DTA[1]" SITE "C16" ;
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##IOBUF PORT "SD_DTA[1]" SLEWRATE=FAST ;
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#LOCATE COMP "SD_DTA[2]" SITE "F12" ;
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##IOBUF PORT "SD_DTA[2]" SLEWRATE=FAST ;
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#LOCATE COMP "SD_DTA[3]" SITE "C14" ;
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##IOBUF PORT "SD_DTA[3]" SLEWRATE=FAST ;
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### DRAM ###
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#LOCATE COMP "DRAM_ADDR[0]" SITE "J15" ;
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#IOBUF PORT "DRAM_ADDR[0]" SLEWRATE=FAST ;
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#LOCATE COMP "DRAM_ADDR[1]" SITE "L16" ;
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#IOBUF PORT "DRAM_ADDR[1]" SLEWRATE=FAST ;
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#LOCATE COMP "DRAM_ADDR[2]" SITE "L15" ;
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#IOBUF PORT "DRAM_ADDR[2]" SLEWRATE=FAST ;
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#LOCATE COMP "DRAM_ADDR[3]" SITE "K15" ;
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#IOBUF PORT "DRAM_ADDR[3]" SLEWRATE=FAST ;
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#LOCATE COMP "DRAM_ADDR[4]" SITE "G15" ;
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#IOBUF PORT "DRAM_ADDR[4]" SLEWRATE=FAST ;
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#LOCATE COMP "DRAM_ADDR[5]" SITE "F15" ;
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#IOBUF PORT "DRAM_ADDR[5]" SLEWRATE=FAST ;
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#LOCATE COMP "DRAM_ADDR[6]" SITE "F16" ;
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#IOBUF PORT "DRAM_ADDR[6]" SLEWRATE=FAST ;
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#LOCATE COMP "DRAM_ADDR[7]" SITE "E16" ;
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#IOBUF PORT "DRAM_ADDR[7]" SLEWRATE=FAST ;
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#LOCATE COMP "DRAM_ADDR[8]" SITE "E15" ;
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#IOBUF PORT "DRAM_ADDR[8]" SLEWRATE=FAST ;
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#LOCATE COMP "DRAM_ADDR[9]" SITE "G13" ;
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#IOBUF PORT "DRAM_ADDR[9]" SLEWRATE=FAST ;
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#LOCATE COMP "DRAM_ADDR[10]" SITE "M16" ;
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#IOBUF PORT "DRAM_ADDR[10]" SLEWRATE=FAST ;
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#LOCATE COMP "DRAM_ADDR[11]" SITE "F13" ;
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#IOBUF PORT "DRAM_ADDR[11]" SLEWRATE=FAST ;
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#LOCATE COMP "DRAM_ADDR[12]" SITE "D16" ;
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#IOBUF PORT "DRAM_ADDR[12]" SLEWRATE=FAST ;
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#LOCATE COMP "DRAM_BA[0]" SITE "L14" ;
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#IOBUF PORT "DRAM_BA[0]" SLEWRATE=FAST ;
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#LOCATE COMP "DRAM_BA[1]" SITE "L13" ;
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#IOBUF PORT "DRAM_BA[1]" SLEWRATE=FAST ;
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#LOCATE COMP "DRAM_CLK" SITE "G14" ;
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#IOBUF PORT "DRAM_CLK" SLEWRATE=FAST ;
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#LOCATE COMP "DRAM_CKE" SITE "G16" ;
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#IOBUF PORT "DRAM_CKE" SLEWRATE=FAST ;
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#LOCATE COMP "DRAM_nRAS" SITE "M14" ;
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#IOBUF PORT "DRAM_nRAS" SLEWRATE=FAST ;
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#LOCATE COMP "DRAM_nCAS" SITE "K13" ;
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#IOBUF PORT "DRAM_nCAS" SLEWRATE=FAST ;
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#LOCATE COMP "DRAM_nWE" SITE "N16" ;
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#IOBUF PORT "DRAM_nWE" SLEWRATE=FAST ;
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#LOCATE COMP "DRAM_nCS" SITE "M15" ;
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#LOCATE COMP "DRAM_DQ[0]" SITE "P14" ;
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#LOCATE COMP "DRAM_DQ[1]" SITE "R15" ;
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#LOCATE COMP "DRAM_DQ[2]" SITE "N14" ;
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#LOCATE COMP "DRAM_DQ[3]" SITE "R16" ;
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#LOCATE COMP "DRAM_DQ[4]" SITE "J14" ;
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#LOCATE COMP "DRAM_DQ[5]" SITE "P15" ;
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#LOCATE COMP "DRAM_DQ[6]" SITE "K14" ;
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#LOCATE COMP "DRAM_DQ[7]" SITE "P16" ;
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#LOCATE COMP "DRAM_DQ[8]" SITE "D14" ;
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#LOCATE COMP "DRAM_DQ[9]" SITE "H14" ;
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#LOCATE COMP "DRAM_DQ[10]" SITE "H12" ;
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#LOCATE COMP "DRAM_DQ[11]" SITE "H13" ;
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#LOCATE COMP "DRAM_DQ[12]" SITE "E14" ;
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#LOCATE COMP "DRAM_DQ[13]" SITE "H15" ;
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#LOCATE COMP "DRAM_DQ[14]" SITE "J13" ;
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#LOCATE COMP "DRAM_DQ[15]" SITE "J16" ;
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#LOCATE COMP "DRAM_DQM[0]" SITE "M13" ;
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#IOBUF PORT "DRAM_DQM[0]" SLEWRATE=FAST ;
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#LOCATE COMP "DRAM_DQM[1]" SITE "F14" ;
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#IOBUF PORT "DRAM_DQM[1]" SLEWRATE=FAST ;
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### USB (chip located on the motherboard) ###
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#LOCATE COMP "USB_MB_TX" SITE "M11" ;
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#IOBUF PORT "USB_MB_TX" SLEWRATE=FAST ;
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#LOCATE COMP "USB_MB_RX" SITE "N12" ;
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#IOBUF PORT "USB_MB_RX" PULLMODE=UP ;
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#LOCATE COMP "USB_MB_RTS" SITE "N11" ;
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#IOBUF PORT "USB_MB_RTS" SLEWRATE=FAST ;
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#LOCATE COMP "USB_MB_CTS" SITE "M12" ;
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#IOBUF PORT "USB_MB_CTS" PULLMODE=UP ;
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|
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### PMOD1 ###
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#LOCATE COMP "dbg_leds[16]" SITE "P1" ;
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#LOCATE COMP "dbg_leds[17]" SITE "N4" ;
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#LOCATE COMP "dbg_leds[18]" SITE "P2" ;
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#LOCATE COMP "dbg_leds[19]" SITE "P5" ;
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#LOCATE COMP "dbg_leds[20]" SITE "R1" ;
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#LOCATE COMP "dbg_leds[21]" SITE "N5" ;
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#LOCATE COMP "dbg_leds[22]" SITE "R2" ;
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#LOCATE COMP "dbg_leds[23]" SITE "N6" ;
|
||||
|
||||
|
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### PMOD2 ###
|
||||
#LOCATE COMP "dbg_leds[24]" SITE "R3" ;
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#LOCATE COMP "dbg_leds[25]" SITE "P11" ;
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||||
#LOCATE COMP "dbg_leds[26]" SITE "P12" ;
|
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#LOCATE COMP "dbg_leds[27]" SITE "T3" ;
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#LOCATE COMP "dbg_leds[28]" SITE "R4" ;
|
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#LOCATE COMP "dbg_leds[29]" SITE "R12" ;
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#LOCATE COMP "dbg_leds[30]" SITE "T13" ;
|
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#LOCATE COMP "dbg_leds[31]" SITE "R5" ;
|
||||
|
||||
|
||||
### PMOD3 ###
|
||||
#LOCATE COMP "dbg_leds[8]" SITE "B2" ;
|
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#LOCATE COMP "dbg_leds[9]" SITE "B3" ;
|
||||
#LOCATE COMP "dbg_leds[10]" SITE "A4" ;
|
||||
#LOCATE COMP "dbg_leds[11]" SITE "D4" ;
|
||||
#LOCATE COMP "dbg_leds[12]" SITE "A2" ;
|
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#LOCATE COMP "dbg_leds[13]" SITE "B4" ;
|
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#LOCATE COMP "dbg_leds[14]" SITE "C3" ;
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#LOCATE COMP "dbg_leds[15]" SITE "C4" ;
|
||||
|
||||
|
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### PMOD4 ###
|
||||
#LOCATE COMP "dbg_leds[0]" SITE "J4" ;
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#LOCATE COMP "dbg_leds[1]" SITE "J5" ;
|
||||
#LOCATE COMP "dbg_leds[2]" SITE "H4" ;
|
||||
#LOCATE COMP "dbg_leds[3]" SITE "E4" ;
|
||||
#LOCATE COMP "dbg_leds[4]" SITE "J3" ;
|
||||
#LOCATE COMP "dbg_leds[5]" SITE "H3" ;
|
||||
#LOCATE COMP "dbg_leds[6]" SITE "E3" ;
|
||||
#LOCATE COMP "dbg_leds[7]" SITE "D3" ;
|
||||
|
||||
|
||||
### Ethernet ###
|
||||
#LOCATE COMP "ETH_CLK_EN" SITE "B1" ;
|
||||
#LOCATE COMP "ETH_nRESET" SITE "C2" ;
|
||||
|
||||
#LOCATE COMP "ETH_nLED_Y" SITE "F1" ;
|
||||
#LOCATE COMP "ETH_nLED_G" SITE "G2" ;
|
||||
|
||||
#LOCATE COMP "ETH_MDC" SITE "J1" ;
|
||||
#LOCATE COMP "ETH_MDIO" SITE "H2" ;
|
||||
#IOBUF PORT "ETH_MDIO" OPENDRAIN=ON SLEWRATE=FAST ;
|
||||
#LOCATE COMP "ETH_MDINT" SITE "G1" ;
|
||||
#IOBUF PORT "ETH_MDINT" SLEWRATE=FAST ;
|
||||
|
||||
#LOCATE COMP "ETH_REF_CLK" SITE "P3" ;
|
||||
|
||||
#LOCATE COMP "ETH_TX_CLK" SITE "M4" ;
|
||||
#IOBUF PORT "ETH_TX_CLK" SLEWRATE=FAST ;
|
||||
#LOCATE COMP "ETH_TX_CTL" SITE "N3" ;
|
||||
#IOBUF PORT "ETH_TX_CTL" SLEWRATE=FAST ;
|
||||
#LOCATE COMP "ETH_TXD[0]" SITE "M3" ;
|
||||
#IOBUF PORT "ETH_TXD[0]" SLEWRATE=FAST ;
|
||||
#LOCATE COMP "ETH_TXD[1]" SITE "L4" ;
|
||||
#IOBUF PORT "ETH_TXD[1]" SLEWRATE=FAST ;
|
||||
#LOCATE COMP "ETH_TXD[2]" SITE "K4" ;
|
||||
#IOBUF PORT "ETH_TXD[2]" SLEWRATE=FAST ;
|
||||
#LOCATE COMP "ETH_TXD[3]" SITE "K3" ;
|
||||
#IOBUF PORT "ETH_TXD[3]" SLEWRATE=FAST ;
|
||||
|
||||
#LOCATE COMP "ETH_RX_CLK" SITE "K1" ;
|
||||
#LOCATE COMP "ETH_RX_CTL" SITE "K2" ;
|
||||
#LOCATE COMP "ETH_RXD[0]" SITE "L1" ;
|
||||
#LOCATE COMP "ETH_RXD[1]" SITE "L2" ;
|
||||
#LOCATE COMP "ETH_RXD[2]" SITE "M1" ;
|
||||
#LOCATE COMP "ETH_RXD[3]" SITE "M2" ;
|
||||
|
||||
|
||||
### Extras ###
|
||||
#LOCATE COMP "EXT[1]" SITE "P13" ;
|
||||
#LOCATE COMP "EXT[2]" SITE "R13" ;
|
||||
#LOCATE COMP "EXT[3]" SITE "A3" ;
|
||||
#LOCATE COMP "EXT[4]" SITE "A5" ;
|
||||
#LOCATE COMP "EXT[5]" SITE "B5" ;
|
||||
#LOCATE COMP "EXT[6]" SITE "C5" ;
|
||||
#LOCATE COMP "EXT[7]" SITE "C6" ;
|
||||
#LOCATE COMP "EXT[8]" SITE "D5" ;
|
||||
#LOCATE COMP "EXT[9]" SITE "D6" ;
|
||||
#LOCATE COMP "EXT[10]" SITE "A11" ;
|
||||
#LOCATE COMP "EXT[11]" SITE "A12" ;
|
||||
#LOCATE COMP "EXT[12]" SITE "B8" ;
|
||||
#LOCATE COMP "EXT[13]" SITE "B9" ;
|
||||
#LOCATE COMP "EXT[14]" SITE "B11" ;
|
||||
#LOCATE COMP "EXT[15]" SITE "C9" ;
|
||||
#LOCATE COMP "EXT[16]" SITE "C11" ;
|
||||
#LOCATE COMP "EXT[17]" SITE "D11" ;
|
||||
#LOCATE COMP "EXT[18]" SITE "D12" ;
|
||||
#LOCATE COMP "EXT[19]" SITE "E10" ;
|
||||
#LOCATE COMP "EXT[20]" SITE "E11" ;
|
||||
#LOCATE COMP "EXT[21]" SITE "E12" ;
|
||||
#LOCATE COMP "EXT[22]" SITE "L3" ;
|
||||
#LOCATE COMP "EXT[23]" SITE "M6" ;
|
||||
#LOCATE COMP "EXT[24]" SITE "N1" ;
|
||||
#LOCATE COMP "EXT[25]" SITE "P4" ;
|
||||
#LOCATE COMP "EXT[26]" SITE "P6" ;
|
||||
#LOCATE COMP "EXT[27]" SITE "T2" ;
|
||||
#LOCATE COMP "EXT[28]" SITE "T4" ;
|
||||
#LOCATE COMP "EXT[29]" SITE "E2" ;
|
||||
#LOCATE COMP "EXT[30]" SITE "F2" ;
|
||||
#LOCATE COMP "EXT[31]" SITE "F5" ;
|
||||
#LOCATE COMP "EXT[32]" SITE "G4" ;
|
||||
#LOCATE COMP "EXT[33]" SITE "G5" ;
|
||||
#LOCATE COMP "EXT[34]" SITE "J2" ;
|
||||
57
06-07-08-09-SystemOnChip/Board/concat/systemOnChip.ucf
Normal file
57
06-07-08-09-SystemOnChip/Board/concat/systemOnChip.ucf
Normal file
@ -0,0 +1,57 @@
|
||||
#-------------------------------------------------------------------------------
|
||||
# Clock and reset
|
||||
#
|
||||
NET "reset_n" LOC = "D3" | PULLUP;
|
||||
NET "clock" LOC = "A10";
|
||||
|
||||
#-------------------------------------------------------------------------------
|
||||
# Buttons & LEDs
|
||||
#
|
||||
NET "selSinCos_n" LOC = "A15" | PULLUP;
|
||||
#NET "button2_n" LOC = "D3" | PULLUP;
|
||||
NET "LED1" LOC = "B16";
|
||||
NET "LED2" LOC = "A16";
|
||||
|
||||
#-------------------------------------------------------------------------------
|
||||
# Sigma-delta outputs
|
||||
#
|
||||
#NET "xOut" LOC = "G4" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW ;
|
||||
#NET "yOut" LOC = "G5" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW ;
|
||||
NET "xOut" LOC = "G4" ;
|
||||
NET "yOut" LOC = "G5" ;
|
||||
|
||||
#-------------------------------------------------------------------------------
|
||||
# Serial ports, Rx, Tx defined with FPGA as master
|
||||
#
|
||||
NET "rxd0" LOC = "V2" ; # female DB9 on J9
|
||||
NET "txd0" LOC = "T1" ;
|
||||
#NET "rxd1" LOC = "U1" ; # male DB9 on J10
|
||||
#NET "txd1" LOC = "P1" ;
|
||||
|
||||
#-------------------------------------------------------------------------------
|
||||
# Debug
|
||||
#
|
||||
NET "spare<1>" LOC = "F8" ;
|
||||
NET "spare<2>" LOC = "F7" ;
|
||||
NET "spare<3>" LOC = "F9" ;
|
||||
NET "spare<4>" LOC = "G9" ;
|
||||
NET "spare<5>" LOC = "E8" ;
|
||||
NET "spare<6>" LOC = "E7" ;
|
||||
NET "spare<7>" LOC = "B14";
|
||||
NET "spare<8>" LOC = "B13";
|
||||
NET "spare<9>" LOC = "B11";
|
||||
NET "spare<10>" LOC = "A8" ;
|
||||
NET "spare<11>" LOC = "C7" ;
|
||||
NET "spare<12>" LOC = "A14";
|
||||
NET "spare<13>" LOC = "A11";
|
||||
NET "spare<14>" LOC = "A13";
|
||||
NET "spare<15>" LOC = "D7" ;
|
||||
NET "spare<16>" LOC = "E9" ;
|
||||
NET "spare<17>" LOC = "F11";
|
||||
|
||||
|
||||
#-------------------------------------------------------------------------------
|
||||
# Globals
|
||||
#
|
||||
#NET "*" IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW;
|
||||
NET "*" IOSTANDARD = LVCMOS33;
|
||||
6031
06-07-08-09-SystemOnChip/Board/concat/systemOnChip.vhd
Normal file
6031
06-07-08-09-SystemOnChip/Board/concat/systemOnChip.vhd
Normal file
File diff suppressed because it is too large
Load Diff
50
06-07-08-09-SystemOnChip/Board/diamond/programmer.xcf
Normal file
50
06-07-08-09-SystemOnChip/Board/diamond/programmer.xcf
Normal file
@ -0,0 +1,50 @@
|
||||
<?xml version='1.0' encoding='utf-8' ?>
|
||||
<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
|
||||
<ispXCF version="3.12">
|
||||
<Comment></Comment>
|
||||
<Chain>
|
||||
<Comm>JTAG</Comm>
|
||||
<Device>
|
||||
<SelectedProg value="TRUE"/>
|
||||
<Pos>1</Pos>
|
||||
<Vendor>Renesas</Vendor>
|
||||
<Family>ECP5U</Family>
|
||||
<Name>LFE5U-25F</Name>
|
||||
<Package>All</Package>
|
||||
<PON>LFE5U-25F</PON>
|
||||
<Bypass>
|
||||
<InstrLen>8</InstrLen>
|
||||
<InstrVal>11111111</InstrVal>
|
||||
<BScanLen>1</BScanLen>
|
||||
<BScanVal>0</BScanVal>
|
||||
</Bypass>
|
||||
<File></File>
|
||||
<FileTime>04/11/23 16:14:28</FileTime>
|
||||
<JedecChecksum>0xA4B0</JedecChecksum>
|
||||
<Operation>Fast Program</Operation>
|
||||
<Option>
|
||||
<SVFVendor>JTAG STANDARD</SVFVendor>
|
||||
<IOState>HighZ</IOState>
|
||||
<PreloadLength>409</PreloadLength>
|
||||
<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
|
||||
<SVFProcessor>SVF Processor</SVFProcessor>
|
||||
<Usercode>0x00000000</Usercode>
|
||||
<AccessMode>JTAG</AccessMode>
|
||||
</Option>
|
||||
</Device>
|
||||
</Chain>
|
||||
<ProjectOptions>
|
||||
<Program>SEQUENTIAL</Program>
|
||||
<Process>ENTIRED CHAIN</Process>
|
||||
<OperationOverride>No Override</OperationOverride>
|
||||
<StartTAP>TLR</StartTAP>
|
||||
<EndTAP>TLR</EndTAP>
|
||||
<VerifyUsercode value="FALSE"/>
|
||||
<TCKDelay>4</TCKDelay>
|
||||
</ProjectOptions>
|
||||
<CableOptions>
|
||||
<CableName>USB2</CableName>
|
||||
<PortAdd>FTUSB-0</PortAdd>
|
||||
<USBID>LFE5U-25F A Location 0000 Serial 018VFVT3A</USBID>
|
||||
</CableOptions>
|
||||
</ispXCF>
|
||||
638
06-07-08-09-SystemOnChip/Board/diamond/reveal_analyze.rva
Normal file
638
06-07-08-09-SystemOnChip/Board/diamond/reveal_analyze.rva
Normal file
@ -0,0 +1,638 @@
|
||||
<!DOCTYPE ispTLA>
|
||||
<ispTLA>
|
||||
<CreationDate>lun. 6. mars 14:29:10 2023</CreationDate>
|
||||
<XCFFileName/>
|
||||
<CableSetting>
|
||||
<IsTRSTConnected val="false"/>
|
||||
<TRSTSetting val="0"/>
|
||||
<IsBSCANConnected val="false"/>
|
||||
<BSCANSetting val="0"/>
|
||||
<CableType val="USB2"/>
|
||||
<PortAddress val="0"/>
|
||||
<PortSetting val="0"/>
|
||||
<TCKDelay val="1"/>
|
||||
</CableSetting>
|
||||
<DeviceCount>1</DeviceCount>
|
||||
<Device>
|
||||
<DeviceIndex>0</DeviceIndex>
|
||||
<DeviceName>1. LFE5U-25F</DeviceName>
|
||||
<DeviceID>0x41111043</DeviceID>
|
||||
<HasIspTRACY>true</HasIspTRACY>
|
||||
<HasJTAG2WB>false</HasJTAG2WB>
|
||||
<SERDES/>
|
||||
<IRBypassLen>8</IRBypassLen>
|
||||
<RVLFileName>reveal_config.rvl</RVLFileName>
|
||||
<RVSFileName>reveal_config.rvs</RVSFileName>
|
||||
<LACoreCount>1</LACoreCount>
|
||||
<WinUI CoreIndex="0">
|
||||
<TraceSigTreeData>
|
||||
<TraceSignal IsHidden="false" Name="en" NodeType="0" PortIndex="508"/>
|
||||
<TraceSignal IsHidden="false" Name="clk_red" NodeType="0" PortIndex="0"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pcwrite" NodeType="0" PortIndex="1"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pc" NodeType="1" PortIndex="2">
|
||||
<BusRadix Radix="3"/>
|
||||
<IsExpanded Expand="false"/>
|
||||
</TraceSignal>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pc:0" NodeType="2" PortIndex="2"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pc:1" NodeType="2" PortIndex="3"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pc:2" NodeType="2" PortIndex="4"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pc:3" NodeType="2" PortIndex="5"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pc:4" NodeType="2" PortIndex="6"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pc:5" NodeType="2" PortIndex="7"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pc:6" NodeType="2" PortIndex="8"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pc:7" NodeType="2" PortIndex="9"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pc:8" NodeType="2" PortIndex="10"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pc:9" NodeType="2" PortIndex="11"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pc:10" NodeType="2" PortIndex="12"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pc:11" NodeType="2" PortIndex="13"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pc:12" NodeType="2" PortIndex="14"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pc:13" NodeType="2" PortIndex="15"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pc:14" NodeType="2" PortIndex="16"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pc:15" NodeType="2" PortIndex="17"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pc:16" NodeType="2" PortIndex="18"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pc:17" NodeType="2" PortIndex="19"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pc:18" NodeType="2" PortIndex="20"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pc:19" NodeType="2" PortIndex="21"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pc:20" NodeType="2" PortIndex="22"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pc:21" NodeType="2" PortIndex="23"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pc:22" NodeType="2" PortIndex="24"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pc:23" NodeType="2" PortIndex="25"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pc:24" NodeType="2" PortIndex="26"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pc:25" NodeType="2" PortIndex="27"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pc:26" NodeType="2" PortIndex="28"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pc:27" NodeType="2" PortIndex="29"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pc:28" NodeType="2" PortIndex="30"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pc:29" NodeType="2" PortIndex="31"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pc:30" NodeType="2" PortIndex="32"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pc:31" NodeType="2" PortIndex="33"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/oldpc" NodeType="1" PortIndex="34">
|
||||
<BusRadix Radix="3"/>
|
||||
<IsExpanded Expand="false"/>
|
||||
</TraceSignal>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/oldpc:0" NodeType="2" PortIndex="34"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/oldpc:1" NodeType="2" PortIndex="35"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/oldpc:2" NodeType="2" PortIndex="36"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/oldpc:3" NodeType="2" PortIndex="37"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/oldpc:4" NodeType="2" PortIndex="38"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/oldpc:5" NodeType="2" PortIndex="39"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/oldpc:6" NodeType="2" PortIndex="40"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/oldpc:7" NodeType="2" PortIndex="41"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/oldpc:8" NodeType="2" PortIndex="42"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/oldpc:9" NodeType="2" PortIndex="43"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/oldpc:10" NodeType="2" PortIndex="44"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/oldpc:11" NodeType="2" PortIndex="45"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/oldpc:12" NodeType="2" PortIndex="46"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/oldpc:13" NodeType="2" PortIndex="47"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/oldpc:14" NodeType="2" PortIndex="48"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/oldpc:15" NodeType="2" PortIndex="49"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/oldpc:16" NodeType="2" PortIndex="50"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/oldpc:17" NodeType="2" PortIndex="51"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/oldpc:18" NodeType="2" PortIndex="52"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/oldpc:19" NodeType="2" PortIndex="53"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/oldpc:20" NodeType="2" PortIndex="54"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/oldpc:21" NodeType="2" PortIndex="55"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/oldpc:22" NodeType="2" PortIndex="56"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/oldpc:23" NodeType="2" PortIndex="57"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/oldpc:24" NodeType="2" PortIndex="58"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/oldpc:25" NodeType="2" PortIndex="59"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/oldpc:26" NodeType="2" PortIndex="60"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/oldpc:27" NodeType="2" PortIndex="61"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/oldpc:28" NodeType="2" PortIndex="62"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/oldpc:29" NodeType="2" PortIndex="63"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/oldpc:30" NodeType="2" PortIndex="64"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/oldpc:31" NodeType="2" PortIndex="65"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pcnext" NodeType="1" PortIndex="66">
|
||||
<BusRadix Radix="3"/>
|
||||
<IsExpanded Expand="false"/>
|
||||
</TraceSignal>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pcnext:0" NodeType="2" PortIndex="66"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pcnext:1" NodeType="2" PortIndex="67"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pcnext:2" NodeType="2" PortIndex="68"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pcnext:3" NodeType="2" PortIndex="69"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pcnext:4" NodeType="2" PortIndex="70"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pcnext:5" NodeType="2" PortIndex="71"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pcnext:6" NodeType="2" PortIndex="72"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pcnext:7" NodeType="2" PortIndex="73"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pcnext:8" NodeType="2" PortIndex="74"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pcnext:9" NodeType="2" PortIndex="75"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pcnext:10" NodeType="2" PortIndex="76"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pcnext:11" NodeType="2" PortIndex="77"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pcnext:12" NodeType="2" PortIndex="78"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pcnext:13" NodeType="2" PortIndex="79"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pcnext:14" NodeType="2" PortIndex="80"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pcnext:15" NodeType="2" PortIndex="81"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pcnext:16" NodeType="2" PortIndex="82"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pcnext:17" NodeType="2" PortIndex="83"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pcnext:18" NodeType="2" PortIndex="84"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pcnext:19" NodeType="2" PortIndex="85"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pcnext:20" NodeType="2" PortIndex="86"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pcnext:21" NodeType="2" PortIndex="87"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pcnext:22" NodeType="2" PortIndex="88"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pcnext:23" NodeType="2" PortIndex="89"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pcnext:24" NodeType="2" PortIndex="90"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pcnext:25" NodeType="2" PortIndex="91"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pcnext:26" NodeType="2" PortIndex="92"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pcnext:27" NodeType="2" PortIndex="93"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pcnext:28" NodeType="2" PortIndex="94"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pcnext:29" NodeType="2" PortIndex="95"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pcnext:30" NodeType="2" PortIndex="96"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/pcnext:31" NodeType="2" PortIndex="97"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/adrsrc" NodeType="0" PortIndex="98"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/adr" NodeType="1" PortIndex="99">
|
||||
<BusRadix Radix="3"/>
|
||||
<IsExpanded Expand="false"/>
|
||||
</TraceSignal>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/adr:0" NodeType="2" PortIndex="99"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/adr:1" NodeType="2" PortIndex="100"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/adr:2" NodeType="2" PortIndex="101"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/adr:3" NodeType="2" PortIndex="102"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/adr:4" NodeType="2" PortIndex="103"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/adr:5" NodeType="2" PortIndex="104"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/adr:6" NodeType="2" PortIndex="105"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/adr:7" NodeType="2" PortIndex="106"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/adr:8" NodeType="2" PortIndex="107"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/adr:9" NodeType="2" PortIndex="108"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/adr:10" NodeType="2" PortIndex="109"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/adr:11" NodeType="2" PortIndex="110"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/adr:12" NodeType="2" PortIndex="111"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/adr:13" NodeType="2" PortIndex="112"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/adr:14" NodeType="2" PortIndex="113"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/adr:15" NodeType="2" PortIndex="114"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/adr:16" NodeType="2" PortIndex="115"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/adr:17" NodeType="2" PortIndex="116"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/adr:18" NodeType="2" PortIndex="117"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/adr:19" NodeType="2" PortIndex="118"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/adr:20" NodeType="2" PortIndex="119"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/adr:21" NodeType="2" PortIndex="120"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/adr:22" NodeType="2" PortIndex="121"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/adr:23" NodeType="2" PortIndex="122"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/adr:24" NodeType="2" PortIndex="123"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/adr:25" NodeType="2" PortIndex="124"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/adr:26" NodeType="2" PortIndex="125"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/adr:27" NodeType="2" PortIndex="126"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/adr:28" NodeType="2" PortIndex="127"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/adr:29" NodeType="2" PortIndex="128"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/adr:30" NodeType="2" PortIndex="129"/>
|
||||
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|
||||
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|
||||
<BusRadix Radix="3"/>
|
||||
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|
||||
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|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/writedata:0" NodeType="2" PortIndex="131"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/writedata:1" NodeType="2" PortIndex="132"/>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/writedata:10" NodeType="2" PortIndex="141"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/writedata:11" NodeType="2" PortIndex="142"/>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/writedata:24" NodeType="2" PortIndex="155"/>
|
||||
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|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/writedata:26" NodeType="2" PortIndex="157"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/writedata:27" NodeType="2" PortIndex="158"/>
|
||||
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|
||||
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|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/writedata:30" NodeType="2" PortIndex="161"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/writedata:31" NodeType="2" PortIndex="162"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/memwrite" NodeType="0" PortIndex="163"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/data" NodeType="1" PortIndex="164">
|
||||
<BusRadix Radix="3"/>
|
||||
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|
||||
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|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/data:0" NodeType="2" PortIndex="164"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/data:1" NodeType="2" PortIndex="165"/>
|
||||
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|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/data:3" NodeType="2" PortIndex="167"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/data:4" NodeType="2" PortIndex="168"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/data:5" NodeType="2" PortIndex="169"/>
|
||||
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|
||||
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|
||||
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|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/data:9" NodeType="2" PortIndex="173"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/data:10" NodeType="2" PortIndex="174"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/data:11" NodeType="2" PortIndex="175"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/data:12" NodeType="2" PortIndex="176"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/data:13" NodeType="2" PortIndex="177"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/data:14" NodeType="2" PortIndex="178"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/data:15" NodeType="2" PortIndex="179"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/data:16" NodeType="2" PortIndex="180"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/data:17" NodeType="2" PortIndex="181"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/data:18" NodeType="2" PortIndex="182"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/data:19" NodeType="2" PortIndex="183"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/data:20" NodeType="2" PortIndex="184"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/data:21" NodeType="2" PortIndex="185"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/data:22" NodeType="2" PortIndex="186"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/data:23" NodeType="2" PortIndex="187"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/data:24" NodeType="2" PortIndex="188"/>
|
||||
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|
||||
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|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/data:27" NodeType="2" PortIndex="191"/>
|
||||
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|
||||
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|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/data:30" NodeType="2" PortIndex="194"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/data:31" NodeType="2" PortIndex="195"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/irwrite" NodeType="0" PortIndex="196"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/instruction" NodeType="1" PortIndex="197">
|
||||
<BusRadix Radix="3"/>
|
||||
<IsExpanded Expand="false"/>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<BusRadix Radix="3"/>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<BusRadix Radix="3"/>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/regwrite" NodeType="0" PortIndex="301"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/alusrca" NodeType="1" PortIndex="302">
|
||||
<BusRadix Radix="0"/>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/rd1" NodeType="1" PortIndex="304">
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/aluout:14" NodeType="2" PortIndex="486"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/aluout:15" NodeType="2" PortIndex="487"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/aluout:16" NodeType="2" PortIndex="488"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/aluout:17" NodeType="2" PortIndex="489"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/aluout:18" NodeType="2" PortIndex="490"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/aluout:19" NodeType="2" PortIndex="491"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/aluout:20" NodeType="2" PortIndex="492"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/aluout:21" NodeType="2" PortIndex="493"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/aluout:22" NodeType="2" PortIndex="494"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/aluout:23" NodeType="2" PortIndex="495"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/aluout:24" NodeType="2" PortIndex="496"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/aluout:25" NodeType="2" PortIndex="497"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/aluout:26" NodeType="2" PortIndex="498"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/aluout:27" NodeType="2" PortIndex="499"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/aluout:28" NodeType="2" PortIndex="500"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/aluout:29" NodeType="2" PortIndex="501"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/aluout:30" NodeType="2" PortIndex="502"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/aluout:31" NodeType="2" PortIndex="503"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/resultsrc" NodeType="1" PortIndex="504">
|
||||
<BusRadix Radix="0"/>
|
||||
<IsExpanded Expand="false"/>
|
||||
</TraceSignal>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/resultsrc:0" NodeType="2" PortIndex="504"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/resultsrc:1" NodeType="2" PortIndex="505"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/u_controlunit/branch" NodeType="0" PortIndex="506"/>
|
||||
<TraceSignal IsHidden="false" Name="u_heirv32/u_controlunit/pcupdate" NodeType="0" PortIndex="507"/>
|
||||
</TraceSigTreeData>
|
||||
<TriggerUI UserSelect="0" PreSelectType="0" PreSelect="1" UserSelectPos="0"/>
|
||||
<CoreRun Run="true"/>
|
||||
<CoreWndUIData>
|
||||
<ClockFrequency Unit="ns" Frequency="-1.0"/>
|
||||
</CoreWndUIData>
|
||||
</WinUI>
|
||||
</Device>
|
||||
</ispTLA>
|
||||
662
06-07-08-09-SystemOnChip/Board/diamond/reveal_config.rvl
Normal file
662
06-07-08-09-SystemOnChip/Board/diamond/reveal_config.rvl
Normal file
@ -0,0 +1,662 @@
|
||||
<Project ModBy="Inserter" SigType="0" Name="C:/dev/car-heirv/Board/diamond/reveal_config.rvl" Date="2023-03-06">
|
||||
<IP Version="1_6_042617"/>
|
||||
<Design DesignEntry="Schematic/VHDL" Synthesis="synplify" DeviceFamily="ECP5U" DesignName="labsDBTester"/>
|
||||
<Core InsertDataset="0" Insert="1" Reveal_sig="483219822" Name="ebs3_mc_LA0" ID="0">
|
||||
<Setting>
|
||||
<Clock SampleClk="u_pll/clk50m" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
|
||||
<TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="512"/>
|
||||
<Capture Mode="0" MinSamplesPerTrig="8"/>
|
||||
<Event CntEnable="0" MaxEventCnt="8"/>
|
||||
<TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="0" TrigOutNet="reveal_debug_ebs3_mc_LA0_net"/>
|
||||
<DistRAM Disable="0"/>
|
||||
</Setting>
|
||||
<Dataset Name="Base">
|
||||
<Trace>
|
||||
<Sig Type="SIG" Name="clk_red"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pcwrite"/>
|
||||
<Bus Name="u_heirv32/pc">
|
||||
<Sig Type="SIG" Name="u_heirv32/pc:0"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pc:1"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pc:2"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pc:3"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pc:4"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pc:5"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pc:6"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pc:7"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pc:8"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pc:9"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pc:10"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pc:11"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pc:12"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pc:13"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pc:14"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pc:15"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pc:16"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pc:17"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pc:18"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pc:19"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pc:20"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pc:21"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pc:22"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pc:23"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pc:24"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pc:25"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pc:26"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pc:27"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pc:28"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pc:29"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pc:30"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pc:31"/>
|
||||
</Bus>
|
||||
<Bus Name="u_heirv32/oldpc">
|
||||
<Sig Type="SIG" Name="u_heirv32/oldpc:0"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/oldpc:1"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/oldpc:2"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/oldpc:3"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/oldpc:4"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/oldpc:5"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/oldpc:6"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/oldpc:7"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/oldpc:8"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/oldpc:9"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/oldpc:10"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/oldpc:11"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/oldpc:12"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/oldpc:13"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/oldpc:14"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/oldpc:15"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/oldpc:16"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/oldpc:17"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/oldpc:18"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/oldpc:19"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/oldpc:20"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/oldpc:21"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/oldpc:22"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/oldpc:23"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/oldpc:24"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/oldpc:25"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/oldpc:26"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/oldpc:27"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/oldpc:28"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/oldpc:29"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/oldpc:30"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/oldpc:31"/>
|
||||
</Bus>
|
||||
<Bus Name="u_heirv32/pcnext">
|
||||
<Sig Type="SIG" Name="u_heirv32/pcnext:0"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pcnext:1"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pcnext:2"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pcnext:3"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pcnext:4"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pcnext:5"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pcnext:6"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pcnext:7"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pcnext:8"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pcnext:9"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pcnext:10"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pcnext:11"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pcnext:12"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pcnext:13"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pcnext:14"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pcnext:15"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pcnext:16"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pcnext:17"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pcnext:18"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pcnext:19"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pcnext:20"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pcnext:21"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pcnext:22"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pcnext:23"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pcnext:24"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pcnext:25"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pcnext:26"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pcnext:27"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pcnext:28"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pcnext:29"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pcnext:30"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/pcnext:31"/>
|
||||
</Bus>
|
||||
<Sig Type="SIG" Name="u_heirv32/adrsrc"/>
|
||||
<Bus Name="u_heirv32/adr">
|
||||
<Sig Type="SIG" Name="u_heirv32/adr:0"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/adr:1"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/adr:2"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/adr:3"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/adr:4"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/adr:5"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/adr:6"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/adr:7"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/adr:8"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/adr:9"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/adr:10"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/adr:11"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/adr:12"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/adr:13"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/adr:14"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/adr:15"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/adr:16"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/adr:17"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/adr:18"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/adr:19"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/adr:20"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/adr:21"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/adr:22"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/adr:23"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/adr:24"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/adr:25"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/adr:26"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/adr:27"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/adr:28"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/adr:29"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/adr:30"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/adr:31"/>
|
||||
</Bus>
|
||||
<Bus Name="u_heirv32/writedata">
|
||||
<Sig Type="SIG" Name="u_heirv32/writedata:0"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/writedata:1"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/writedata:2"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/writedata:3"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/writedata:4"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/writedata:5"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/writedata:6"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/writedata:7"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/writedata:8"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/writedata:9"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/writedata:10"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/writedata:11"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/writedata:12"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/writedata:13"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/writedata:14"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/writedata:15"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/writedata:16"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/writedata:17"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/writedata:18"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/writedata:19"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/writedata:20"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/writedata:21"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/writedata:22"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/writedata:23"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/writedata:24"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/writedata:25"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/writedata:26"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/writedata:27"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/writedata:28"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/writedata:29"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/writedata:30"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/writedata:31"/>
|
||||
</Bus>
|
||||
<Sig Type="SIG" Name="u_heirv32/memwrite"/>
|
||||
<Bus Name="u_heirv32/data">
|
||||
<Sig Type="SIG" Name="u_heirv32/data:0"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/data:1"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/data:2"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/data:3"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/data:4"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/data:5"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/data:6"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/data:7"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/data:8"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/data:9"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/data:10"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/data:11"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/data:12"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/data:13"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/data:14"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/data:15"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/data:16"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/data:17"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/data:18"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/data:19"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/data:20"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/data:21"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/data:22"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/data:23"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/data:24"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/data:25"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/data:26"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/data:27"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/data:28"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/data:29"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/data:30"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/data:31"/>
|
||||
</Bus>
|
||||
<Sig Type="SIG" Name="u_heirv32/irwrite"/>
|
||||
<Bus Name="u_heirv32/instruction">
|
||||
<Sig Type="SIG" Name="u_heirv32/instruction:0"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/instruction:1"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/instruction:2"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/instruction:3"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/instruction:4"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/instruction:5"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/instruction:6"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/instruction:7"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/instruction:8"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/instruction:9"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/instruction:10"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/instruction:11"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/instruction:12"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/instruction:13"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/instruction:14"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/instruction:15"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/instruction:16"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/instruction:17"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/instruction:18"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/instruction:19"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/instruction:20"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/instruction:21"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/instruction:22"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/instruction:23"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/instruction:24"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/instruction:25"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/instruction:26"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/instruction:27"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/instruction:28"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/instruction:29"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/instruction:30"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/instruction:31"/>
|
||||
</Bus>
|
||||
<Bus Name="u_heirv32/u_extend/input">
|
||||
<Sig Type="SIG" Name="u_heirv32/u_extend/input:7"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_extend/input:8"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_extend/input:9"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_extend/input:10"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_extend/input:11"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_extend/input:12"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_extend/input:13"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_extend/input:14"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_extend/input:15"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_extend/input:16"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_extend/input:17"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_extend/input:18"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_extend/input:19"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_extend/input:20"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_extend/input:21"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_extend/input:22"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_extend/input:23"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_extend/input:24"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_extend/input:25"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_extend/input:26"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_extend/input:27"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_extend/input:28"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_extend/input:29"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_extend/input:30"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_extend/input:31"/>
|
||||
</Bus>
|
||||
<Bus Name="u_heirv32/u_registerfile/addr1">
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/addr1:0"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/addr1:1"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/addr1:2"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/addr1:3"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/addr1:4"/>
|
||||
</Bus>
|
||||
<Bus Name="u_heirv32/u_registerfile/addr2">
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/addr2:0"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/addr2:1"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/addr2:2"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/addr2:3"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/addr2:4"/>
|
||||
</Bus>
|
||||
<Bus Name="u_heirv32/u_registerfile/addr3">
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/addr3:0"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/addr3:1"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/addr3:2"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/addr3:3"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/addr3:4"/>
|
||||
</Bus>
|
||||
<Bus Name="u_heirv32/result">
|
||||
<Sig Type="SIG" Name="u_heirv32/result:0"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/result:1"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/result:2"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/result:3"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/result:4"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/result:5"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/result:6"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/result:7"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/result:8"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/result:9"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/result:10"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/result:11"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/result:12"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/result:13"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/result:14"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/result:15"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/result:16"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/result:17"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/result:18"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/result:19"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/result:20"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/result:21"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/result:22"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/result:23"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/result:24"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/result:25"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/result:26"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/result:27"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/result:28"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/result:29"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/result:30"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/result:31"/>
|
||||
</Bus>
|
||||
<Sig Type="SIG" Name="u_heirv32/regwrite"/>
|
||||
<Bus Name="u_heirv32/alusrca">
|
||||
<Sig Type="SIG" Name="u_heirv32/alusrca:0"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/alusrca:1"/>
|
||||
</Bus>
|
||||
<Bus Name="u_heirv32/rd1">
|
||||
<Sig Type="SIG" Name="u_heirv32/rd1:0"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/rd1:1"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/rd1:2"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/rd1:3"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/rd1:4"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/rd1:5"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/rd1:6"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/rd1:7"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/rd1:8"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/rd1:9"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/rd1:10"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/rd1:11"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/rd1:12"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/rd1:13"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/rd1:14"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/rd1:15"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/rd1:16"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/rd1:17"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/rd1:18"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/rd1:19"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/rd1:20"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/rd1:21"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/rd1:22"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/rd1:23"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/rd1:24"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/rd1:25"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/rd1:26"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/rd1:27"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/rd1:28"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/rd1:29"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/rd1:30"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/rd1:31"/>
|
||||
</Bus>
|
||||
<Bus Name="u_heirv32/srca">
|
||||
<Sig Type="SIG" Name="u_heirv32/srca:0"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srca:1"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srca:2"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srca:3"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srca:4"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srca:5"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srca:6"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srca:7"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srca:8"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srca:9"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srca:10"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srca:11"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srca:12"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srca:13"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srca:14"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srca:15"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srca:16"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srca:17"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srca:18"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srca:19"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srca:20"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srca:21"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srca:22"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srca:23"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srca:24"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srca:25"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srca:26"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srca:27"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srca:28"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srca:29"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srca:30"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srca:31"/>
|
||||
</Bus>
|
||||
<Bus Name="u_heirv32/alusrcb">
|
||||
<Sig Type="SIG" Name="u_heirv32/alusrcb:0"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/alusrcb:1"/>
|
||||
</Bus>
|
||||
<Bus Name="u_heirv32/immsrc">
|
||||
<Sig Type="SIG" Name="u_heirv32/immsrc:0"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/immsrc:1"/>
|
||||
</Bus>
|
||||
<Bus Name="u_heirv32/immext">
|
||||
<Sig Type="SIG" Name="u_heirv32/immext:0"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/immext:1"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/immext:2"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/immext:3"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/immext:4"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/immext:5"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/immext:6"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/immext:7"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/immext:8"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/immext:9"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/immext:10"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/immext:11"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/immext:12"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/immext:13"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/immext:14"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/immext:15"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/immext:16"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/immext:17"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/immext:18"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/immext:19"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/immext:20"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/immext:21"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/immext:22"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/immext:23"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/immext:24"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/immext:25"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/immext:26"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/immext:27"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/immext:28"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/immext:29"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/immext:30"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/immext:31"/>
|
||||
</Bus>
|
||||
<Bus Name="u_heirv32/srcb">
|
||||
<Sig Type="SIG" Name="u_heirv32/srcb:0"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srcb:1"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srcb:2"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srcb:3"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srcb:4"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srcb:5"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srcb:6"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srcb:7"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srcb:8"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srcb:9"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srcb:10"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srcb:11"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srcb:12"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srcb:13"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srcb:14"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srcb:15"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srcb:16"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srcb:17"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srcb:18"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srcb:19"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srcb:20"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srcb:21"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srcb:22"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srcb:23"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srcb:24"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srcb:25"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srcb:26"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srcb:27"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srcb:28"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srcb:29"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srcb:30"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/srcb:31"/>
|
||||
</Bus>
|
||||
<Bus Name="u_heirv32/alucontrol">
|
||||
<Sig Type="SIG" Name="u_heirv32/alucontrol:0"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/alucontrol:1"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/alucontrol:2"/>
|
||||
</Bus>
|
||||
<Sig Type="SIG" Name="u_heirv32/zero"/>
|
||||
<Bus Name="u_heirv32/aluresult">
|
||||
<Sig Type="SIG" Name="u_heirv32/aluresult:0"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluresult:1"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluresult:2"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluresult:3"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluresult:4"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluresult:5"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluresult:6"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluresult:7"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluresult:8"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluresult:9"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluresult:10"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluresult:11"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluresult:12"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluresult:13"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluresult:14"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluresult:15"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluresult:16"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluresult:17"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluresult:18"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluresult:19"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluresult:20"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluresult:21"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluresult:22"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluresult:23"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluresult:24"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluresult:25"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluresult:26"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluresult:27"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluresult:28"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluresult:29"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluresult:30"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluresult:31"/>
|
||||
</Bus>
|
||||
<Bus Name="u_heirv32/aluout">
|
||||
<Sig Type="SIG" Name="u_heirv32/aluout:0"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluout:1"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluout:2"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluout:3"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluout:4"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluout:5"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluout:6"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluout:7"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluout:8"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluout:9"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluout:10"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluout:11"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluout:12"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluout:13"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluout:14"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluout:15"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluout:16"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluout:17"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluout:18"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluout:19"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluout:20"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluout:21"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluout:22"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluout:23"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluout:24"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluout:25"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluout:26"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluout:27"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluout:28"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluout:29"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluout:30"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/aluout:31"/>
|
||||
</Bus>
|
||||
<Bus Name="u_heirv32/resultsrc">
|
||||
<Sig Type="SIG" Name="u_heirv32/resultsrc:0"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/resultsrc:1"/>
|
||||
</Bus>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_controlunit/branch"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_controlunit/pcupdate"/>
|
||||
</Trace>
|
||||
<Trigger>
|
||||
<TU Serialbits="0" Type="0" ID="1" Sig="u_heirv32/en,"/>
|
||||
<TE MaxSequence="1" MaxEvnCnt="1" ID="1" Resource="1"/>
|
||||
</Trigger>
|
||||
</Dataset>
|
||||
</Core>
|
||||
<Core InsertDataset="0" Insert="1" Reveal_sig="483219824" Name="ebs3_mc_LA1" ID="1">
|
||||
<Setting>
|
||||
<Clock SampleClk="clk50m" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
|
||||
<TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="512"/>
|
||||
<Capture Mode="0" MinSamplesPerTrig="8"/>
|
||||
<Event CntEnable="0" MaxEventCnt="8"/>
|
||||
<TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="0" TrigOutNet="reveal_debug_ebs3_mc_LA1_net"/>
|
||||
<DistRAM Disable="0"/>
|
||||
</Setting>
|
||||
<Dataset Name="Base">
|
||||
<Trace>
|
||||
<Bus Name="leds">
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:0"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:1"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:2"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:3"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:4"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:5"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:6"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:7"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:8"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:9"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:10"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:11"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:12"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:13"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:14"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:15"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:16"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:17"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:18"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:19"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:20"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:21"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:22"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:23"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:24"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:25"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:26"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:27"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:28"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:29"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:30"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:31"/>
|
||||
</Bus>
|
||||
<Bus Name="btns">
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:0"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:1"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:2"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:3"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:4"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:5"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:6"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:7"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:8"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:9"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:10"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:11"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:12"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:13"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:14"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:15"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:16"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:17"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:18"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:19"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:20"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:21"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:22"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:23"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:24"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:25"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:26"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:27"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:28"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:29"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:30"/>
|
||||
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:31"/>
|
||||
</Bus>
|
||||
</Trace>
|
||||
<Trigger>
|
||||
<TU Serialbits="0" Type="0" ID="1" Sig="u_heirv32/en,"/>
|
||||
<TE MaxSequence="2" MaxEvnCnt="1" ID="1" Resource="1"/>
|
||||
</Trigger>
|
||||
</Dataset>
|
||||
</Core>
|
||||
</Project>
|
||||
203
06-07-08-09-SystemOnChip/Board/diamond/strategy.sty
Normal file
203
06-07-08-09-SystemOnChip/Board/diamond/strategy.sty
Normal file
@ -0,0 +1,203 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!DOCTYPE strategy>
|
||||
<Strategy version="1.0" predefined="0" description="" label="Strategy">
|
||||
<Property name="PROP_BD_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_BD_EdfHardtimer" value="Enable" time="0"/>
|
||||
<Property name="PROP_BD_EdfInBusNameConv" value="None" time="0"/>
|
||||
<Property name="PROP_BD_EdfInLibPath" value="" time="0"/>
|
||||
<Property name="PROP_BD_EdfInRemLoc" value="Off" time="0"/>
|
||||
<Property name="PROP_BD_EdfMemPath" value="" time="0"/>
|
||||
<Property name="PROP_BD_ParSearchPath" value="" time="0"/>
|
||||
<Property name="PROP_BIT_AddressBitGen" value="Increment" time="0"/>
|
||||
<Property name="PROP_BIT_AllowReadBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_ByteWideBitMirror" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_CapReadBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_ConModBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_CreateBitFile" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_DisRAMResBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_DisableUESBitgen" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_DonePinBitGen" value="Pullup" time="0"/>
|
||||
<Property name="PROP_BIT_DoneSigBitGen" value="4" time="0"/>
|
||||
<Property name="PROP_BIT_EnIOBitGen" value="TriStateDuringReConfig" time="0"/>
|
||||
<Property name="PROP_BIT_EnIntOscBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_ExtClockBitGen" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_GSREnableBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_GSRRelOnBitGen" value="DoneIn" time="0"/>
|
||||
<Property name="PROP_BIT_GranTimBitGen" value="0" time="0"/>
|
||||
<Property name="PROP_BIT_IOTriRelBitGen" value="Cycle 2" time="0"/>
|
||||
<Property name="PROP_BIT_JTAGEnableBitGen" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_LenBitsBitGen" value="24" time="0"/>
|
||||
<Property name="PROP_BIT_MIFFileBitGen" value="" time="0"/>
|
||||
<Property name="PROP_BIT_NoHeader" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_OutFormatBitGen" value="Bit File (Binary)" time="0"/>
|
||||
<Property name="PROP_BIT_OutFormatBitGen_REF" value="" time="0"/>
|
||||
<Property name="PROP_BIT_OutFormatPromGen" value="Intel Hex 32-bit" time="0"/>
|
||||
<Property name="PROP_BIT_ParityCheckBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_RemZeroFramesBitGen" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_RunDRCBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_SearchPthBitGen" value="" time="0"/>
|
||||
<Property name="PROP_BIT_StartUpClkBitGen" value="Cclk" time="0"/>
|
||||
<Property name="PROP_BIT_SynchIOBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_SysClockConBitGen" value="Reset" time="0"/>
|
||||
<Property name="PROP_BIT_SysConBitGen" value="Reset" time="0"/>
|
||||
<Property name="PROP_BIT_WaitStTimBitGen" value="5" time="0"/>
|
||||
<Property name="PROP_IOTIMING_AllSpeed" value="False" time="0"/>
|
||||
<Property name="PROP_LST_AllowDUPMod" value="False" time="0"/>
|
||||
<Property name="PROP_LST_CarryChain" value="True" time="0"/>
|
||||
<Property name="PROP_LST_CarryChainLength" value="0" time="0"/>
|
||||
<Property name="PROP_LST_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_LST_DSPStyle" value="DSP" time="0"/>
|
||||
<Property name="PROP_LST_DSPUtil" value="100" time="0"/>
|
||||
<Property name="PROP_LST_DecodeUnreachableStates" value="False" time="0"/>
|
||||
<Property name="PROP_LST_DisableDistRam" value="False" time="0"/>
|
||||
<Property name="PROP_LST_EBRUtil" value="100" time="0"/>
|
||||
<Property name="PROP_LST_EdfFrequency" value="200" time="0"/>
|
||||
<Property name="PROP_LST_EdfHardtimer" value="Enable" time="0"/>
|
||||
<Property name="PROP_LST_EdfInLibPath" value="" time="0"/>
|
||||
<Property name="PROP_LST_EdfInRemLoc" value="Off" time="0"/>
|
||||
<Property name="PROP_LST_EdfMemPath" value="" time="0"/>
|
||||
<Property name="PROP_LST_FIXGATEDCLKS" value="True" time="0"/>
|
||||
<Property name="PROP_LST_FSMEncodeStyle" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_ForceGSRInfer" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_IOInsertion" value="True" time="0"/>
|
||||
<Property name="PROP_LST_InterFileDump" value="False" time="0"/>
|
||||
<Property name="PROP_LST_LoopLimit" value="1950" time="0"/>
|
||||
<Property name="PROP_LST_MaxFanout" value="1000" time="0"/>
|
||||
<Property name="PROP_LST_MuxStyle" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_NumCriticalPaths" value="3" time="0"/>
|
||||
<Property name="PROP_LST_OptimizeGoal" value="Timing" time="0"/>
|
||||
<Property name="PROP_LST_PropagatConst" value="True" time="0"/>
|
||||
<Property name="PROP_LST_RAMStyle" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_ROMStyle" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_RemoveDupRegs" value="True" time="0"/>
|
||||
<Property name="PROP_LST_ResolvedMixedDrivers" value="False" time="0"/>
|
||||
<Property name="PROP_LST_ResourceShare" value="True" time="0"/>
|
||||
<Property name="PROP_LST_UseIOReg" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_UseLPF" value="True" time="0"/>
|
||||
<Property name="PROP_LST_VHDL2008" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
|
||||
<Property name="PROP_MAPSTA_AutoTiming" value="True" time="0"/>
|
||||
<Property name="PROP_MAPSTA_CheckUnconstrainedConns" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_CheckUnconstrainedPaths" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_FullName" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_NumUnconstrainedPaths" value="0" time="0"/>
|
||||
<Property name="PROP_MAPSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
|
||||
<Property name="PROP_MAPSTA_RouteEstAlogtithm" value="0" time="0"/>
|
||||
<Property name="PROP_MAPSTA_RptAsynTimLoop" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_WordCasePaths" value="1" time="0"/>
|
||||
<Property name="PROP_MAP_IgnorePreErr" value="True" time="0"/>
|
||||
<Property name="PROP_MAP_MAPIORegister" value="Auto" time="0"/>
|
||||
<Property name="PROP_MAP_MAPInferGSR" value="True" time="0"/>
|
||||
<Property name="PROP_MAP_MapModArgs" value="" time="0"/>
|
||||
<Property name="PROP_MAP_OvermapDevice" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_PackLogMapDes" value="" time="0"/>
|
||||
<Property name="PROP_MAP_RegRetiming" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_SigCrossRef" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_SymCrossRef" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_TimingDriven" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_TimingDrivenNodeRep" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_TimingDrivenPack" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
|
||||
<Property name="PROP_PARSTA_AutoTiming" value="True" time="0"/>
|
||||
<Property name="PROP_PARSTA_CheckUnconstrainedConns" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_CheckUnconstrainedPaths" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_FullName" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_NumUnconstrainedPaths" value="0" time="0"/>
|
||||
<Property name="PROP_PARSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
|
||||
<Property name="PROP_PARSTA_RptAsynTimLoop" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_SpeedForHoldAnalysis" value="m" time="0"/>
|
||||
<Property name="PROP_PARSTA_SpeedForSetupAnalysis" value="default" time="0"/>
|
||||
<Property name="PROP_PARSTA_WordCasePaths" value="10" time="0"/>
|
||||
<Property name="PROP_PAR_CrDlyStFileParDes" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_DisableTDParDes" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_EffortParDes" value="5" time="0"/>
|
||||
<Property name="PROP_PAR_MultiSeedSortMode" value="Worst Slack" time="0"/>
|
||||
<Property name="PROP_PAR_NewRouteParDes" value="NBR" time="0"/>
|
||||
<Property name="PROP_PAR_PARClockSkew" value="Off" time="0"/>
|
||||
<Property name="PROP_PAR_PARModArgs" value="" time="0"/>
|
||||
<Property name="PROP_PAR_ParMultiNodeList" value="" time="0"/>
|
||||
<Property name="PROP_PAR_ParRunPlaceOnly" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_PlcIterParDes" value="1" time="0"/>
|
||||
<Property name="PROP_PAR_PlcStCostTblParDes" value="1" time="0"/>
|
||||
<Property name="PROP_PAR_PrefErrorOut" value="True" time="0"/>
|
||||
<Property name="PROP_PAR_RemoveDir" value="True" time="0"/>
|
||||
<Property name="PROP_PAR_RouteDlyRedParDes" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RoutePassParDes" value="6" time="0"/>
|
||||
<Property name="PROP_PAR_RouteResOptParDes" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RoutingCDP" value="Auto" time="0"/>
|
||||
<Property name="PROP_PAR_RoutingCDR" value="1" time="0"/>
|
||||
<Property name="PROP_PAR_RunParWithTrce" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_RunTimeReduction" value="True" time="0"/>
|
||||
<Property name="PROP_PAR_SaveBestRsltParDes" value="1" time="0"/>
|
||||
<Property name="PROP_PAR_StopZero" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_parHold" value="On" time="0"/>
|
||||
<Property name="PROP_PAR_parPathBased" value="Off" time="0"/>
|
||||
<Property name="PROP_PRE_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_PRE_EdfArrayBoundsCase" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfAutoResOfRam" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfClockDomainCross" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfDSPAcrossHie" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfFullCase" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfIgnoreRamRWCol" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfMissConstraint" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfNetFanout" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfParaCase" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfReencodeFSM" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfResSharing" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfTimingViolation" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfUseSafeFSM" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfVlog2001" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynComArea" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_VSynCritcal" value="3" time="0"/>
|
||||
<Property name="PROP_PRE_VSynFSM" value="Auto" time="0"/>
|
||||
<Property name="PROP_PRE_VSynFreq" value="200" time="0"/>
|
||||
<Property name="PROP_PRE_VSynGSR" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_VSynGatedClk" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_VSynIOPad" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_VSynOutNetForm" value="None" time="0"/>
|
||||
<Property name="PROP_PRE_VSynOutPref" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynRepClkFreq" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynRetime" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynTimSum" value="10" time="0"/>
|
||||
<Property name="PROP_PRE_VSynTransform" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSyninpd" value="0" time="0"/>
|
||||
<Property name="PROP_PRE_VSynoutd" value="0" time="0"/>
|
||||
<Property name="PROP_SYN_ClockConversion" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_SYN_DisableRegisterRep" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfAllowDUPMod" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfArea" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfArrangeVHDLFiles" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfDefEnumEncode" value="Default" time="0"/>
|
||||
<Property name="PROP_SYN_EdfFanout" value="1000" time="0"/>
|
||||
<Property name="PROP_SYN_EdfFrequency" value="" time="0"/>
|
||||
<Property name="PROP_SYN_EdfGSR" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfInsertIO" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfNumCritPath" value="" time="0"/>
|
||||
<Property name="PROP_SYN_EdfNumStartEnd" value="" time="0"/>
|
||||
<Property name="PROP_SYN_EdfOutNetForm" value="None" time="0"/>
|
||||
<Property name="PROP_SYN_EdfPushTirstates" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfResSharing" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfRunRetiming" value="None" time="0"/>
|
||||
<Property name="PROP_SYN_EdfSymFSM" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfUnconsClk" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfVerilogInput" value="Verilog 2001" time="0"/>
|
||||
<Property name="PROP_SYN_ExportSetting" value="No" time="0"/>
|
||||
<Property name="PROP_SYN_LibPath" value="" time="0"/>
|
||||
<Property name="PROP_SYN_ResolvedMixedDrivers" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_UpdateCompilePtTimData" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_UseLPF" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_VHDL2008" value="False" time="0"/>
|
||||
<Property name="PROP_THERMAL_DefaultFreq" value="0" time="0"/>
|
||||
<Property name="PROP_TIM_MaxDelSimDes" value="" time="0"/>
|
||||
<Property name="PROP_TIM_MinSpeedGrade" value="False" time="0"/>
|
||||
<Property name="PROP_TIM_ModPreSimDes" value="" time="0"/>
|
||||
<Property name="PROP_TIM_NegStupHldTim" value="True" time="0"/>
|
||||
<Property name="PROP_TIM_TimSimGenPUR" value="True" time="0"/>
|
||||
<Property name="PROP_TIM_TimSimGenX" value="False" time="0"/>
|
||||
<Property name="PROP_TIM_TimSimHierSep" value="" time="0"/>
|
||||
<Property name="PROP_TIM_TransportModeOfPathDelay" value="False" time="0"/>
|
||||
<Property name="PROP_TIM_TrgtSpeedGrade" value="" time="0"/>
|
||||
<Property name="PROP_TIM_WriteVerboseNetlist" value="False" time="0"/>
|
||||
<Property name="PROP_TMCHK_EnableCheck" value="True" time="0"/>
|
||||
</Strategy>
|
||||
BIN
06-07-08-09-SystemOnChip/Board/diamond/systemOnChip.bit
Normal file
BIN
06-07-08-09-SystemOnChip/Board/diamond/systemOnChip.bit
Normal file
Binary file not shown.
22
06-07-08-09-SystemOnChip/Board/diamond/systemOnChip.ldf
Normal file
22
06-07-08-09-SystemOnChip/Board/diamond/systemOnChip.ldf
Normal file
@ -0,0 +1,22 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<BaliProject version="3.2" title="MyProjectTitle" device="LFE5U-25F-6BG256C" default_implementation="toplevel">
|
||||
<Options/>
|
||||
<Implementation title="toplevel" dir="toplevel" description="toplevel" synthesis="synplify" default_strategy="Strategy">
|
||||
<Source name="../concat/did-synchro.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="../concat/did-synchro.lpf" type="Logic Preference" type_short="LPF">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="reveal_analyze.rva" type="Reveal Analyzer Project File" type_short="RVA">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="reveal_config.rvl" type="Reveal" type_short="Reveal" excluded="TRUE">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="programmer.xcf" type="Programming Project File" type_short="Programming">
|
||||
<Options/>
|
||||
</Source>
|
||||
</Implementation>
|
||||
<Strategy name="Strategy" file="strategy.sty"/>
|
||||
</BaliProject>
|
||||
14
06-07-08-09-SystemOnChip/Board/hdl/DFF_sim.vhd
Normal file
14
06-07-08-09-SystemOnChip/Board/hdl/DFF_sim.vhd
Normal file
@ -0,0 +1,14 @@
|
||||
ARCHITECTURE sim OF DFF IS
|
||||
BEGIN
|
||||
|
||||
process(clk, clr)
|
||||
begin
|
||||
if clr = '1' then
|
||||
q <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
q <= d;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
END ARCHITECTURE sim;
|
||||
|
||||
7
06-07-08-09-SystemOnChip/Board/hdl/buff_sim.vhd
Normal file
7
06-07-08-09-SystemOnChip/Board/hdl/buff_sim.vhd
Normal file
@ -0,0 +1,7 @@
|
||||
ARCHITECTURE sim OF buff IS
|
||||
BEGIN
|
||||
|
||||
out1 <= in1;
|
||||
|
||||
END ARCHITECTURE sim;
|
||||
|
||||
7
06-07-08-09-SystemOnChip/Board/hdl/inverterIn_sim.vhd
Normal file
7
06-07-08-09-SystemOnChip/Board/hdl/inverterIn_sim.vhd
Normal file
@ -0,0 +1,7 @@
|
||||
ARCHITECTURE sim OF inverterIn IS
|
||||
BEGIN
|
||||
|
||||
out1 <= NOT in1;
|
||||
|
||||
END ARCHITECTURE sim;
|
||||
|
||||
7
06-07-08-09-SystemOnChip/Board/hdl/inverter_sim.vhd
Normal file
7
06-07-08-09-SystemOnChip/Board/hdl/inverter_sim.vhd
Normal file
@ -0,0 +1,7 @@
|
||||
ARCHITECTURE sim OF inverter IS
|
||||
BEGIN
|
||||
|
||||
out1 <= NOT in1;
|
||||
|
||||
END ARCHITECTURE sim;
|
||||
|
||||
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
||||
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
||||
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
||||
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
||||
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
||||
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
||||
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
||||
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
||||
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
||||
@ -0,0 +1 @@
|
||||
DIALECT atom VHDL_2008
|
||||
1211
06-07-08-09-SystemOnChip/Board/hds/@d@f@f/symbol.sb
Normal file
1211
06-07-08-09-SystemOnChip/Board/hds/@d@f@f/symbol.sb
Normal file
File diff suppressed because it is too large
Load Diff
6067
06-07-08-09-SystemOnChip/Board/hds/@f@p@g@a_beamer/struct.bd
Normal file
6067
06-07-08-09-SystemOnChip/Board/hds/@f@p@g@a_beamer/struct.bd
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
1994
06-07-08-09-SystemOnChip/Board/hds/@f@p@g@a_beamer/symbol.sb
Normal file
1994
06-07-08-09-SystemOnChip/Board/hds/@f@p@g@a_beamer/symbol.sb
Normal file
File diff suppressed because it is too large
Load Diff
6067
06-07-08-09-SystemOnChip/Board/hds/@so@c_ebs2/struct.bd
Normal file
6067
06-07-08-09-SystemOnChip/Board/hds/@so@c_ebs2/struct.bd
Normal file
File diff suppressed because it is too large
Load Diff
6671
06-07-08-09-SystemOnChip/Board/hds/@so@c_ebs2/student@version.bd
Normal file
6671
06-07-08-09-SystemOnChip/Board/hds/@so@c_ebs2/student@version.bd
Normal file
File diff suppressed because it is too large
Load Diff
1994
06-07-08-09-SystemOnChip/Board/hds/@so@c_ebs2/symbol.sb
Normal file
1994
06-07-08-09-SystemOnChip/Board/hds/@so@c_ebs2/symbol.sb
Normal file
File diff suppressed because it is too large
Load Diff
6806
06-07-08-09-SystemOnChip/Board/hds/@so@c_ebs3/struct.bd
Normal file
6806
06-07-08-09-SystemOnChip/Board/hds/@so@c_ebs3/struct.bd
Normal file
File diff suppressed because it is too large
Load Diff
1895
06-07-08-09-SystemOnChip/Board/hds/@so@c_ebs3/symbol.sb
Normal file
1895
06-07-08-09-SystemOnChip/Board/hds/@so@c_ebs3/symbol.sb
Normal file
File diff suppressed because it is too large
Load Diff
2
06-07-08-09-SystemOnChip/Board/hds/_buff._epf
Normal file
2
06-07-08-09-SystemOnChip/Board/hds/_buff._epf
Normal file
@ -0,0 +1,2 @@
|
||||
DEFAULT_FILE atom buff_sim.vhd
|
||||
DEFAULT_ARCHITECTURE atom sim
|
||||
3
06-07-08-09-SystemOnChip/Board/hds/_fpga_beamer._epf
Normal file
3
06-07-08-09-SystemOnChip/Board/hds/_fpga_beamer._epf
Normal file
@ -0,0 +1,3 @@
|
||||
DEFAULT_ARCHITECTURE atom struct
|
||||
DEFAULT_FILE atom @f@p@g@a_beamer/struct.bd
|
||||
TOP_MARKER atom 1
|
||||
@ -0,0 +1,3 @@
|
||||
DEFAULT_FILE atom lissajous@generator_circuit/struct.bd
|
||||
DEFAULT_ARCHITECTURE atom struct
|
||||
TOP_MARKER atom 1
|
||||
3
06-07-08-09-SystemOnChip/Board/hds/_soc_ebs2._epf
Normal file
3
06-07-08-09-SystemOnChip/Board/hds/_soc_ebs2._epf
Normal file
@ -0,0 +1,3 @@
|
||||
DEFAULT_FILE atom @so@c_ebs2/struct.bd
|
||||
DEFAULT_ARCHITECTURE atom struct
|
||||
TOP_MARKER atom 1
|
||||
3
06-07-08-09-SystemOnChip/Board/hds/_soc_ebs3._epf
Normal file
3
06-07-08-09-SystemOnChip/Board/hds/_soc_ebs3._epf
Normal file
@ -0,0 +1,3 @@
|
||||
DEFAULT_ARCHITECTURE atom struct
|
||||
DEFAULT_FILE atom @so@c_ebs3/struct.bd
|
||||
TOP_MARKER atom 1
|
||||
1107
06-07-08-09-SystemOnChip/Board/hds/buff/symbol.sb
Normal file
1107
06-07-08-09-SystemOnChip/Board/hds/buff/symbol.sb
Normal file
File diff suppressed because it is too large
Load Diff
1092
06-07-08-09-SystemOnChip/Board/hds/inverter/symbol.sb
Normal file
1092
06-07-08-09-SystemOnChip/Board/hds/inverter/symbol.sb
Normal file
File diff suppressed because it is too large
Load Diff
1095
06-07-08-09-SystemOnChip/Board/hds/inverter@in/symbol.sb
Normal file
1095
06-07-08-09-SystemOnChip/Board/hds/inverter@in/symbol.sb
Normal file
File diff suppressed because it is too large
Load Diff
BIN
06-07-08-09-SystemOnChip/Board/ise/systemOnChip-XC3S1200E.bit
Normal file
BIN
06-07-08-09-SystemOnChip/Board/ise/systemOnChip-XC3S1200E.bit
Normal file
Binary file not shown.
30019
06-07-08-09-SystemOnChip/Board/ise/systemOnChip-XC3S1200E.mcs
Normal file
30019
06-07-08-09-SystemOnChip/Board/ise/systemOnChip-XC3S1200E.mcs
Normal file
File diff suppressed because it is too large
Load Diff
BIN
06-07-08-09-SystemOnChip/Board/ise/systemOnChip-XC3S500E.bit
Normal file
BIN
06-07-08-09-SystemOnChip/Board/ise/systemOnChip-XC3S500E.bit
Normal file
Binary file not shown.
17742
06-07-08-09-SystemOnChip/Board/ise/systemOnChip-XC3S500E.mcs
Normal file
17742
06-07-08-09-SystemOnChip/Board/ise/systemOnChip-XC3S500E.mcs
Normal file
File diff suppressed because it is too large
Load Diff
331
06-07-08-09-SystemOnChip/Board/ise/systemOnChip.xise
Normal file
331
06-07-08-09-SystemOnChip/Board/ise/systemOnChip.xise
Normal file
@ -0,0 +1,331 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/Lissajous/Board/concat/lissajous.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
</file>
|
||||
<file xil_pn:name="/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/Lissajous/Board/concat/lissajous.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To" xil_pn:value="-5" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-5" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate" xil_pn:value="Default (1)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc3s500e" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Spartan3E" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-5" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="HDL Instantiation Template Target Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|lissajousGenerator_circuit|struct" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="/home/francois/Documents/HEVs/SEm/SEm_labs/VHDL/Lissajous/Board/concat/lissajous.vhd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/lissajousGenerator_circuit" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="500" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="24" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="motherboard_FPGA" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="fg320" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="motherboard_FPGA_map.vhd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="motherboard_FPGA_timesim.vhd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="motherboard_FPGA_synthesis.vhd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="motherboard_FPGA_translate.vhd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="motherboard_FPGA" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset DCM if SHUTDOWN & AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="boardTester" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-01-21T13:37:47" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="EB7134DB38C3437A9E7F7D37E53531BE" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
Reference in New Issue
Block a user