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github-classroom[bot]
2024-02-23 13:01:05 +00:00
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commit d212040c30
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82
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[Concat]
Board = $HDS_PROJECT_DIR/../Board/concat
[ModelSim]
AhbLite = $SCRATCH_DIR/AhbLite
AhbLite_test = $SCRATCH_DIR/AhbLite_test
AhbLiteComponents = $SCRATCH_DIR/AhbLiteComponents
AhbLiteComponents_test = $SCRATCH_DIR/AhbLiteComponents_test
Board = $SCRATCH_DIR/Board
Common = $SCRATCH_DIR/Common
Common_test = $SCRATCH_DIR/Common_test
DigitalToAnalogConverter = $SCRATCH_DIR/DigitalToAnalogConverter
DigitalToAnalogConverter_test = $SCRATCH_DIR/DigitalToAnalogConverter_test
Lattice = $SCRATCH_DIR/Lattice
NanoBlaze = $SCRATCH_DIR/NanoBlaze
NanoBlaze_test = $SCRATCH_DIR/NanoBlaze_test
RiscV = $SCRATCH_DIR/RiscV
RiscV_test = $SCRATCH_DIR/RiscV_test
SplineInterpolator = $SCRATCH_DIR/SplineInterpolator
SplineInterpolator_test = $SCRATCH_DIR/SplineInterpolator_test
SystemOnChip = $SCRATCH_DIR/SystemOnChip
SystemOnChip_test = $SCRATCH_DIR/SystemOnChip_test
UVM = $SCRATCH_DIR/UVM
UVM_test = $SCRATCH_DIR/UVM_test
WaveformGenerator = $SCRATCH_DIR/WaveformGenerator
WaveformGenerator_test = $SCRATCH_DIR/WaveformGenerator_test
[hdl]
AhbLite = $HDS_PROJECT_DIR/../../Libs/AhbLite/hdl
AhbLite_test = $HDS_PROJECT_DIR/../../Libs/AhbLite_test/hdl
AhbLiteComponents = $HDS_PROJECT_DIR/../AhbLiteComponents/hdl
AhbLiteComponents_test = $HDS_PROJECT_DIR/../AhbLiteComponents_test/hdl
Board = $HDS_PROJECT_DIR/../Board/hdl
Common = $HDS_PROJECT_DIR/../../Libs/Common/hdl
Common_test = $HDS_PROJECT_DIR/../../Libs/Common_test/hdl
DigitalToAnalogConverter = $HDS_PROJECT_DIR/../../03-DigitalToAnalogConverter/DigitalToAnalogConverter/hdl
DigitalToAnalogConverter_test = $HDS_PROJECT_DIR/../../03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hdl
ieee = $HDS_HOME/hdl_libs/ieee/hdl
Lattice = $HDS_PROJECT_DIR/../../Libs/Lattice/hdl
NanoBlaze = $HDS_PROJECT_DIR/../../Libs/NanoBlaze/hdl
NanoBlaze_test = $HDS_PROJECT_DIR/../../Libs/NanoBlaze_test/hdl
RiscV = $HDS_PROJECT_DIR/../../Libs/RiscV/hdl
RiscV_test = $HDS_PROJECT_DIR/../../Libs/RiscV_test/hdl
SplineInterpolator = $HDS_PROJECT_DIR/../../02-SplineInterpolator/SplineInterpolator/hdl
SplineInterpolator_test = $HDS_PROJECT_DIR/../../02-SplineInterpolator/SplineInterpolator_test/hdl
std = $HDS_HOME/hdl_libs/std/hdl
SystemOnChip = $HDS_PROJECT_DIR/../SystemOnChip/hdl
SystemOnChip_test = $HDS_PROJECT_DIR/../SystemOnChip_test/hdl
UVM = $HDS_PROJECT_DIR/../../Libs/UVM/hdl
UVM_test = $HDS_PROJECT_DIR/../../Libs/UVM_test/hdl
WaveformGenerator = $HDS_PROJECT_DIR/../../01-WaveformGenerator/WaveformGenerator/hdl
WaveformGenerator_test = $HDS_PROJECT_DIR/../../01-WaveformGenerator/WaveformGenerator_test/hdl
[hds]
AhbLite = $HDS_PROJECT_DIR/../../Libs/AhbLite/hds
AhbLite_test = $HDS_PROJECT_DIR/../../Libs/AhbLite_test/hds
AhbLiteComponents = $HDS_PROJECT_DIR/../AhbLiteComponents/hds
AhbLiteComponents_test = $HDS_PROJECT_DIR/../AhbLiteComponents_test/hds
Board = $HDS_PROJECT_DIR/../Board/hds
Common = $HDS_PROJECT_DIR/../../Libs/Common/hds
Common_test = $HDS_PROJECT_DIR/../../Libs/Common_test/hds
DigitalToAnalogConverter = $HDS_PROJECT_DIR/../../03-DigitalToAnalogConverter/DigitalToAnalogConverter/hds
DigitalToAnalogConverter_test = $HDS_PROJECT_DIR/../../03-DigitalToAnalogConverter/DigitalToAnalogConverter_test/hds
ieee = $HDS_HOME/hdl_libs/ieee/hds
Lattice = $HDS_PROJECT_DIR/../../Libs/Lattice/hds
NanoBlaze = $HDS_PROJECT_DIR/../../Libs/NanoBlaze/hds
NanoBlaze_test = $HDS_PROJECT_DIR/../../Libs/NanoBlaze_test/hds
RiscV = $HDS_PROJECT_DIR/../../Libs/RiscV/hds
RiscV_test = $HDS_PROJECT_DIR/../../Libs/RiscV_test/hds
SplineInterpolator = $HDS_PROJECT_DIR/../../02-SplineInterpolator/SplineInterpolator/hds
SplineInterpolator_test = $HDS_PROJECT_DIR/../../02-SplineInterpolator/SplineInterpolator_test/hds
std = $HDS_HOME/hdl_libs/std/hds
SystemOnChip = $HDS_PROJECT_DIR/../SystemOnChip/hds
SystemOnChip_test = $HDS_PROJECT_DIR/../SystemOnChip_test/hds
UVM = $HDS_PROJECT_DIR/../../Libs/UVM/hds
UVM_test = $HDS_PROJECT_DIR/../../Libs/UVM_test/hds
WaveformGenerator = $HDS_PROJECT_DIR/../../01-WaveformGenerator/WaveformGenerator/hds
WaveformGenerator_test = $HDS_PROJECT_DIR/../../01-WaveformGenerator/WaveformGenerator_test/hds
[hds_settings]
design_root = Board.SoC_ebs3(struct)@so@c_ebs3/struct.bd
[library_type]
ieee = standard
std = standard
[shared]
others = $HDS_TEAM_HOME/shared.hdp

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[hds_settings]
version = 1
project_description = The standard HDS shared project
[hds]
ieee = $HDS_HOME/hdl_libs/ieee/hds
std = $HDS_HOME/hdl_libs/std/hds
synopsys = $HDS_HOME/hdl_libs/synopsys/hds
verilog = $HDS_HOME/hdl_libs/verilog/hds
vital2000 = $HDS_HOME/hdl_libs/vital2000/hds
[hdl]
ieee = $HDS_HOME/hdl_libs/ieee/hdl
std = $HDS_HOME/hdl_libs/std/hdl
synopsys = $HDS_HOME/hdl_libs/synopsys/hdl
verilog = $HDS_HOME/hdl_libs/verilog/hdl
vital2000 = $HDS_HOME/hdl_libs/vital2000/hdl
[library_type]
ieee = standard
std = standard
synopsys = standard
verilog = standard
vital2000 = standard

55
06-07-08-09-SystemOnChip/Prefs/hds_team/v2018.1/hds_team_prefs Normal file
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06-07-08-09-SystemOnChip/Prefs/hds_team/v2019.2/hds_team_prefs Normal file
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06-07-08-09-SystemOnChip/Prefs/hds_team/v2019.3/hds_team_prefs Normal file
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114
06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/tasks/xilinx_project_navigator.tsk Normal file
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FILE_NAMING_RULE: new_document.txt
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15
06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/templates/vhdl_architecture/architecture.vhd Normal file
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17
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19
06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/templates/vhdl_configuration/configuration.vhd Normal file
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FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd
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15
06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/templates/vhdl_entity/entity.vhd Normal file
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16
06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_body/package_body.vhd Normal file
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18
06-07-08-09-SystemOnChip/Prefs/hds_user-linux/v2019.3/templates/vhdl_package_header/package_header.vhd Normal file
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73
06-07-08-09-SystemOnChip/Prefs/hds_user/logs/HDS_log.txt Normal file
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Application HDL Designer version 2019.2 (Build 5)
Created on 02/20/2020 13:36:10
HDL Designer Series
HDL Designer
Version 2019.2 (Build 5)
Built on Sat Apr 20 2019 at 23:05
Verilog parser dynamic library version 5.1.42.f ( 2019/04/20 21:28:10 )
Running on Professional (Build 9200)
Loading HDS Project file via Environment variable $HDS_LIBS C:\work\repo\edu\sem\labo\solution\sem_labs\06-07-08-09-SystemOnChip\Prefs\hds.hdp
Loading prefs env variable USER_HOME C:\work\repo\edu\sem\labo\solution\sem_labs\06-07-08-09-SystemOnChip\Prefs\hds_user
Loading teamprefs env variable TEAM_HOME C:\work\repo\edu\sem\labo\solution\sem_labs\06-07-08-09-SystemOnChip\Prefs\hds_team
Loading user Task files from 'C:\work\repo\edu\sem\labo\solution\sem_labs\06-07-08-09-SystemOnChip\Prefs\hds_user\v2019.2\tasks'.
Loading team Task files from 'C:\work\repo\edu\sem\labo\solution\sem_labs\06-07-08-09-SystemOnChip\Prefs\hds_team\v2019.2\tasks'.
The timezone environment variable is set : TZ=GMT-1:0
HDS_HOME is set to : C:\tools\eda\HDS
Environment variables:
HDS_HOME set to C:\tools\eda\HDS
HDS_USER_HOME set to C:\work\repo\edu\sem\labo\solution\sem_labs\06-07-08-09-SystemOnChip\Prefs\hds_user
HDS_TEAM_HOME set to C:\work\repo\edu\sem\labo\solution\sem_labs\06-07-08-09-SystemOnChip\Prefs\hds_team
HDS_LIBS set to C:\work\repo\edu\sem\labo\solution\sem_labs\06-07-08-09-SystemOnChip\Prefs\hds.hdp
HDS_PORT set to zell:51992
10 events recorded:
Undo
Undo
Undo
Undo
Undo
Undo
ExecuteAction
Print
Print
ExecuteAction
Traceback
hdldesigner.exe caused an EXCEPTION_ACCESS_VIOLATION in module <UNKNOWN> at 0023:6F6C6C61
EAX=6F6C6C61 EBX=0291A7F0 ECX=142B6EB0 EDX=02FFEF64 ESI=00000000
EDI=00000111 EBP=03C3F39C ESP=03C3F34C EIP=6F6C6C61 FLG=00210202
CS=0023 DS=002B SS=002B ES=002B FS=0053 GS=002B
0x6F6C6C61 <UNKNOWN>
0x01C2358B hdldesigner.exe
0x01C1E5B4 hdldesigner.exe
0x01D06A6D hdldesigner.exe
0x01939CB1 hdldesigner.exe
0x018F899B hdldesigner.exe
0x01CD5F69 hdldesigner.exe
0x01AFB193 hdldesigner.exe
0x00702F46 hdldesigner.exe
0x01CE7705 hdldesigner.exe
0x01A07AA9 hdldesigner.exe
0x01A0763F hdldesigner.exe
0x02797EC1 hdldesigner.exe
0x02818CBB hdldesigner.exe
0x027D60D0 hdldesigner.exe
0x0291A820 hdldesigner.exe
0x0004438B USER32.dll, AddClipboardFormatListener()+0075 byte(s)
0x00024F8C USER32.dll, CallWindowProcW()+2860 byte(s)
0x000240DE USER32.dll, DispatchMessageW()+0558 byte(s)
0x0003E7B0 USER32.dll, DispatchMessageA()+0016 byte(s)
0x027D4515 hdldesigner.exe
0x027D42CB hdldesigner.exe
0x0040469A hdldesigner.exe
0x00401BA6 hdldesigner.exe
0x0291B412 hdldesigner.exe
0x028DAD8F hdldesigner.exe
0x00016359 KERNEL32.DLL, BaseThreadInitThunk()+0025 byte(s)
0x00067B74 ntdll.dll, RtlGetAppContainerNamedObjectPath()+0228 byte(s)
0x00067B44 ntdll.dll, RtlGetAppContainerNamedObjectPath()+0180 byte(s)
End of traceback

6831
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41
06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/tasks/generate.tsk Normal file
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@ -0,0 +1,41 @@
version "1.1"
HDSTool (HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "Generate"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp"
hasBitmap 1
tooltip "Performs generation of graphics files"
taskSettings [
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(SettingsMap
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""
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""
"initialDir"
""
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98
06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/tasks/modelsim_compile.tsk Normal file
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@ -0,0 +1,98 @@
version "1.1"
HDSTool (HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "ModelSim Compile"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp"
hasBitmap 1
tooltip "Runs ModelSim compilation"
taskSettings [
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(SettingsMap
settingsMap [
"additionalToolArgs"
""
"captureOutput"
"0"
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""
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""
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""
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""
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""
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enabled 1
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83
06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/tasks/modelsim_flow.tsk Normal file
View File

@ -0,0 +1,83 @@
version "1.1"
HDSFlow (HDSFlow
TaskName "ModelSim Flow"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp"
hasBitmap 1
tooltip "Generate and run entire ModelSim flow"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"flowSettingsDlg"
""
"taskInvocationScript"
""
]
)
]
PreferedTasks [
(preferedMap
preferedEnum 0
preferedSetting "$MODELSIM_HOME"
)
(preferedMap
preferedEnum 2
preferedSetting "ModelSim"
)
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onPulldownMenu 1
onToolbar 1
enabled 1
hierDepth 1
subTasks [
(HDSTaskRef
TaskName "Generate"
bitmap ""
hasBitmap 1
tooltip ""
taskSettings [
]
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]
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onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 1
reffedTaskName "USER:Generate"
)
(HDSTaskRef
TaskName "ModelSim Compile"
bitmap ""
hasBitmap 1
tooltip ""
taskSettings [
]
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onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 1
reffedTaskName "USER:ModelSim Compile"
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(HDSTaskRef
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bitmap ""
hasBitmap 1
tooltip ""
taskSettings [
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]
onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 3
reffedTaskName "USER:ModelSim Simulate"
)
]
)

96
06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/tasks/modelsim_simulate.tsk Normal file
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@ -0,0 +1,96 @@
version "1.1"
HDSTool (HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "ModelSim Simulate"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp"
hasBitmap 1
tooltip "Invokes the ModelSim Simulator"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"additionalToolArgs"
""
"captureOutput"
"0"
"customPrompt"
""
"initialDir"
""
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"TaskSetting"
(SettingsMap
settingsMap [
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""
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"do controller.do"
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"controller.do"
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""
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162
06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/tasks/prepare_for_synthesis.tsk Normal file
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@ -0,0 +1,162 @@
version "1.1"
HDSFlow (HDSFlow
TaskName "Prepare for Synthesis"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp"
hasBitmap 1
tooltip "generates a single file"
taskSettings [
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(SettingsMap
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""
"taskInvocationScript"
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(HDSTool
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163
06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/tasks/xilinx_project_navigator.tsk Normal file
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@ -0,0 +1,163 @@
version "1.1"
HDSFlow (HDSFlow
TaskName "Xilinx Project Navigator"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp"
hasBitmap 1
tooltip "Xilinx Flow"
taskSettings [
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(SettingsMap
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""
"taskInvocationScript"
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hierDepth 1
subTasks [
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associatedFileExt ""
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(SettingsMap
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13
06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/templates/text_files/new_document.txt Normal file
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@ -0,0 +1,13 @@
FILE_NAMING_RULE: new_document.txt
DESCRIPTION_START
This is the default template used for the creation of Text Document files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
#
# Created:
# by - %(user).%(group) (%(host))
# at - %(time) %(date)
#
# using Mentor Graphics HDL Designer(TM) %(version)
#

15
06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/templates/vhdl_architecture/architecture.vhd Normal file
View File

@ -0,0 +1,15 @@
FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Architecture files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Architecture %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
%(architecture)

17
06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/templates/vhdl_combined/combined.vhd Normal file
View File

@ -0,0 +1,17 @@
FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd
DESCRIPTION_START
This is the default template used for the creation of combined VHDL Architecture and Entity files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Architecture %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
%(entity)
--
%(architecture)

19
06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/templates/vhdl_configuration/configuration.vhd Normal file
View File

@ -0,0 +1,19 @@
FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Configuration files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Configuration %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
CONFIGURATION %(entity_name)_config OF %(entity_name) IS
FOR %(arch_name)
END FOR;
END %(entity_name)_config;

15
06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/templates/vhdl_entity/entity.vhd Normal file
View File

@ -0,0 +1,15 @@
FILE_NAMING_RULE: %(entity_name)_entity.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Entity files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Entity %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
%(entity)

16
06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/templates/vhdl_package_body/package_body.vhd Normal file
View File

@ -0,0 +1,16 @@
FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Package Body files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Package Body %(library).%(unit)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
PACKAGE BODY %(entity_name) IS
END %(entity_name);

18
06-07-08-09-SystemOnChip/Prefs/hds_user/v2018.1/templates/vhdl_package_header/package_header.vhd Normal file
View File

@ -0,0 +1,18 @@
FILE_NAMING_RULE: %(entity_name)_pkg.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Package Header files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Package Header %(library).%(unit)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE %(entity_name) IS
END %(entity_name);

6866
06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/hds_user_prefs Normal file
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162
06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/tasks/diamond_project_navigator.tsk Normal file
View File

@ -0,0 +1,162 @@
version "1.1"
HDSFlow (HDSFlow
TaskName "Diamond Project Navigator"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_lattice.bmp"
hasBitmap 1
tooltip "Diamond synthesis Flow"
taskSettings [
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(SettingsMap
settingsMap [
"flowSettingsDlg"
""
"taskInvocationScript"
""
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)
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onPulldownMenu 0
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enabled 1
hierDepth 1
subTasks [
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associatedFileExt ""
TaskName "Update.ldf"
bitmap "tool_default_tool.bmp"
hasBitmap 1
tooltip "Update file references in the Diamond project .prjx file"
taskSettings [
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(SettingsMap
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"TaskSetting"
(SettingsMap
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"U:/ELN_board/Board/concat/cursor.vhd"
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41
06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/tasks/generate.tsk Normal file
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@ -0,0 +1,41 @@
version "1.1"
HDSTool (HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "Generate"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp"
hasBitmap 1
tooltip "Performs generation of graphics files"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"additionalToolArgs"
""
"captureOutput"
"0"
"customPrompt"
""
"initialDir"
""
"promptForRunSettings"
"0"
"runMethod"
"gui"
"runnableObject"
"Generator"
"runnableObjectType"
"tcl_plugin"
"useViewSpecific"
"0"
]
)
]
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]
onShortcutBar 1
onPulldownMenu 1
onToolbar 1
enabled 1
hierDepth 2
)

98
06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk Normal file
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@ -0,0 +1,98 @@
version "1.1"
HDSTool (HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "ModelSim Compile"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp"
hasBitmap 1
tooltip "Runs ModelSim compilation"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"additionalToolArgs"
""
"captureOutput"
"0"
"customPrompt"
""
"initialDir"
""
"promptForRunSettings"
"0"
"runMethod"
"gui"
"runnableObject"
"ModelSimCompiler"
"runnableObjectType"
"tcl_plugin"
"useViewSpecific"
"0"
]
)
"TaskSetting"
(SettingsMap
settingsMap [
"64bit"
"0"
"compAlways"
"0"
"covSwitch"
""
"coverNoSub"
""
"dontAskAgain"
"0"
"enableMFCU"
"1"
"excludePSL"
"0"
"exepath"
"$MODELSIM_HOME"
"logFile"
""
"logicalLib"
"1"
"mapAllLib"
"0"
"mapQuartusIPs"
"1"
"masterCov"
"0"
"peSe"
"EE"
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"$HDS_PROJECT_DIR/QuartusIPSimLibs"
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""
"saveReplayScript"
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""
"showCmd"
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"1"
"useFlatLibrary"
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" -nologo"
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onToolbar 0
enabled 1
hierDepth 1
)

83
06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk Normal file
View File

@ -0,0 +1,83 @@
version "1.1"
HDSFlow (HDSFlow
TaskName "ModelSim Flow"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp"
hasBitmap 1
tooltip "Generate and run entire ModelSim flow"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"flowSettingsDlg"
""
"taskInvocationScript"
""
]
)
]
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(preferedMap
preferedEnum 0
preferedSetting "$MODELSIM_HOME"
)
(preferedMap
preferedEnum 2
preferedSetting "ModelSim"
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onShortcutBar 1
onPulldownMenu 1
onToolbar 1
enabled 1
hierDepth 1
subTasks [
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TaskName "Generate"
bitmap ""
hasBitmap 1
tooltip ""
taskSettings [
]
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]
onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 1
reffedTaskName "USER:Generate"
)
(HDSTaskRef
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bitmap ""
hasBitmap 1
tooltip ""
taskSettings [
]
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]
onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 1
reffedTaskName "USER:ModelSim Compile"
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(HDSTaskRef
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bitmap ""
hasBitmap 1
tooltip ""
taskSettings [
]
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]
onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 3
reffedTaskName "USER:ModelSim Simulate"
)
]
)

98
06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk Normal file
View File

@ -0,0 +1,98 @@
version "1.1"
HDSTool (HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "ModelSim Simulate"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp"
hasBitmap 1
tooltip "Invokes the ModelSim Simulator"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"additionalToolArgs"
""
"captureOutput"
"0"
"customPrompt"
""
"initialDir"
""
"promptForRunSettings"
"1"
"runMethod"
"gui"
"runnableObject"
"ModelSimSimulator"
"runnableObjectType"
"tcl_plugin"
"useViewSpecific"
"0"
]
)
"TaskSetting"
(SettingsMap
settingsMap [
"Arguments"
""
"Arguments1"
"do controller.do"
"Arguments2"
"controller.do"
"Communication"
"1"
"DelaySelection"
"typ"
"GlitchGeneration"
"1"
"InitCmd"
"$SIMULATION_DIR/beamerSoc.do"
"LogFile"
""
"RemoteHost"
""
"Resolution"
"ps"
"SdfDelay"
"typ"
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"latest"
"SdfReduce"
"0"
"SdfWarnings"
"1"
"TimingChecks"
"1"
"UseBatch"
"0"
"UseCLI"
"0"
"UseGUI"
"1"
"VitalVersion"
"95"
"autoNames"
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"coverage"
"0"
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hierDepth 3
)

162
06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/tasks/prepare_for_synthesis.tsk Normal file
View File

@ -0,0 +1,162 @@
version "1.1"
HDSFlow (HDSFlow
TaskName "Prepare for Synthesis"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_synthesis.bmp"
hasBitmap 1
tooltip "generates a single file"
taskSettings [
"InternalTaskSetting"
(SettingsMap
settingsMap [
"flowSettingsDlg"
""
"taskInvocationScript"
""
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]
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onShortcutBar 0
onPulldownMenu 0
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enabled 1
hierDepth 1
subTasks [
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taskSettings [
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(SettingsMap
settingsMap [
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""
"captureOutput"
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onShortcutBar 0
onPulldownMenu 0
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(HDSTool
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associatedFileExt ""
TaskName "Concatenate HDL"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_concatenate.bmp"
hasBitmap 1
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(SettingsMap
settingsMap [
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""
"captureOutput"
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(SettingsMap
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"v"
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onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 1
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(HDSTool
hasAssociatedFileExt 0
associatedFileExt ""
TaskName "Trim libraries"
bitmap "tool_default_tool.bmp"
hasBitmap 1
tooltip "comment out library declarations for singles file"
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hierDepth 3
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]
)

163
06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk Normal file
View File

@ -0,0 +1,163 @@
version "1.1"
HDSFlow (HDSFlow
TaskName "Xilinx Project Navigator"
bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_xilinx_synthesis.bmp"
hasBitmap 1
tooltip "Xilinx Flow"
taskSettings [
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(SettingsMap
settingsMap [
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""
"taskInvocationScript"
""
]
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]
onShortcutBar 0
onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 1
subTasks [
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hasAssociatedFileExt 0
associatedFileExt ""
TaskName "Update.xise"
bitmap "tool_default_tool.bmp"
hasBitmap 1
tooltip "Update file references in the Xilnx project .xise file"
taskSettings [
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(SettingsMap
settingsMap [
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"1"
"customPrompt"
""
"initialDir"
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"0"
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tooltip "Invokes the Xilinx ISE tool"
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(SettingsMap
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"0"
"needsSave"
"0"
"pluginInfo"
"FPGA Technology Setup Plug-in v2.0
For additional information, exceptions, compatibility issues and updates, visit SupportNet."
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"-7"
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"Xilinx XST"
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""
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onPulldownMenu 0
onToolbar 0
enabled 1
hierDepth 3
)
]
)

13
06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/templates/text_files/new_document.txt Normal file
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@ -0,0 +1,13 @@
FILE_NAMING_RULE: new_document.txt
DESCRIPTION_START
This is the default template used for the creation of Text Document files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
#
# Created:
# by - %(user).%(group) (%(host))
# at - %(time) %(date)
#
# using Mentor Graphics HDL Designer(TM) %(version)
#

15
06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd Normal file
View File

@ -0,0 +1,15 @@
FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Architecture files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Architecture %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
%(architecture)

17
06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd Normal file
View File

@ -0,0 +1,17 @@
FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd
DESCRIPTION_START
This is the default template used for the creation of combined VHDL Architecture and Entity files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Architecture %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
%(entity)
--
%(architecture)

19
06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd Normal file
View File

@ -0,0 +1,19 @@
FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Configuration files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Configuration %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
CONFIGURATION %(entity_name)_config OF %(entity_name) IS
FOR %(arch_name)
END FOR;
END %(entity_name)_config;

15
06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd Normal file
View File

@ -0,0 +1,15 @@
FILE_NAMING_RULE: %(entity_name)_entity.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Entity files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Entity %(library).%(unit).%(view)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
%(entity)

16
06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd Normal file
View File

@ -0,0 +1,16 @@
FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Package Body files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Package Body %(library).%(unit)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
PACKAGE BODY %(entity_name) IS
END %(entity_name);

18
06-07-08-09-SystemOnChip/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd Normal file
View File

@ -0,0 +1,18 @@
FILE_NAMING_RULE: %(entity_name)_pkg.vhd
DESCRIPTION_START
This is the default template used for the creation of VHDL Package Header files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
--
-- VHDL Package Header %(library).%(unit)
--
-- Created:
-- by - %(user).%(group) (%(host))
-- at - %(time) %(date)
--
-- using Mentor Graphics HDL Designer(TM) %(version)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE %(entity_name) IS
END %(entity_name);