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2024-02-23 13:01:05 +00:00
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334
10-PipelinedOperators/Board/concat/pipelinedOperators.lpf Normal file
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### For reference, see TN1262 / FPGA-TN-02032
# .lpf file format is not really documented by Lattice, normally generated through Diamond
################
#### sysCONFIG
################
# The BLOCK commands disable tracing of paths within clock domains (impacting overall timing score)
# It can also be used on paths if the TRACE should not consider the clock domain crossing
# like : BLOCK PATH FROM CLKNET "CLK_A" TO CLKNET "CLK_B" ;
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
BLOCK JTAGPATHS ;
BLOCK RD_DURING_WR_PATHS ;
# Not comprehensive
# dflt : CONFIG_IOVOLTAGE 1.2, 1.5, 1.8, 2.5(dflt), 3.3 voltage is 3.3V
# dflt : COMPRESS_CONFIG OFF (dflt), ON no bitstream compression
# mod : MCCLK_FREQ 2.4, 4.8, 9.7, 19.4, 38.8, 62 NOR program read @ 62MHz
# mod : MASTER_SPI_PORT DISABLE (dflt), ENABLE master SPI port stays SPI and not GPIOs, other mods disabled by dflt
# dflt : BACKGROUND_RECONFIG - no soft ERC when hot-loading bitstream (due to cosmic rays)
# dflt : DONE_PULL ON (dflt), OFF IPU on DONE pin
# dflt : DONE_EX OFF (dflt), ON not delaying end of the configuration (used for daisy chaining FPGAs)
# mod : DONE_OD OFF (dflt), ON DONE pin as open-drain instead of push-pull
# dflt : CONFIG_SECURE OFF (dflt), ON allows external access to current program
# mod : CONFIG_MODE JTAG (dflt), SSPI, SPI_SERIAL, SPI_DUAL, SPI_QUAD, SLAVE_PARALLEL, SLAVE_SERIAL
# which bus and mode is used to load configuration (for the Lattic IDE)
# dflt : TRANSFR OFF (dflt), ON if using TransFR tool from Lattice
# dflt : WAKE_UP 4 (set DONE=1 before starting user code, dflt for DONE_EX=ON)
# 21 (set DONE=1 once FPGA is already running user code, dflt for DONE_EX=OFF)
# mod : INBUF ON, OFF disable unused input buffers (not sure it impacts the ECP5 family)
SYSCONFIG MCCLK_FREQ=62 MASTER_SPI_PORT=ENABLE DONE_OD=ON CONFIG_MODE=SPI_QUAD INBUF=OFF CONFIG_IOVOLTAGE=3.3 ;
IOBUF ALLPORTS IO_TYPE=LVCMOS33 ;
################
#### Labs DB
################
### Clock and reset ###
#INPUT_SETUP ALLPORTS 50.000000 ns HOLD 10.000000 ns CLKPORT "CLK" ;
#INPUT_SETUP PORT "nRST" 50.000000 ns CLKPORT "CLK" ;
FREQUENCY PORT "clock" 100.000000 MHz ;
LOCATE COMP "clock" SITE "K16" ;
IOBUF PORT "clock" PULLMODE=NONE ;
LOCATE COMP "reset_n" SITE "E13" ;
GSR_NET NET "resetSynch_n";
### LEDs ###
LOCATE COMP "LED1" SITE "T14" ;# red
LOCATE COMP "LED2" SITE "R14" ;# green
LOCATE COMP "LED3" SITE "T15" ;# blue
################
#### SODIMM-200
################
### PP2 ###
LOCATE COMP "xOut" SITE "G3" ;
LOCATE COMP "yOut" SITE "E1" ;
#LOCATE COMP "" SITE "F3" ;
#LOCATE COMP "" SITE "D1" ;
LOCATE COMP "triggerOut" SITE "F4" ;
#LOCATE COMP "" SITE "C1" ;
#LOCATE COMP "" SITE "D7" ;
#LOCATE COMP "" SITE "B6" ;
#LOCATE COMP "" SITE "C7" ;
#LOCATE COMP "" SITE "A6" ; # PP2 11
#LOCATE COMP "" SITE "D8" ; # PP2 13
#LOCATE COMP "" SITE "B7" ; # PP2 15
#LOCATE COMP "" SITE "C8" ; # PP2 17
#LOCATE COMP "" SITE "A7" ; # PP2 19
#LOCATE COMP "" SITE "E9" ; # PP2 21
#LOCATE COMP "" SITE "A8" ; # PP2 23
#LOCATE COMP "" SITE "D9" ; # PP2 25
### PP1 ###
#LOCATE COMP "" SITE "A9" ;
#LOCATE COMP "" SITE "D10" ;
#LOCATE COMP "" SITE "A10" ;
#LOCATE COMP "" SITE "C10" ;
#LOCATE COMP "" SITE "B10" ;
#LOCATE COMP "" SITE "C12" ;
#LOCATE COMP "" SITE "B12" ;
#LOCATE COMP "" SITE "D13" ;
#LOCATE COMP "" SITE "A13" ;
#LOCATE COMP "" SITE "M5" ; # PP1 11
#LOCATE COMP "" SITE "L5" ; # PP1 13
#LOCATE COMP "" SITE "K5" ; # PP1 15
#LOCATE COMP "" SITE "H5" ; # PP1 17
#LOCATE COMP "" SITE "E8" ; # PP1 19
#LOCATE COMP "" SITE "E5" ; # PP1 21
LOCATE COMP "selSinCos_n" SITE "E6" ; # PP1 23
#LOCATE COMP "" SITE "E7" ; # PP1 25
### USB (FTDI2232HL located on the daughterboard) ###
LOCATE COMP "TxD" SITE "A14" ;
IOBUF PORT "TxD" SLEWRATE=FAST ;
LOCATE COMP "RxD" SITE "B14" ;
IOBUF PORT "RxD" PULLMODE=UP ;
#LOCATE COMP "USB_DB_RTS" SITE "B13" ;
#IOBUF PORT "USB_DB_RTS" SLEWRATE=FAST ;
#LOCATE COMP "USB_DB_CTS" SITE "C13" ;
#IOBUF PORT "USB_DB_CTS" PULLMODE=UP ;
################
#### Extras
################
### SD Flash (External SD card) ###
#LOCATE COMP "SD_DETECT" SITE "G12" ;
#IOBUF PORT "SD_DETECT" PULLMODE=UP ;
#LOCATE COMP "SD_CMD" SITE "C15" ;
#IOBUF PORT "SD_CMD" SLEWRATE=FAST ;
#LOCATE COMP "SD_CLK" SITE "B15" ;
#IOBUF PORT "SD_CLK" SLEWRATE=FAST ;
#LOCATE COMP "SD_DTA[0]" SITE "B16" ;
##IOBUF PORT "SD_DTA[0]" SLEWRATE=FAST ;
#LOCATE COMP "SD_DTA[1]" SITE "C16" ;
##IOBUF PORT "SD_DTA[1]" SLEWRATE=FAST ;
#LOCATE COMP "SD_DTA[2]" SITE "F12" ;
##IOBUF PORT "SD_DTA[2]" SLEWRATE=FAST ;
#LOCATE COMP "SD_DTA[3]" SITE "C14" ;
##IOBUF PORT "SD_DTA[3]" SLEWRATE=FAST ;
### DRAM ###
#LOCATE COMP "DRAM_ADDR[0]" SITE "J15" ;
#IOBUF PORT "DRAM_ADDR[0]" SLEWRATE=FAST ;
#LOCATE COMP "DRAM_ADDR[1]" SITE "L16" ;
#IOBUF PORT "DRAM_ADDR[1]" SLEWRATE=FAST ;
#LOCATE COMP "DRAM_ADDR[2]" SITE "L15" ;
#IOBUF PORT "DRAM_ADDR[2]" SLEWRATE=FAST ;
#LOCATE COMP "DRAM_ADDR[3]" SITE "K15" ;
#IOBUF PORT "DRAM_ADDR[3]" SLEWRATE=FAST ;
#LOCATE COMP "DRAM_ADDR[4]" SITE "G15" ;
#IOBUF PORT "DRAM_ADDR[4]" SLEWRATE=FAST ;
#LOCATE COMP "DRAM_ADDR[5]" SITE "F15" ;
#IOBUF PORT "DRAM_ADDR[5]" SLEWRATE=FAST ;
#LOCATE COMP "DRAM_ADDR[6]" SITE "F16" ;
#IOBUF PORT "DRAM_ADDR[6]" SLEWRATE=FAST ;
#LOCATE COMP "DRAM_ADDR[7]" SITE "E16" ;
#IOBUF PORT "DRAM_ADDR[7]" SLEWRATE=FAST ;
#LOCATE COMP "DRAM_ADDR[8]" SITE "E15" ;
#IOBUF PORT "DRAM_ADDR[8]" SLEWRATE=FAST ;
#LOCATE COMP "DRAM_ADDR[9]" SITE "G13" ;
#IOBUF PORT "DRAM_ADDR[9]" SLEWRATE=FAST ;
#LOCATE COMP "DRAM_ADDR[10]" SITE "M16" ;
#IOBUF PORT "DRAM_ADDR[10]" SLEWRATE=FAST ;
#LOCATE COMP "DRAM_ADDR[11]" SITE "F13" ;
#IOBUF PORT "DRAM_ADDR[11]" SLEWRATE=FAST ;
#LOCATE COMP "DRAM_ADDR[12]" SITE "D16" ;
#IOBUF PORT "DRAM_ADDR[12]" SLEWRATE=FAST ;
#LOCATE COMP "DRAM_BA[0]" SITE "L14" ;
#IOBUF PORT "DRAM_BA[0]" SLEWRATE=FAST ;
#LOCATE COMP "DRAM_BA[1]" SITE "L13" ;
#IOBUF PORT "DRAM_BA[1]" SLEWRATE=FAST ;
#LOCATE COMP "DRAM_CLK" SITE "G14" ;
#IOBUF PORT "DRAM_CLK" SLEWRATE=FAST ;
#LOCATE COMP "DRAM_CKE" SITE "G16" ;
#IOBUF PORT "DRAM_CKE" SLEWRATE=FAST ;
#LOCATE COMP "DRAM_nRAS" SITE "M14" ;
#IOBUF PORT "DRAM_nRAS" SLEWRATE=FAST ;
#LOCATE COMP "DRAM_nCAS" SITE "K13" ;
#IOBUF PORT "DRAM_nCAS" SLEWRATE=FAST ;
#LOCATE COMP "DRAM_nWE" SITE "N16" ;
#IOBUF PORT "DRAM_nWE" SLEWRATE=FAST ;
#LOCATE COMP "DRAM_nCS" SITE "M15" ;
#LOCATE COMP "DRAM_DQ[0]" SITE "P14" ;
#LOCATE COMP "DRAM_DQ[1]" SITE "R15" ;
#LOCATE COMP "DRAM_DQ[2]" SITE "N14" ;
#LOCATE COMP "DRAM_DQ[3]" SITE "R16" ;
#LOCATE COMP "DRAM_DQ[4]" SITE "J14" ;
#LOCATE COMP "DRAM_DQ[5]" SITE "P15" ;
#LOCATE COMP "DRAM_DQ[6]" SITE "K14" ;
#LOCATE COMP "DRAM_DQ[7]" SITE "P16" ;
#LOCATE COMP "DRAM_DQ[8]" SITE "D14" ;
#LOCATE COMP "DRAM_DQ[9]" SITE "H14" ;
#LOCATE COMP "DRAM_DQ[10]" SITE "H12" ;
#LOCATE COMP "DRAM_DQ[11]" SITE "H13" ;
#LOCATE COMP "DRAM_DQ[12]" SITE "E14" ;
#LOCATE COMP "DRAM_DQ[13]" SITE "H15" ;
#LOCATE COMP "DRAM_DQ[14]" SITE "J13" ;
#LOCATE COMP "DRAM_DQ[15]" SITE "J16" ;
#LOCATE COMP "DRAM_DQM[0]" SITE "M13" ;
#IOBUF PORT "DRAM_DQM[0]" SLEWRATE=FAST ;
#LOCATE COMP "DRAM_DQM[1]" SITE "F14" ;
#IOBUF PORT "DRAM_DQM[1]" SLEWRATE=FAST ;
### USB (chip located on the motherboard) ###
#LOCATE COMP "USB_MB_TX" SITE "M11" ;
#IOBUF PORT "USB_MB_TX" SLEWRATE=FAST ;
#LOCATE COMP "USB_MB_RX" SITE "N12" ;
#IOBUF PORT "USB_MB_RX" PULLMODE=UP ;
#LOCATE COMP "USB_MB_RTS" SITE "N11" ;
#IOBUF PORT "USB_MB_RTS" SLEWRATE=FAST ;
#LOCATE COMP "USB_MB_CTS" SITE "M12" ;
#IOBUF PORT "USB_MB_CTS" PULLMODE=UP ;
### PMOD1 ###
#LOCATE COMP "dbg_leds[16]" SITE "P1" ;
#LOCATE COMP "dbg_leds[17]" SITE "N4" ;
#LOCATE COMP "dbg_leds[18]" SITE "P2" ;
#LOCATE COMP "dbg_leds[19]" SITE "P5" ;
#LOCATE COMP "dbg_leds[20]" SITE "R1" ;
#LOCATE COMP "dbg_leds[21]" SITE "N5" ;
#LOCATE COMP "dbg_leds[22]" SITE "R2" ;
#LOCATE COMP "dbg_leds[23]" SITE "N6" ;
### PMOD2 ###
#LOCATE COMP "dbg_leds[24]" SITE "R3" ;
#LOCATE COMP "dbg_leds[25]" SITE "P11" ;
#LOCATE COMP "dbg_leds[26]" SITE "P12" ;
#LOCATE COMP "dbg_leds[27]" SITE "T3" ;
#LOCATE COMP "dbg_leds[28]" SITE "R4" ;
#LOCATE COMP "dbg_leds[29]" SITE "R12" ;
#LOCATE COMP "dbg_leds[30]" SITE "T13" ;
#LOCATE COMP "dbg_leds[31]" SITE "R5" ;
### PMOD3 ###
#LOCATE COMP "dbg_leds[8]" SITE "B2" ;
#LOCATE COMP "dbg_leds[9]" SITE "B3" ;
#LOCATE COMP "dbg_leds[10]" SITE "A4" ;
#LOCATE COMP "dbg_leds[11]" SITE "D4" ;
#LOCATE COMP "dbg_leds[12]" SITE "A2" ;
#LOCATE COMP "dbg_leds[13]" SITE "B4" ;
#LOCATE COMP "dbg_leds[14]" SITE "C3" ;
#LOCATE COMP "dbg_leds[15]" SITE "C4" ;
### PMOD4 ###
#LOCATE COMP "dbg_leds[0]" SITE "J4" ;
#LOCATE COMP "dbg_leds[1]" SITE "J5" ;
#LOCATE COMP "dbg_leds[2]" SITE "H4" ;
#LOCATE COMP "dbg_leds[3]" SITE "E4" ;
#LOCATE COMP "dbg_leds[4]" SITE "J3" ;
#LOCATE COMP "dbg_leds[5]" SITE "H3" ;
#LOCATE COMP "dbg_leds[6]" SITE "E3" ;
#LOCATE COMP "dbg_leds[7]" SITE "D3" ;
### Ethernet ###
#LOCATE COMP "ETH_CLK_EN" SITE "B1" ;
#LOCATE COMP "ETH_nRESET" SITE "C2" ;
#LOCATE COMP "ETH_nLED_Y" SITE "F1" ;
#LOCATE COMP "ETH_nLED_G" SITE "G2" ;
#LOCATE COMP "ETH_MDC" SITE "J1" ;
#LOCATE COMP "ETH_MDIO" SITE "H2" ;
#IOBUF PORT "ETH_MDIO" OPENDRAIN=ON SLEWRATE=FAST ;
#LOCATE COMP "ETH_MDINT" SITE "G1" ;
#IOBUF PORT "ETH_MDINT" SLEWRATE=FAST ;
#LOCATE COMP "ETH_REF_CLK" SITE "P3" ;
#LOCATE COMP "ETH_TX_CLK" SITE "M4" ;
#IOBUF PORT "ETH_TX_CLK" SLEWRATE=FAST ;
#LOCATE COMP "ETH_TX_CTL" SITE "N3" ;
#IOBUF PORT "ETH_TX_CTL" SLEWRATE=FAST ;
#LOCATE COMP "ETH_TXD[0]" SITE "M3" ;
#IOBUF PORT "ETH_TXD[0]" SLEWRATE=FAST ;
#LOCATE COMP "ETH_TXD[1]" SITE "L4" ;
#IOBUF PORT "ETH_TXD[1]" SLEWRATE=FAST ;
#LOCATE COMP "ETH_TXD[2]" SITE "K4" ;
#IOBUF PORT "ETH_TXD[2]" SLEWRATE=FAST ;
#LOCATE COMP "ETH_TXD[3]" SITE "K3" ;
#IOBUF PORT "ETH_TXD[3]" SLEWRATE=FAST ;
#LOCATE COMP "ETH_RX_CLK" SITE "K1" ;
#LOCATE COMP "ETH_RX_CTL" SITE "K2" ;
#LOCATE COMP "ETH_RXD[0]" SITE "L1" ;
#LOCATE COMP "ETH_RXD[1]" SITE "L2" ;
#LOCATE COMP "ETH_RXD[2]" SITE "M1" ;
#LOCATE COMP "ETH_RXD[3]" SITE "M2" ;
### Extras ###
#LOCATE COMP "EXT[1]" SITE "P13" ;
#LOCATE COMP "EXT[2]" SITE "R13" ;
#LOCATE COMP "EXT[3]" SITE "A3" ;
#LOCATE COMP "EXT[4]" SITE "A5" ;
#LOCATE COMP "EXT[5]" SITE "B5" ;
#LOCATE COMP "EXT[6]" SITE "C5" ;
#LOCATE COMP "EXT[7]" SITE "C6" ;
#LOCATE COMP "EXT[8]" SITE "D5" ;
#LOCATE COMP "EXT[9]" SITE "D6" ;
#LOCATE COMP "EXT[10]" SITE "A11" ;
#LOCATE COMP "EXT[11]" SITE "A12" ;
#LOCATE COMP "EXT[12]" SITE "B8" ;
#LOCATE COMP "EXT[13]" SITE "B9" ;
#LOCATE COMP "EXT[14]" SITE "B11" ;
#LOCATE COMP "EXT[15]" SITE "C9" ;
#LOCATE COMP "EXT[16]" SITE "C11" ;
#LOCATE COMP "EXT[17]" SITE "D11" ;
#LOCATE COMP "EXT[18]" SITE "D12" ;
#LOCATE COMP "EXT[19]" SITE "E10" ;
#LOCATE COMP "EXT[20]" SITE "E11" ;
#LOCATE COMP "EXT[21]" SITE "E12" ;
#LOCATE COMP "EXT[22]" SITE "L3" ;
#LOCATE COMP "EXT[23]" SITE "M6" ;
#LOCATE COMP "EXT[24]" SITE "N1" ;
#LOCATE COMP "EXT[25]" SITE "P4" ;
#LOCATE COMP "EXT[26]" SITE "P6" ;
#LOCATE COMP "EXT[27]" SITE "T2" ;
#LOCATE COMP "EXT[28]" SITE "T4" ;
#LOCATE COMP "EXT[29]" SITE "E2" ;
#LOCATE COMP "EXT[30]" SITE "F2" ;
#LOCATE COMP "EXT[31]" SITE "F5" ;
#LOCATE COMP "EXT[32]" SITE "G4" ;
#LOCATE COMP "EXT[33]" SITE "G5" ;
#LOCATE COMP "EXT[34]" SITE "J2" ;

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10-PipelinedOperators/Board/concat/pipelinedOperators.ucf Normal file
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#-------------------------------------------------------------------------------
# Clock and reset
#
NET "clock" LOC = "A10";
NET "reset_N" LOC = "D3" | PULLUP;
#-------------------------------------------------------------------------------
# Analog outputs
#
NET "xOut" LOC = "G4" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW;
NET "yOut" LOC = "G5" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW;
#NET "xOut" LOC = "G4" ;
#NET "yOut" LOC = "G5" ;
#-------------------------------------------------------------------------------
# Trigger output
#
NET "triggerOut" LOC = "D2" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW;
#NET "triggerOut" LOC = "D2" ;

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10-PipelinedOperators/Board/concat/pipelinedOperators.vhd Normal file
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-- VHDL Entity Board.pipelineCounter_ebs3.symbol
--
-- Created:
-- by - axel.amand.UNKNOWN (WE7860)
-- at - 11:16:01 08.05.2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY pipelineCounter_ebs3 IS
GENERIC(
counterBitNb : positive := 16
);
PORT(
clock : IN std_ulogic;
reset_n : IN std_ulogic;
countOut : OUT unsigned (counterBitNb-1 DOWNTO 0)
);
-- Declarations
END pipelineCounter_ebs3 ;
-- VHDL Entity PipelinedOperators.pipelineCounter.symbol
--
-- Created:
-- by - francois.francois (Aphelia)
-- at - 08:50:00 03/11/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY pipelineCounter IS
GENERIC(
bitNb : positive;
stageNb : positive
);
PORT(
countOut : OUT unsigned (bitNb-1 DOWNTO 0);
clock : IN std_ulogic;
reset : IN std_ulogic
);
-- Declarations
END pipelineCounter ;
-- VHDL Entity PipelinedOperators.pipelineAdder.symbol
--
-- Created:
-- by - francois.francois (Aphelia)
-- at - 08:50:15 03/11/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY pipelineAdder IS
GENERIC(
bitNb : positive;
stageNb : positive
);
PORT(
sum : OUT signed (bitNb-1 DOWNTO 0);
clock : IN std_ulogic;
reset : IN std_ulogic;
cIn : IN std_ulogic;
cOut : OUT std_ulogic;
a : IN signed (bitNb-1 DOWNTO 0);
b : IN signed (bitNb-1 DOWNTO 0)
);
-- Declarations
END pipelineAdder ;
-- VHDL Entity PipelinedOperators.parallelAdder.symbol
--
-- Created:
-- by - axel.amand.UNKNOWN (WE7860)
-- at - 11:43:49 28.04.2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY parallelAdder IS
GENERIC(
bitNb : positive := 32
);
PORT(
sum : OUT signed (bitNb-1 DOWNTO 0);
cIn : IN std_ulogic;
cOut : OUT std_ulogic;
a : IN signed (bitNb-1 DOWNTO 0);
b : IN signed (bitNb-1 DOWNTO 0)
);
-- Declarations
END parallelAdder ;
ARCHITECTURE masterVersion OF parallelAdder IS
signal sum_int: unsigned(sum'high+1 downto 0);
BEGIN
sum_int <= resize(unsigned(a), sum_int'length) +
resize(unsigned(b), sum_int'length) +
resize('0' & cIn, sum_int'length);
sum <= signed(sum_int(sum'range));
cOut <= sum_int(sum_int'high);
END ARCHITECTURE masterVersion;
ARCHITECTURE masterVersion OF pipelineAdder IS
constant stageBitNb : positive := sum'length/stageNb;
subtype stageOperandType is signed(stageBitNb-1 downto 0);
type stageOperandVectorType is array(stageNb-1 downto 0) of stageOperandType;
type stageOperandMatrixType is array(stageNb-1 downto 0) of stageOperandVectorType;
subtype carryType is std_ulogic_vector(stageNb downto 0);
signal a_int, b_int, sum_int : stageOperandMatrixType;
signal carryIn, carryOut : carryType;
COMPONENT parallelAdder
GENERIC (
bitNb : positive := 32
);
PORT (
sum : OUT signed (bitNb-1 DOWNTO 0);
cIn : IN std_ulogic ;
cOut : OUT std_ulogic ;
a : IN signed (bitNb-1 DOWNTO 0);
b : IN signed (bitNb-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
carryIn(0) <= cIn;
distributeInput: for wordIndex in stageOperandVectorType'range generate
a_int(wordIndex)(0) <= a(wordIndex*stageBitNb+stageBitNb-1 downto wordIndex*stageBitNb);
b_int(wordIndex)(0) <= b(wordIndex*stageBitNb+stageBitNb-1 downto wordIndex*stageBitNb);
end generate distributeInput;
inputRegistersX: for wordIndex in stageOperandVectorType'high downto 1 generate
inputRegistersY: for pipeIndex in stageOperandMatrixType'high downto 1 generate
upperTriangle: if wordIndex >= pipeIndex generate
inputRegisters: process(reset, clock)
begin
if reset = '1' then
a_int(wordIndex)(pipeIndex) <= (others => '0');
b_int(wordIndex)(pipeIndex) <= (others => '0');
elsif rising_edge(clock) then
a_int(wordIndex)(pipeIndex) <= a_int(wordIndex)(pipeIndex-1);
b_int(wordIndex)(pipeIndex) <= b_int(wordIndex)(pipeIndex-1);
end if;
end process inputRegisters;
end generate upperTriangle;
end generate inputRegistersY;
end generate inputRegistersX;
operation: for index in stageOperandVectorType'range generate
partialAdder: parallelAdder
GENERIC MAP (bitNb => stageBitNb)
PORT MAP (
a => a_int(index)(index),
b => b_int(index)(index),
sum => sum_int(index)(index),
cIn => carryIn(index),
cOut => carryOut(index)
);
carryRegisters: process(reset, clock)
begin
if reset = '1' then
carryIn(index+1) <= '0';
elsif rising_edge(clock) then
carryIn(index+1) <= carryOut(index);
end if;
end process carryRegisters;
end generate operation;
outputRegistersX: for wordIndex in stageOperandVectorType'range generate
outputRegistersY: for pipeIndex in stageOperandMatrixType'range generate
lowerTriangle: if wordIndex < pipeIndex generate
outputRegisters: process(reset, clock)
begin
if reset = '1' then
sum_int(wordIndex)(pipeIndex) <= (others => '0');
elsif rising_edge(clock) then
sum_int(wordIndex)(pipeIndex) <= sum_int(wordIndex)(pipeIndex-1);
end if;
end process outputRegisters;
end generate lowerTriangle;
end generate outputRegistersY;
end generate outputRegistersX;
packOutput: for index in stageOperandVectorType'range generate
sum(index*stageBitNb+stageBitNb-1 downto index*stageBitNb) <=
sum_int(index)(stageOperandMatrixType'high);
end generate packOutput;
cOut <= carryOut(carryOut'high-1);
END ARCHITECTURE masterVersion;
ARCHITECTURE masterVersion OF pipelineCounter IS
signal initCounter : unsigned(countOut'length/stageNb-1 downto 0);
signal b : signed(countOut'range);
signal sum : signed(countOut'range);
COMPONENT pipelineAdder
GENERIC (
bitNb : positive := 32;
stageNb : positive := 4
);
PORT (
reset : IN std_ulogic;
clock : IN std_ulogic;
cIn : IN std_ulogic;
a : IN signed (bitNb-1 DOWNTO 0);
b : IN signed (bitNb-1 DOWNTO 0);
sum : OUT signed (bitNb-1 DOWNTO 0);
cOut : OUT std_ulogic
);
END COMPONENT;
BEGIN
adder: pipelineAdder
GENERIC MAP (
bitNb => countOut'length,
stageNb => stageNb
)
PORT MAP (
reset => reset,
clock => clock,
cIn => '0',
a => sum,
b => b,
sum => sum,
cOut => open
);
prepareBInput: process(reset, clock)
begin
if reset = '1' then
initCounter <= (others => '0');
elsif rising_edge(clock) then
if initCounter < stageNb then
initCounter <= initCounter + 1;
end if;
end if;
end process prepareBInput;
selectInitOrRun: process(initCounter, sum)
begin
if initCounter < stageNb-1 then
b <= signed(resize(initCounter+stageNb-1, b'length));
countOut <= resize(initCounter, countOut'length);
else
b <= to_signed(stageNb-1, b'length);
countOut <= unsigned(sum);
end if;
end process selectInitOrRun;
END ARCHITECTURE masterVersion;
-- VHDL Entity Board.DFF.symbol
--
-- Created:
-- by - francois.francois (Aphelia)
-- at - 13:07:05 02/19/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY DFF IS
PORT(
CLK : IN std_uLogic;
CLR : IN std_uLogic;
D : IN std_uLogic;
Q : OUT std_uLogic
);
-- Declarations
END DFF ;
ARCHITECTURE sim OF DFF IS
BEGIN
process(clk, clr)
begin
if clr = '1' then
q <= '0';
elsif rising_edge(clk) then
q <= d;
end if;
end process;
END ARCHITECTURE sim;
-- VHDL Entity Board.inverterIn.symbol
--
-- Created:
-- by - francois.francois (Aphelia)
-- at - 13:07:14 02/19/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY inverterIn IS
PORT(
in1 : IN std_uLogic;
out1 : OUT std_uLogic
);
-- Declarations
END inverterIn ;
ARCHITECTURE sim OF inverterIn IS
BEGIN
out1 <= NOT in1;
END ARCHITECTURE sim;
-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454
-- Module Version: 5.7
--C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n pll -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00 -type pll -fin 100.00 -fclkop 60 -fclkop_tol 10.0 -fclkos 75 -fclkos_tol 10.0 -phases 0 -fclkos2 50 -fclkos2_tol 10.0 -phases2 0 -fclkos3 10 -fclkos3_tol 10.0 -phases3 0 -phase_cntl STATIC -enable_s -enable_s2 -enable_s3 -pllLocked -fb_mode 1 -fdc C:/temp/clocker/pll/pll.fdc
-- Offers 10MHz, 50MHz, 60MHz and 75MHz clocks
library IEEE;
use IEEE.std_logic_1164.all;
library ECP5U;
use ECP5U.components.all;
ENTITY pll IS
PORT(
clkIn100M : IN std_ulogic;
en75M : IN std_ulogic;
en50M : IN std_ulogic;
en10M : IN std_ulogic;
clk60MHz : OUT std_ulogic;
clk75MHz : OUT std_ulogic;
clk50MHz : OUT std_ulogic;
clk10MHz : OUT std_ulogic;
pllLocked : OUT std_ulogic
);
-- Declarations
END pll ;
architecture rtl of pll is
-- internal signal declarations
signal REFCLK: std_logic;
signal CLKOS3_t: std_logic;
signal CLKOS2_t: std_logic;
signal CLKOS_t: std_logic;
signal CLKOP_t: std_logic;
signal scuba_vhi: std_logic;
signal scuba_vlo: std_logic;
attribute FREQUENCY_PIN_CLKOS3 : string;
attribute FREQUENCY_PIN_CLKOS2 : string;
attribute FREQUENCY_PIN_CLKOS : string;
attribute FREQUENCY_PIN_CLKOP : string;
attribute FREQUENCY_PIN_CLKI : string;
attribute ICP_CURRENT : string;
attribute LPF_RESISTOR : string;
attribute FREQUENCY_PIN_CLKOS3 of PLLInst_0 : label is "10.000000";
attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "50.000000";
attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "75.000000";
attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "60.000000";
attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "100.000000";
attribute ICP_CURRENT of PLLInst_0 : label is "5";
attribute LPF_RESISTOR of PLLInst_0 : label is "16";
attribute syn_keep : boolean;
attribute NGD_DRC_MASK : integer;
attribute NGD_DRC_MASK of rtl : architecture is 1;
begin
-- component instantiation statements
scuba_vhi_inst: VHI
port map (Z=>scuba_vhi);
scuba_vlo_inst: VLO
port map (Z=>scuba_vlo);
PLLInst_0: EHXPLLL
generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED",
STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED",
CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 59, CLKOS2_FPHASE=> 0,
CLKOS2_CPHASE=> 11, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 7,
CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 9, PLL_LOCK_MODE=> 0,
CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING",
CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING",
OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED",
OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "DISABLED",
OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "DISABLED",
OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 60,
CLKOS2_DIV=> 12, CLKOS_DIV=> 8, CLKOP_DIV=> 10, CLKFB_DIV=> 3,
CLKI_DIV=> 5, FEEDBK_PATH=> "CLKOP")
port map (CLKI=>clkIn100M, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo,
PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo,
PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo,
STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo,
ENCLKOP=>scuba_vlo, ENCLKOS=>en75M, ENCLKOS2=>en50M,
ENCLKOS3=>en10M, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t,
CLKOS2=>CLKOS2_t, CLKOS3=>CLKOS3_t, LOCK=>pllLocked,
INTLOCK=>open, REFCLK=>REFCLK, CLKINTFB=>open);
clk10MHz <= CLKOS3_t;
clk50MHz <= CLKOS2_t;
clk75MHz <= CLKOS_t;
clk60MHz <= CLKOP_t;
end rtl;
--
-- VHDL Architecture Board.pipelineCounter_ebs3.struct
--
-- Created:
-- by - axel.amand.UNKNOWN (WE7860)
-- at - 11:16:01 08.05.2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
-- LIBRARY Board;
-- LIBRARY Lattice;
-- LIBRARY PipelinedOperators;
ARCHITECTURE struct OF pipelineCounter_ebs3 IS
-- Architecture declarations
constant pipelineStageNb: positive := 5;
-- Internal signal declarations
SIGNAL clk_sys : std_ulogic;
SIGNAL logic0 : std_ulogic;
SIGNAL logic1 : std_uLogic;
SIGNAL reset : std_ulogic;
SIGNAL resetSynch : std_ulogic;
SIGNAL resetSynch_n : std_ulogic;
-- Component Declarations
COMPONENT DFF
PORT (
CLK : IN std_uLogic ;
CLR : IN std_uLogic ;
D : IN std_uLogic ;
Q : OUT std_uLogic
);
END COMPONENT;
COMPONENT inverterIn
PORT (
in1 : IN std_uLogic ;
out1 : OUT std_uLogic
);
END COMPONENT;
COMPONENT pll
PORT (
clkIn100M : IN std_ulogic ;
en75M : IN std_ulogic ;
en50M : IN std_ulogic ;
en10M : IN std_ulogic ;
clk60MHz : OUT std_ulogic ;
clk75MHz : OUT std_ulogic ;
clk50MHz : OUT std_ulogic ;
clk10MHz : OUT std_ulogic ;
pllLocked : OUT std_ulogic
);
END COMPONENT;
COMPONENT pipelineCounter
GENERIC (
bitNb : positive;
stageNb : positive
);
PORT (
countOut : OUT unsigned (bitNb-1 DOWNTO 0);
clock : IN std_ulogic ;
reset : IN std_ulogic
);
END COMPONENT;
-- Optional embedded configurations
-- pragma synthesis_off
-- FOR ALL : DFF USE ENTITY Board.DFF;
-- FOR ALL : inverterIn USE ENTITY Board.inverterIn;
-- FOR ALL : pipelineCounter USE ENTITY PipelinedOperators.pipelineCounter;
-- FOR ALL : pll USE ENTITY Lattice.pll;
-- pragma synthesis_on
BEGIN
-- Architecture concurrent statements
-- HDL Embedded Text Block 5 eb5
logic1 <= '1';
-- HDL Embedded Text Block 6 eb6
logic0 <= '0';
-- Instance port mappings.
I_dff : DFF
PORT MAP (
CLK => clock,
CLR => reset,
D => logic1,
Q => resetSynch_n
);
I_inv1 : inverterIn
PORT MAP (
in1 => reset_n,
out1 => reset
);
I_inv2 : inverterIn
PORT MAP (
in1 => resetSynch_n,
out1 => resetSynch
);
I_pll : pll
PORT MAP (
clkIn100M => clock,
en75M => logic0,
en50M => logic0,
en10M => logic0,
clk60MHz => clk_sys,
clk75MHz => OPEN,
clk50MHz => OPEN,
clk10MHz => OPEN,
pllLocked => OPEN
);
I_cnt : pipelineCounter
GENERIC MAP (
bitNb => counterBitNb,
stageNb => pipelineStageNb
)
PORT MAP (
countOut => countOut,
clock => clk_sys,
reset => resetSynch
);
END struct;

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10-PipelinedOperators/Board/diamond/pipelinedOperators.bit Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<BaliProject version="3.2" title="MyProjectTitle" device="LFE5U-25F-6BG256C" default_implementation="toplevel">
<Options/>
<Implementation title="toplevel" dir="toplevel" description="toplevel" synthesis="synplify" default_strategy="Strategy">
<Source name="../concat/did-synchro.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="../concat/did-synchro.lpf" type="Logic Preference" type_short="LPF">
<Options/>
</Source>
<Source name="reveal_analyze.rva" type="Reveal Analyzer Project File" type_short="RVA">
<Options/>
</Source>
<Source name="reveal_config.rvl" type="Reveal" type_short="Reveal" excluded="TRUE">
<Options/>
</Source>
<Source name="programmer.xcf" type="Programming Project File" type_short="Programming">
<Options/>
</Source>
</Implementation>
<Strategy name="Strategy" file="strategy.sty"/>
</BaliProject>

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<?xml version='1.0' encoding='utf-8' ?>
<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
<ispXCF version="3.12">
<Comment></Comment>
<Chain>
<Comm>JTAG</Comm>
<Device>
<SelectedProg value="TRUE"/>
<Pos>1</Pos>
<Vendor>Renesas</Vendor>
<Family>ECP5U</Family>
<Name>LFE5U-25F</Name>
<Package>All</Package>
<PON>LFE5U-25F</PON>
<Bypass>
<InstrLen>8</InstrLen>
<InstrVal>11111111</InstrVal>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
<File></File>
<FileTime>04/11/23 16:14:28</FileTime>
<JedecChecksum>0xA4B0</JedecChecksum>
<Operation>Fast Program</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<IOState>HighZ</IOState>
<PreloadLength>409</PreloadLength>
<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
<SVFProcessor>SVF Processor</SVFProcessor>
<Usercode>0x00000000</Usercode>
<AccessMode>JTAG</AccessMode>
</Option>
</Device>
</Chain>
<ProjectOptions>
<Program>SEQUENTIAL</Program>
<Process>ENTIRED CHAIN</Process>
<OperationOverride>No Override</OperationOverride>
<StartTAP>TLR</StartTAP>
<EndTAP>TLR</EndTAP>
<VerifyUsercode value="FALSE"/>
<TCKDelay>4</TCKDelay>
</ProjectOptions>
<CableOptions>
<CableName>USB2</CableName>
<PortAdd>FTUSB-0</PortAdd>
<USBID>LFE5U-25F A Location 0000 Serial 018VFVT3A</USBID>
</CableOptions>
</ispXCF>

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<!DOCTYPE ispTLA>
<ispTLA>
<CreationDate>lun. 6. mars 14:29:10 2023</CreationDate>
<XCFFileName/>
<CableSetting>
<IsTRSTConnected val="false"/>
<TRSTSetting val="0"/>
<IsBSCANConnected val="false"/>
<BSCANSetting val="0"/>
<CableType val="USB2"/>
<PortAddress val="0"/>
<PortSetting val="0"/>
<TCKDelay val="1"/>
</CableSetting>
<DeviceCount>1</DeviceCount>
<Device>
<DeviceIndex>0</DeviceIndex>
<DeviceName>1. LFE5U-25F</DeviceName>
<DeviceID>0x41111043</DeviceID>
<HasIspTRACY>true</HasIspTRACY>
<HasJTAG2WB>false</HasJTAG2WB>
<SERDES/>
<IRBypassLen>8</IRBypassLen>
<RVLFileName>reveal_config.rvl</RVLFileName>
<RVSFileName>reveal_config.rvs</RVSFileName>
<LACoreCount>1</LACoreCount>
<WinUI CoreIndex="0">
<TraceSigTreeData>
<TraceSignal IsHidden="false" Name="en" NodeType="0" PortIndex="508"/>
<TraceSignal IsHidden="false" Name="clk_red" NodeType="0" PortIndex="0"/>
<TraceSignal IsHidden="false" Name="u_heirv32/pcwrite" NodeType="0" PortIndex="1"/>
<TraceSignal IsHidden="false" Name="u_heirv32/pc" NodeType="1" PortIndex="2">
<BusRadix Radix="3"/>
<IsExpanded Expand="false"/>
</TraceSignal>
<TraceSignal IsHidden="false" Name="u_heirv32/pc:0" NodeType="2" PortIndex="2"/>
<TraceSignal IsHidden="false" Name="u_heirv32/pc:1" NodeType="2" PortIndex="3"/>
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<TraceSignal IsHidden="false" Name="u_heirv32/pc:19" NodeType="2" PortIndex="21"/>
<TraceSignal IsHidden="false" Name="u_heirv32/pc:20" NodeType="2" PortIndex="22"/>
<TraceSignal IsHidden="false" Name="u_heirv32/pc:21" NodeType="2" PortIndex="23"/>
<TraceSignal IsHidden="false" Name="u_heirv32/pc:22" NodeType="2" PortIndex="24"/>
<TraceSignal IsHidden="false" Name="u_heirv32/pc:23" NodeType="2" PortIndex="25"/>
<TraceSignal IsHidden="false" Name="u_heirv32/pc:24" NodeType="2" PortIndex="26"/>
<TraceSignal IsHidden="false" Name="u_heirv32/pc:25" NodeType="2" PortIndex="27"/>
<TraceSignal IsHidden="false" Name="u_heirv32/pc:26" NodeType="2" PortIndex="28"/>
<TraceSignal IsHidden="false" Name="u_heirv32/pc:27" NodeType="2" PortIndex="29"/>
<TraceSignal IsHidden="false" Name="u_heirv32/pc:28" NodeType="2" PortIndex="30"/>
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<TraceSignal IsHidden="false" Name="u_heirv32/pc:31" NodeType="2" PortIndex="33"/>
<TraceSignal IsHidden="false" Name="u_heirv32/oldpc" NodeType="1" PortIndex="34">
<BusRadix Radix="3"/>
<IsExpanded Expand="false"/>
</TraceSignal>
<TraceSignal IsHidden="false" Name="u_heirv32/oldpc:0" NodeType="2" PortIndex="34"/>
<TraceSignal IsHidden="false" Name="u_heirv32/oldpc:1" NodeType="2" PortIndex="35"/>
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<TraceSignal IsHidden="false" Name="u_heirv32/oldpc:31" NodeType="2" PortIndex="65"/>
<TraceSignal IsHidden="false" Name="u_heirv32/pcnext" NodeType="1" PortIndex="66">
<BusRadix Radix="3"/>
<IsExpanded Expand="false"/>
</TraceSignal>
<TraceSignal IsHidden="false" Name="u_heirv32/pcnext:0" NodeType="2" PortIndex="66"/>
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<TraceSignal IsHidden="false" Name="u_heirv32/pcnext:4" NodeType="2" PortIndex="70"/>
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</TraceSigTreeData>
<TriggerUI UserSelect="0" PreSelectType="0" PreSelect="1" UserSelectPos="0"/>
<CoreRun Run="true"/>
<CoreWndUIData>
<ClockFrequency Unit="ns" Frequency="-1.0"/>
</CoreWndUIData>
</WinUI>
</Device>
</ispTLA>

662
10-PipelinedOperators/Board/diamond/reveal_config.rvl Normal file
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@ -0,0 +1,662 @@
<Project ModBy="Inserter" SigType="0" Name="C:/dev/car-heirv/Board/diamond/reveal_config.rvl" Date="2023-03-06">
<IP Version="1_6_042617"/>
<Design DesignEntry="Schematic/VHDL" Synthesis="synplify" DeviceFamily="ECP5U" DesignName="labsDBTester"/>
<Core InsertDataset="0" Insert="1" Reveal_sig="483219822" Name="ebs3_mc_LA0" ID="0">
<Setting>
<Clock SampleClk="u_pll/clk50m" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
<TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="512"/>
<Capture Mode="0" MinSamplesPerTrig="8"/>
<Event CntEnable="0" MaxEventCnt="8"/>
<TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="0" TrigOutNet="reveal_debug_ebs3_mc_LA0_net"/>
<DistRAM Disable="0"/>
</Setting>
<Dataset Name="Base">
<Trace>
<Sig Type="SIG" Name="clk_red"/>
<Sig Type="SIG" Name="u_heirv32/pcwrite"/>
<Bus Name="u_heirv32/pc">
<Sig Type="SIG" Name="u_heirv32/pc:0"/>
<Sig Type="SIG" Name="u_heirv32/pc:1"/>
<Sig Type="SIG" Name="u_heirv32/pc:2"/>
<Sig Type="SIG" Name="u_heirv32/pc:3"/>
<Sig Type="SIG" Name="u_heirv32/pc:4"/>
<Sig Type="SIG" Name="u_heirv32/pc:5"/>
<Sig Type="SIG" Name="u_heirv32/pc:6"/>
<Sig Type="SIG" Name="u_heirv32/pc:7"/>
<Sig Type="SIG" Name="u_heirv32/pc:8"/>
<Sig Type="SIG" Name="u_heirv32/pc:9"/>
<Sig Type="SIG" Name="u_heirv32/pc:10"/>
<Sig Type="SIG" Name="u_heirv32/pc:11"/>
<Sig Type="SIG" Name="u_heirv32/pc:12"/>
<Sig Type="SIG" Name="u_heirv32/pc:13"/>
<Sig Type="SIG" Name="u_heirv32/pc:14"/>
<Sig Type="SIG" Name="u_heirv32/pc:15"/>
<Sig Type="SIG" Name="u_heirv32/pc:16"/>
<Sig Type="SIG" Name="u_heirv32/pc:17"/>
<Sig Type="SIG" Name="u_heirv32/pc:18"/>
<Sig Type="SIG" Name="u_heirv32/pc:19"/>
<Sig Type="SIG" Name="u_heirv32/pc:20"/>
<Sig Type="SIG" Name="u_heirv32/pc:21"/>
<Sig Type="SIG" Name="u_heirv32/pc:22"/>
<Sig Type="SIG" Name="u_heirv32/pc:23"/>
<Sig Type="SIG" Name="u_heirv32/pc:24"/>
<Sig Type="SIG" Name="u_heirv32/pc:25"/>
<Sig Type="SIG" Name="u_heirv32/pc:26"/>
<Sig Type="SIG" Name="u_heirv32/pc:27"/>
<Sig Type="SIG" Name="u_heirv32/pc:28"/>
<Sig Type="SIG" Name="u_heirv32/pc:29"/>
<Sig Type="SIG" Name="u_heirv32/pc:30"/>
<Sig Type="SIG" Name="u_heirv32/pc:31"/>
</Bus>
<Bus Name="u_heirv32/oldpc">
<Sig Type="SIG" Name="u_heirv32/oldpc:0"/>
<Sig Type="SIG" Name="u_heirv32/oldpc:1"/>
<Sig Type="SIG" Name="u_heirv32/oldpc:2"/>
<Sig Type="SIG" Name="u_heirv32/oldpc:3"/>
<Sig Type="SIG" Name="u_heirv32/oldpc:4"/>
<Sig Type="SIG" Name="u_heirv32/oldpc:5"/>
<Sig Type="SIG" Name="u_heirv32/oldpc:6"/>
<Sig Type="SIG" Name="u_heirv32/oldpc:7"/>
<Sig Type="SIG" Name="u_heirv32/oldpc:8"/>
<Sig Type="SIG" Name="u_heirv32/oldpc:9"/>
<Sig Type="SIG" Name="u_heirv32/oldpc:10"/>
<Sig Type="SIG" Name="u_heirv32/oldpc:11"/>
<Sig Type="SIG" Name="u_heirv32/oldpc:12"/>
<Sig Type="SIG" Name="u_heirv32/oldpc:13"/>
<Sig Type="SIG" Name="u_heirv32/oldpc:14"/>
<Sig Type="SIG" Name="u_heirv32/oldpc:15"/>
<Sig Type="SIG" Name="u_heirv32/oldpc:16"/>
<Sig Type="SIG" Name="u_heirv32/oldpc:17"/>
<Sig Type="SIG" Name="u_heirv32/oldpc:18"/>
<Sig Type="SIG" Name="u_heirv32/oldpc:19"/>
<Sig Type="SIG" Name="u_heirv32/oldpc:20"/>
<Sig Type="SIG" Name="u_heirv32/oldpc:21"/>
<Sig Type="SIG" Name="u_heirv32/oldpc:22"/>
<Sig Type="SIG" Name="u_heirv32/oldpc:23"/>
<Sig Type="SIG" Name="u_heirv32/oldpc:24"/>
<Sig Type="SIG" Name="u_heirv32/oldpc:25"/>
<Sig Type="SIG" Name="u_heirv32/oldpc:26"/>
<Sig Type="SIG" Name="u_heirv32/oldpc:27"/>
<Sig Type="SIG" Name="u_heirv32/oldpc:28"/>
<Sig Type="SIG" Name="u_heirv32/oldpc:29"/>
<Sig Type="SIG" Name="u_heirv32/oldpc:30"/>
<Sig Type="SIG" Name="u_heirv32/oldpc:31"/>
</Bus>
<Bus Name="u_heirv32/pcnext">
<Sig Type="SIG" Name="u_heirv32/pcnext:0"/>
<Sig Type="SIG" Name="u_heirv32/pcnext:1"/>
<Sig Type="SIG" Name="u_heirv32/pcnext:2"/>
<Sig Type="SIG" Name="u_heirv32/pcnext:3"/>
<Sig Type="SIG" Name="u_heirv32/pcnext:4"/>
<Sig Type="SIG" Name="u_heirv32/pcnext:5"/>
<Sig Type="SIG" Name="u_heirv32/pcnext:6"/>
<Sig Type="SIG" Name="u_heirv32/pcnext:7"/>
<Sig Type="SIG" Name="u_heirv32/pcnext:8"/>
<Sig Type="SIG" Name="u_heirv32/pcnext:9"/>
<Sig Type="SIG" Name="u_heirv32/pcnext:10"/>
<Sig Type="SIG" Name="u_heirv32/pcnext:11"/>
<Sig Type="SIG" Name="u_heirv32/pcnext:12"/>
<Sig Type="SIG" Name="u_heirv32/pcnext:13"/>
<Sig Type="SIG" Name="u_heirv32/pcnext:14"/>
<Sig Type="SIG" Name="u_heirv32/pcnext:15"/>
<Sig Type="SIG" Name="u_heirv32/pcnext:16"/>
<Sig Type="SIG" Name="u_heirv32/pcnext:17"/>
<Sig Type="SIG" Name="u_heirv32/pcnext:18"/>
<Sig Type="SIG" Name="u_heirv32/pcnext:19"/>
<Sig Type="SIG" Name="u_heirv32/pcnext:20"/>
<Sig Type="SIG" Name="u_heirv32/pcnext:21"/>
<Sig Type="SIG" Name="u_heirv32/pcnext:22"/>
<Sig Type="SIG" Name="u_heirv32/pcnext:23"/>
<Sig Type="SIG" Name="u_heirv32/pcnext:24"/>
<Sig Type="SIG" Name="u_heirv32/pcnext:25"/>
<Sig Type="SIG" Name="u_heirv32/pcnext:26"/>
<Sig Type="SIG" Name="u_heirv32/pcnext:27"/>
<Sig Type="SIG" Name="u_heirv32/pcnext:28"/>
<Sig Type="SIG" Name="u_heirv32/pcnext:29"/>
<Sig Type="SIG" Name="u_heirv32/pcnext:30"/>
<Sig Type="SIG" Name="u_heirv32/pcnext:31"/>
</Bus>
<Sig Type="SIG" Name="u_heirv32/adrsrc"/>
<Bus Name="u_heirv32/adr">
<Sig Type="SIG" Name="u_heirv32/adr:0"/>
<Sig Type="SIG" Name="u_heirv32/adr:1"/>
<Sig Type="SIG" Name="u_heirv32/adr:2"/>
<Sig Type="SIG" Name="u_heirv32/adr:3"/>
<Sig Type="SIG" Name="u_heirv32/adr:4"/>
<Sig Type="SIG" Name="u_heirv32/adr:5"/>
<Sig Type="SIG" Name="u_heirv32/adr:6"/>
<Sig Type="SIG" Name="u_heirv32/adr:7"/>
<Sig Type="SIG" Name="u_heirv32/adr:8"/>
<Sig Type="SIG" Name="u_heirv32/adr:9"/>
<Sig Type="SIG" Name="u_heirv32/adr:10"/>
<Sig Type="SIG" Name="u_heirv32/adr:11"/>
<Sig Type="SIG" Name="u_heirv32/adr:12"/>
<Sig Type="SIG" Name="u_heirv32/adr:13"/>
<Sig Type="SIG" Name="u_heirv32/adr:14"/>
<Sig Type="SIG" Name="u_heirv32/adr:15"/>
<Sig Type="SIG" Name="u_heirv32/adr:16"/>
<Sig Type="SIG" Name="u_heirv32/adr:17"/>
<Sig Type="SIG" Name="u_heirv32/adr:18"/>
<Sig Type="SIG" Name="u_heirv32/adr:19"/>
<Sig Type="SIG" Name="u_heirv32/adr:20"/>
<Sig Type="SIG" Name="u_heirv32/adr:21"/>
<Sig Type="SIG" Name="u_heirv32/adr:22"/>
<Sig Type="SIG" Name="u_heirv32/adr:23"/>
<Sig Type="SIG" Name="u_heirv32/adr:24"/>
<Sig Type="SIG" Name="u_heirv32/adr:25"/>
<Sig Type="SIG" Name="u_heirv32/adr:26"/>
<Sig Type="SIG" Name="u_heirv32/adr:27"/>
<Sig Type="SIG" Name="u_heirv32/adr:28"/>
<Sig Type="SIG" Name="u_heirv32/adr:29"/>
<Sig Type="SIG" Name="u_heirv32/adr:30"/>
<Sig Type="SIG" Name="u_heirv32/adr:31"/>
</Bus>
<Bus Name="u_heirv32/writedata">
<Sig Type="SIG" Name="u_heirv32/writedata:0"/>
<Sig Type="SIG" Name="u_heirv32/writedata:1"/>
<Sig Type="SIG" Name="u_heirv32/writedata:2"/>
<Sig Type="SIG" Name="u_heirv32/writedata:3"/>
<Sig Type="SIG" Name="u_heirv32/writedata:4"/>
<Sig Type="SIG" Name="u_heirv32/writedata:5"/>
<Sig Type="SIG" Name="u_heirv32/writedata:6"/>
<Sig Type="SIG" Name="u_heirv32/writedata:7"/>
<Sig Type="SIG" Name="u_heirv32/writedata:8"/>
<Sig Type="SIG" Name="u_heirv32/writedata:9"/>
<Sig Type="SIG" Name="u_heirv32/writedata:10"/>
<Sig Type="SIG" Name="u_heirv32/writedata:11"/>
<Sig Type="SIG" Name="u_heirv32/writedata:12"/>
<Sig Type="SIG" Name="u_heirv32/writedata:13"/>
<Sig Type="SIG" Name="u_heirv32/writedata:14"/>
<Sig Type="SIG" Name="u_heirv32/writedata:15"/>
<Sig Type="SIG" Name="u_heirv32/writedata:16"/>
<Sig Type="SIG" Name="u_heirv32/writedata:17"/>
<Sig Type="SIG" Name="u_heirv32/writedata:18"/>
<Sig Type="SIG" Name="u_heirv32/writedata:19"/>
<Sig Type="SIG" Name="u_heirv32/writedata:20"/>
<Sig Type="SIG" Name="u_heirv32/writedata:21"/>
<Sig Type="SIG" Name="u_heirv32/writedata:22"/>
<Sig Type="SIG" Name="u_heirv32/writedata:23"/>
<Sig Type="SIG" Name="u_heirv32/writedata:24"/>
<Sig Type="SIG" Name="u_heirv32/writedata:25"/>
<Sig Type="SIG" Name="u_heirv32/writedata:26"/>
<Sig Type="SIG" Name="u_heirv32/writedata:27"/>
<Sig Type="SIG" Name="u_heirv32/writedata:28"/>
<Sig Type="SIG" Name="u_heirv32/writedata:29"/>
<Sig Type="SIG" Name="u_heirv32/writedata:30"/>
<Sig Type="SIG" Name="u_heirv32/writedata:31"/>
</Bus>
<Sig Type="SIG" Name="u_heirv32/memwrite"/>
<Bus Name="u_heirv32/data">
<Sig Type="SIG" Name="u_heirv32/data:0"/>
<Sig Type="SIG" Name="u_heirv32/data:1"/>
<Sig Type="SIG" Name="u_heirv32/data:2"/>
<Sig Type="SIG" Name="u_heirv32/data:3"/>
<Sig Type="SIG" Name="u_heirv32/data:4"/>
<Sig Type="SIG" Name="u_heirv32/data:5"/>
<Sig Type="SIG" Name="u_heirv32/data:6"/>
<Sig Type="SIG" Name="u_heirv32/data:7"/>
<Sig Type="SIG" Name="u_heirv32/data:8"/>
<Sig Type="SIG" Name="u_heirv32/data:9"/>
<Sig Type="SIG" Name="u_heirv32/data:10"/>
<Sig Type="SIG" Name="u_heirv32/data:11"/>
<Sig Type="SIG" Name="u_heirv32/data:12"/>
<Sig Type="SIG" Name="u_heirv32/data:13"/>
<Sig Type="SIG" Name="u_heirv32/data:14"/>
<Sig Type="SIG" Name="u_heirv32/data:15"/>
<Sig Type="SIG" Name="u_heirv32/data:16"/>
<Sig Type="SIG" Name="u_heirv32/data:17"/>
<Sig Type="SIG" Name="u_heirv32/data:18"/>
<Sig Type="SIG" Name="u_heirv32/data:19"/>
<Sig Type="SIG" Name="u_heirv32/data:20"/>
<Sig Type="SIG" Name="u_heirv32/data:21"/>
<Sig Type="SIG" Name="u_heirv32/data:22"/>
<Sig Type="SIG" Name="u_heirv32/data:23"/>
<Sig Type="SIG" Name="u_heirv32/data:24"/>
<Sig Type="SIG" Name="u_heirv32/data:25"/>
<Sig Type="SIG" Name="u_heirv32/data:26"/>
<Sig Type="SIG" Name="u_heirv32/data:27"/>
<Sig Type="SIG" Name="u_heirv32/data:28"/>
<Sig Type="SIG" Name="u_heirv32/data:29"/>
<Sig Type="SIG" Name="u_heirv32/data:30"/>
<Sig Type="SIG" Name="u_heirv32/data:31"/>
</Bus>
<Sig Type="SIG" Name="u_heirv32/irwrite"/>
<Bus Name="u_heirv32/instruction">
<Sig Type="SIG" Name="u_heirv32/instruction:0"/>
<Sig Type="SIG" Name="u_heirv32/instruction:1"/>
<Sig Type="SIG" Name="u_heirv32/instruction:2"/>
<Sig Type="SIG" Name="u_heirv32/instruction:3"/>
<Sig Type="SIG" Name="u_heirv32/instruction:4"/>
<Sig Type="SIG" Name="u_heirv32/instruction:5"/>
<Sig Type="SIG" Name="u_heirv32/instruction:6"/>
<Sig Type="SIG" Name="u_heirv32/instruction:7"/>
<Sig Type="SIG" Name="u_heirv32/instruction:8"/>
<Sig Type="SIG" Name="u_heirv32/instruction:9"/>
<Sig Type="SIG" Name="u_heirv32/instruction:10"/>
<Sig Type="SIG" Name="u_heirv32/instruction:11"/>
<Sig Type="SIG" Name="u_heirv32/instruction:12"/>
<Sig Type="SIG" Name="u_heirv32/instruction:13"/>
<Sig Type="SIG" Name="u_heirv32/instruction:14"/>
<Sig Type="SIG" Name="u_heirv32/instruction:15"/>
<Sig Type="SIG" Name="u_heirv32/instruction:16"/>
<Sig Type="SIG" Name="u_heirv32/instruction:17"/>
<Sig Type="SIG" Name="u_heirv32/instruction:18"/>
<Sig Type="SIG" Name="u_heirv32/instruction:19"/>
<Sig Type="SIG" Name="u_heirv32/instruction:20"/>
<Sig Type="SIG" Name="u_heirv32/instruction:21"/>
<Sig Type="SIG" Name="u_heirv32/instruction:22"/>
<Sig Type="SIG" Name="u_heirv32/instruction:23"/>
<Sig Type="SIG" Name="u_heirv32/instruction:24"/>
<Sig Type="SIG" Name="u_heirv32/instruction:25"/>
<Sig Type="SIG" Name="u_heirv32/instruction:26"/>
<Sig Type="SIG" Name="u_heirv32/instruction:27"/>
<Sig Type="SIG" Name="u_heirv32/instruction:28"/>
<Sig Type="SIG" Name="u_heirv32/instruction:29"/>
<Sig Type="SIG" Name="u_heirv32/instruction:30"/>
<Sig Type="SIG" Name="u_heirv32/instruction:31"/>
</Bus>
<Bus Name="u_heirv32/u_extend/input">
<Sig Type="SIG" Name="u_heirv32/u_extend/input:7"/>
<Sig Type="SIG" Name="u_heirv32/u_extend/input:8"/>
<Sig Type="SIG" Name="u_heirv32/u_extend/input:9"/>
<Sig Type="SIG" Name="u_heirv32/u_extend/input:10"/>
<Sig Type="SIG" Name="u_heirv32/u_extend/input:11"/>
<Sig Type="SIG" Name="u_heirv32/u_extend/input:12"/>
<Sig Type="SIG" Name="u_heirv32/u_extend/input:13"/>
<Sig Type="SIG" Name="u_heirv32/u_extend/input:14"/>
<Sig Type="SIG" Name="u_heirv32/u_extend/input:15"/>
<Sig Type="SIG" Name="u_heirv32/u_extend/input:16"/>
<Sig Type="SIG" Name="u_heirv32/u_extend/input:17"/>
<Sig Type="SIG" Name="u_heirv32/u_extend/input:18"/>
<Sig Type="SIG" Name="u_heirv32/u_extend/input:19"/>
<Sig Type="SIG" Name="u_heirv32/u_extend/input:20"/>
<Sig Type="SIG" Name="u_heirv32/u_extend/input:21"/>
<Sig Type="SIG" Name="u_heirv32/u_extend/input:22"/>
<Sig Type="SIG" Name="u_heirv32/u_extend/input:23"/>
<Sig Type="SIG" Name="u_heirv32/u_extend/input:24"/>
<Sig Type="SIG" Name="u_heirv32/u_extend/input:25"/>
<Sig Type="SIG" Name="u_heirv32/u_extend/input:26"/>
<Sig Type="SIG" Name="u_heirv32/u_extend/input:27"/>
<Sig Type="SIG" Name="u_heirv32/u_extend/input:28"/>
<Sig Type="SIG" Name="u_heirv32/u_extend/input:29"/>
<Sig Type="SIG" Name="u_heirv32/u_extend/input:30"/>
<Sig Type="SIG" Name="u_heirv32/u_extend/input:31"/>
</Bus>
<Bus Name="u_heirv32/u_registerfile/addr1">
<Sig Type="SIG" Name="u_heirv32/u_registerfile/addr1:0"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/addr1:1"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/addr1:2"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/addr1:3"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/addr1:4"/>
</Bus>
<Bus Name="u_heirv32/u_registerfile/addr2">
<Sig Type="SIG" Name="u_heirv32/u_registerfile/addr2:0"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/addr2:1"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/addr2:2"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/addr2:3"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/addr2:4"/>
</Bus>
<Bus Name="u_heirv32/u_registerfile/addr3">
<Sig Type="SIG" Name="u_heirv32/u_registerfile/addr3:0"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/addr3:1"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/addr3:2"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/addr3:3"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/addr3:4"/>
</Bus>
<Bus Name="u_heirv32/result">
<Sig Type="SIG" Name="u_heirv32/result:0"/>
<Sig Type="SIG" Name="u_heirv32/result:1"/>
<Sig Type="SIG" Name="u_heirv32/result:2"/>
<Sig Type="SIG" Name="u_heirv32/result:3"/>
<Sig Type="SIG" Name="u_heirv32/result:4"/>
<Sig Type="SIG" Name="u_heirv32/result:5"/>
<Sig Type="SIG" Name="u_heirv32/result:6"/>
<Sig Type="SIG" Name="u_heirv32/result:7"/>
<Sig Type="SIG" Name="u_heirv32/result:8"/>
<Sig Type="SIG" Name="u_heirv32/result:9"/>
<Sig Type="SIG" Name="u_heirv32/result:10"/>
<Sig Type="SIG" Name="u_heirv32/result:11"/>
<Sig Type="SIG" Name="u_heirv32/result:12"/>
<Sig Type="SIG" Name="u_heirv32/result:13"/>
<Sig Type="SIG" Name="u_heirv32/result:14"/>
<Sig Type="SIG" Name="u_heirv32/result:15"/>
<Sig Type="SIG" Name="u_heirv32/result:16"/>
<Sig Type="SIG" Name="u_heirv32/result:17"/>
<Sig Type="SIG" Name="u_heirv32/result:18"/>
<Sig Type="SIG" Name="u_heirv32/result:19"/>
<Sig Type="SIG" Name="u_heirv32/result:20"/>
<Sig Type="SIG" Name="u_heirv32/result:21"/>
<Sig Type="SIG" Name="u_heirv32/result:22"/>
<Sig Type="SIG" Name="u_heirv32/result:23"/>
<Sig Type="SIG" Name="u_heirv32/result:24"/>
<Sig Type="SIG" Name="u_heirv32/result:25"/>
<Sig Type="SIG" Name="u_heirv32/result:26"/>
<Sig Type="SIG" Name="u_heirv32/result:27"/>
<Sig Type="SIG" Name="u_heirv32/result:28"/>
<Sig Type="SIG" Name="u_heirv32/result:29"/>
<Sig Type="SIG" Name="u_heirv32/result:30"/>
<Sig Type="SIG" Name="u_heirv32/result:31"/>
</Bus>
<Sig Type="SIG" Name="u_heirv32/regwrite"/>
<Bus Name="u_heirv32/alusrca">
<Sig Type="SIG" Name="u_heirv32/alusrca:0"/>
<Sig Type="SIG" Name="u_heirv32/alusrca:1"/>
</Bus>
<Bus Name="u_heirv32/rd1">
<Sig Type="SIG" Name="u_heirv32/rd1:0"/>
<Sig Type="SIG" Name="u_heirv32/rd1:1"/>
<Sig Type="SIG" Name="u_heirv32/rd1:2"/>
<Sig Type="SIG" Name="u_heirv32/rd1:3"/>
<Sig Type="SIG" Name="u_heirv32/rd1:4"/>
<Sig Type="SIG" Name="u_heirv32/rd1:5"/>
<Sig Type="SIG" Name="u_heirv32/rd1:6"/>
<Sig Type="SIG" Name="u_heirv32/rd1:7"/>
<Sig Type="SIG" Name="u_heirv32/rd1:8"/>
<Sig Type="SIG" Name="u_heirv32/rd1:9"/>
<Sig Type="SIG" Name="u_heirv32/rd1:10"/>
<Sig Type="SIG" Name="u_heirv32/rd1:11"/>
<Sig Type="SIG" Name="u_heirv32/rd1:12"/>
<Sig Type="SIG" Name="u_heirv32/rd1:13"/>
<Sig Type="SIG" Name="u_heirv32/rd1:14"/>
<Sig Type="SIG" Name="u_heirv32/rd1:15"/>
<Sig Type="SIG" Name="u_heirv32/rd1:16"/>
<Sig Type="SIG" Name="u_heirv32/rd1:17"/>
<Sig Type="SIG" Name="u_heirv32/rd1:18"/>
<Sig Type="SIG" Name="u_heirv32/rd1:19"/>
<Sig Type="SIG" Name="u_heirv32/rd1:20"/>
<Sig Type="SIG" Name="u_heirv32/rd1:21"/>
<Sig Type="SIG" Name="u_heirv32/rd1:22"/>
<Sig Type="SIG" Name="u_heirv32/rd1:23"/>
<Sig Type="SIG" Name="u_heirv32/rd1:24"/>
<Sig Type="SIG" Name="u_heirv32/rd1:25"/>
<Sig Type="SIG" Name="u_heirv32/rd1:26"/>
<Sig Type="SIG" Name="u_heirv32/rd1:27"/>
<Sig Type="SIG" Name="u_heirv32/rd1:28"/>
<Sig Type="SIG" Name="u_heirv32/rd1:29"/>
<Sig Type="SIG" Name="u_heirv32/rd1:30"/>
<Sig Type="SIG" Name="u_heirv32/rd1:31"/>
</Bus>
<Bus Name="u_heirv32/srca">
<Sig Type="SIG" Name="u_heirv32/srca:0"/>
<Sig Type="SIG" Name="u_heirv32/srca:1"/>
<Sig Type="SIG" Name="u_heirv32/srca:2"/>
<Sig Type="SIG" Name="u_heirv32/srca:3"/>
<Sig Type="SIG" Name="u_heirv32/srca:4"/>
<Sig Type="SIG" Name="u_heirv32/srca:5"/>
<Sig Type="SIG" Name="u_heirv32/srca:6"/>
<Sig Type="SIG" Name="u_heirv32/srca:7"/>
<Sig Type="SIG" Name="u_heirv32/srca:8"/>
<Sig Type="SIG" Name="u_heirv32/srca:9"/>
<Sig Type="SIG" Name="u_heirv32/srca:10"/>
<Sig Type="SIG" Name="u_heirv32/srca:11"/>
<Sig Type="SIG" Name="u_heirv32/srca:12"/>
<Sig Type="SIG" Name="u_heirv32/srca:13"/>
<Sig Type="SIG" Name="u_heirv32/srca:14"/>
<Sig Type="SIG" Name="u_heirv32/srca:15"/>
<Sig Type="SIG" Name="u_heirv32/srca:16"/>
<Sig Type="SIG" Name="u_heirv32/srca:17"/>
<Sig Type="SIG" Name="u_heirv32/srca:18"/>
<Sig Type="SIG" Name="u_heirv32/srca:19"/>
<Sig Type="SIG" Name="u_heirv32/srca:20"/>
<Sig Type="SIG" Name="u_heirv32/srca:21"/>
<Sig Type="SIG" Name="u_heirv32/srca:22"/>
<Sig Type="SIG" Name="u_heirv32/srca:23"/>
<Sig Type="SIG" Name="u_heirv32/srca:24"/>
<Sig Type="SIG" Name="u_heirv32/srca:25"/>
<Sig Type="SIG" Name="u_heirv32/srca:26"/>
<Sig Type="SIG" Name="u_heirv32/srca:27"/>
<Sig Type="SIG" Name="u_heirv32/srca:28"/>
<Sig Type="SIG" Name="u_heirv32/srca:29"/>
<Sig Type="SIG" Name="u_heirv32/srca:30"/>
<Sig Type="SIG" Name="u_heirv32/srca:31"/>
</Bus>
<Bus Name="u_heirv32/alusrcb">
<Sig Type="SIG" Name="u_heirv32/alusrcb:0"/>
<Sig Type="SIG" Name="u_heirv32/alusrcb:1"/>
</Bus>
<Bus Name="u_heirv32/immsrc">
<Sig Type="SIG" Name="u_heirv32/immsrc:0"/>
<Sig Type="SIG" Name="u_heirv32/immsrc:1"/>
</Bus>
<Bus Name="u_heirv32/immext">
<Sig Type="SIG" Name="u_heirv32/immext:0"/>
<Sig Type="SIG" Name="u_heirv32/immext:1"/>
<Sig Type="SIG" Name="u_heirv32/immext:2"/>
<Sig Type="SIG" Name="u_heirv32/immext:3"/>
<Sig Type="SIG" Name="u_heirv32/immext:4"/>
<Sig Type="SIG" Name="u_heirv32/immext:5"/>
<Sig Type="SIG" Name="u_heirv32/immext:6"/>
<Sig Type="SIG" Name="u_heirv32/immext:7"/>
<Sig Type="SIG" Name="u_heirv32/immext:8"/>
<Sig Type="SIG" Name="u_heirv32/immext:9"/>
<Sig Type="SIG" Name="u_heirv32/immext:10"/>
<Sig Type="SIG" Name="u_heirv32/immext:11"/>
<Sig Type="SIG" Name="u_heirv32/immext:12"/>
<Sig Type="SIG" Name="u_heirv32/immext:13"/>
<Sig Type="SIG" Name="u_heirv32/immext:14"/>
<Sig Type="SIG" Name="u_heirv32/immext:15"/>
<Sig Type="SIG" Name="u_heirv32/immext:16"/>
<Sig Type="SIG" Name="u_heirv32/immext:17"/>
<Sig Type="SIG" Name="u_heirv32/immext:18"/>
<Sig Type="SIG" Name="u_heirv32/immext:19"/>
<Sig Type="SIG" Name="u_heirv32/immext:20"/>
<Sig Type="SIG" Name="u_heirv32/immext:21"/>
<Sig Type="SIG" Name="u_heirv32/immext:22"/>
<Sig Type="SIG" Name="u_heirv32/immext:23"/>
<Sig Type="SIG" Name="u_heirv32/immext:24"/>
<Sig Type="SIG" Name="u_heirv32/immext:25"/>
<Sig Type="SIG" Name="u_heirv32/immext:26"/>
<Sig Type="SIG" Name="u_heirv32/immext:27"/>
<Sig Type="SIG" Name="u_heirv32/immext:28"/>
<Sig Type="SIG" Name="u_heirv32/immext:29"/>
<Sig Type="SIG" Name="u_heirv32/immext:30"/>
<Sig Type="SIG" Name="u_heirv32/immext:31"/>
</Bus>
<Bus Name="u_heirv32/srcb">
<Sig Type="SIG" Name="u_heirv32/srcb:0"/>
<Sig Type="SIG" Name="u_heirv32/srcb:1"/>
<Sig Type="SIG" Name="u_heirv32/srcb:2"/>
<Sig Type="SIG" Name="u_heirv32/srcb:3"/>
<Sig Type="SIG" Name="u_heirv32/srcb:4"/>
<Sig Type="SIG" Name="u_heirv32/srcb:5"/>
<Sig Type="SIG" Name="u_heirv32/srcb:6"/>
<Sig Type="SIG" Name="u_heirv32/srcb:7"/>
<Sig Type="SIG" Name="u_heirv32/srcb:8"/>
<Sig Type="SIG" Name="u_heirv32/srcb:9"/>
<Sig Type="SIG" Name="u_heirv32/srcb:10"/>
<Sig Type="SIG" Name="u_heirv32/srcb:11"/>
<Sig Type="SIG" Name="u_heirv32/srcb:12"/>
<Sig Type="SIG" Name="u_heirv32/srcb:13"/>
<Sig Type="SIG" Name="u_heirv32/srcb:14"/>
<Sig Type="SIG" Name="u_heirv32/srcb:15"/>
<Sig Type="SIG" Name="u_heirv32/srcb:16"/>
<Sig Type="SIG" Name="u_heirv32/srcb:17"/>
<Sig Type="SIG" Name="u_heirv32/srcb:18"/>
<Sig Type="SIG" Name="u_heirv32/srcb:19"/>
<Sig Type="SIG" Name="u_heirv32/srcb:20"/>
<Sig Type="SIG" Name="u_heirv32/srcb:21"/>
<Sig Type="SIG" Name="u_heirv32/srcb:22"/>
<Sig Type="SIG" Name="u_heirv32/srcb:23"/>
<Sig Type="SIG" Name="u_heirv32/srcb:24"/>
<Sig Type="SIG" Name="u_heirv32/srcb:25"/>
<Sig Type="SIG" Name="u_heirv32/srcb:26"/>
<Sig Type="SIG" Name="u_heirv32/srcb:27"/>
<Sig Type="SIG" Name="u_heirv32/srcb:28"/>
<Sig Type="SIG" Name="u_heirv32/srcb:29"/>
<Sig Type="SIG" Name="u_heirv32/srcb:30"/>
<Sig Type="SIG" Name="u_heirv32/srcb:31"/>
</Bus>
<Bus Name="u_heirv32/alucontrol">
<Sig Type="SIG" Name="u_heirv32/alucontrol:0"/>
<Sig Type="SIG" Name="u_heirv32/alucontrol:1"/>
<Sig Type="SIG" Name="u_heirv32/alucontrol:2"/>
</Bus>
<Sig Type="SIG" Name="u_heirv32/zero"/>
<Bus Name="u_heirv32/aluresult">
<Sig Type="SIG" Name="u_heirv32/aluresult:0"/>
<Sig Type="SIG" Name="u_heirv32/aluresult:1"/>
<Sig Type="SIG" Name="u_heirv32/aluresult:2"/>
<Sig Type="SIG" Name="u_heirv32/aluresult:3"/>
<Sig Type="SIG" Name="u_heirv32/aluresult:4"/>
<Sig Type="SIG" Name="u_heirv32/aluresult:5"/>
<Sig Type="SIG" Name="u_heirv32/aluresult:6"/>
<Sig Type="SIG" Name="u_heirv32/aluresult:7"/>
<Sig Type="SIG" Name="u_heirv32/aluresult:8"/>
<Sig Type="SIG" Name="u_heirv32/aluresult:9"/>
<Sig Type="SIG" Name="u_heirv32/aluresult:10"/>
<Sig Type="SIG" Name="u_heirv32/aluresult:11"/>
<Sig Type="SIG" Name="u_heirv32/aluresult:12"/>
<Sig Type="SIG" Name="u_heirv32/aluresult:13"/>
<Sig Type="SIG" Name="u_heirv32/aluresult:14"/>
<Sig Type="SIG" Name="u_heirv32/aluresult:15"/>
<Sig Type="SIG" Name="u_heirv32/aluresult:16"/>
<Sig Type="SIG" Name="u_heirv32/aluresult:17"/>
<Sig Type="SIG" Name="u_heirv32/aluresult:18"/>
<Sig Type="SIG" Name="u_heirv32/aluresult:19"/>
<Sig Type="SIG" Name="u_heirv32/aluresult:20"/>
<Sig Type="SIG" Name="u_heirv32/aluresult:21"/>
<Sig Type="SIG" Name="u_heirv32/aluresult:22"/>
<Sig Type="SIG" Name="u_heirv32/aluresult:23"/>
<Sig Type="SIG" Name="u_heirv32/aluresult:24"/>
<Sig Type="SIG" Name="u_heirv32/aluresult:25"/>
<Sig Type="SIG" Name="u_heirv32/aluresult:26"/>
<Sig Type="SIG" Name="u_heirv32/aluresult:27"/>
<Sig Type="SIG" Name="u_heirv32/aluresult:28"/>
<Sig Type="SIG" Name="u_heirv32/aluresult:29"/>
<Sig Type="SIG" Name="u_heirv32/aluresult:30"/>
<Sig Type="SIG" Name="u_heirv32/aluresult:31"/>
</Bus>
<Bus Name="u_heirv32/aluout">
<Sig Type="SIG" Name="u_heirv32/aluout:0"/>
<Sig Type="SIG" Name="u_heirv32/aluout:1"/>
<Sig Type="SIG" Name="u_heirv32/aluout:2"/>
<Sig Type="SIG" Name="u_heirv32/aluout:3"/>
<Sig Type="SIG" Name="u_heirv32/aluout:4"/>
<Sig Type="SIG" Name="u_heirv32/aluout:5"/>
<Sig Type="SIG" Name="u_heirv32/aluout:6"/>
<Sig Type="SIG" Name="u_heirv32/aluout:7"/>
<Sig Type="SIG" Name="u_heirv32/aluout:8"/>
<Sig Type="SIG" Name="u_heirv32/aluout:9"/>
<Sig Type="SIG" Name="u_heirv32/aluout:10"/>
<Sig Type="SIG" Name="u_heirv32/aluout:11"/>
<Sig Type="SIG" Name="u_heirv32/aluout:12"/>
<Sig Type="SIG" Name="u_heirv32/aluout:13"/>
<Sig Type="SIG" Name="u_heirv32/aluout:14"/>
<Sig Type="SIG" Name="u_heirv32/aluout:15"/>
<Sig Type="SIG" Name="u_heirv32/aluout:16"/>
<Sig Type="SIG" Name="u_heirv32/aluout:17"/>
<Sig Type="SIG" Name="u_heirv32/aluout:18"/>
<Sig Type="SIG" Name="u_heirv32/aluout:19"/>
<Sig Type="SIG" Name="u_heirv32/aluout:20"/>
<Sig Type="SIG" Name="u_heirv32/aluout:21"/>
<Sig Type="SIG" Name="u_heirv32/aluout:22"/>
<Sig Type="SIG" Name="u_heirv32/aluout:23"/>
<Sig Type="SIG" Name="u_heirv32/aluout:24"/>
<Sig Type="SIG" Name="u_heirv32/aluout:25"/>
<Sig Type="SIG" Name="u_heirv32/aluout:26"/>
<Sig Type="SIG" Name="u_heirv32/aluout:27"/>
<Sig Type="SIG" Name="u_heirv32/aluout:28"/>
<Sig Type="SIG" Name="u_heirv32/aluout:29"/>
<Sig Type="SIG" Name="u_heirv32/aluout:30"/>
<Sig Type="SIG" Name="u_heirv32/aluout:31"/>
</Bus>
<Bus Name="u_heirv32/resultsrc">
<Sig Type="SIG" Name="u_heirv32/resultsrc:0"/>
<Sig Type="SIG" Name="u_heirv32/resultsrc:1"/>
</Bus>
<Sig Type="SIG" Name="u_heirv32/u_controlunit/branch"/>
<Sig Type="SIG" Name="u_heirv32/u_controlunit/pcupdate"/>
</Trace>
<Trigger>
<TU Serialbits="0" Type="0" ID="1" Sig="u_heirv32/en,"/>
<TE MaxSequence="1" MaxEvnCnt="1" ID="1" Resource="1"/>
</Trigger>
</Dataset>
</Core>
<Core InsertDataset="0" Insert="1" Reveal_sig="483219824" Name="ebs3_mc_LA1" ID="1">
<Setting>
<Clock SampleClk="clk50m" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
<TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="512"/>
<Capture Mode="0" MinSamplesPerTrig="8"/>
<Event CntEnable="0" MaxEventCnt="8"/>
<TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="0" TrigOutNet="reveal_debug_ebs3_mc_LA1_net"/>
<DistRAM Disable="0"/>
</Setting>
<Dataset Name="Base">
<Trace>
<Bus Name="leds">
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:0"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:1"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:2"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:3"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:4"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:5"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:6"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:7"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:8"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:9"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:10"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:11"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:12"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:13"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:14"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:15"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:16"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:17"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:18"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:19"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:20"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:21"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:22"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:23"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:24"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:25"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:26"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:27"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:28"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:29"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:30"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:30:31"/>
</Bus>
<Bus Name="btns">
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:0"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:1"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:2"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:3"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:4"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:5"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:6"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:7"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:8"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:9"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:10"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:11"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:12"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:13"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:14"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:15"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:16"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:17"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:18"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:19"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:20"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:21"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:22"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:23"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:24"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:25"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:26"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:27"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:28"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:29"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:30"/>
<Sig Type="SIG" Name="u_heirv32/u_registerfile/larr_registers:31:31"/>
</Bus>
</Trace>
<Trigger>
<TU Serialbits="0" Type="0" ID="1" Sig="u_heirv32/en,"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="1" Resource="1"/>
</Trigger>
</Dataset>
</Core>
</Project>

203
10-PipelinedOperators/Board/diamond/strategy.sty Normal file
View File

@ -0,0 +1,203 @@
<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE strategy>
<Strategy version="1.0" predefined="0" description="" label="Strategy">
<Property name="PROP_BD_CmdLineArgs" value="" time="0"/>
<Property name="PROP_BD_EdfHardtimer" value="Enable" time="0"/>
<Property name="PROP_BD_EdfInBusNameConv" value="None" time="0"/>
<Property name="PROP_BD_EdfInLibPath" value="" time="0"/>
<Property name="PROP_BD_EdfInRemLoc" value="Off" time="0"/>
<Property name="PROP_BD_EdfMemPath" value="" time="0"/>
<Property name="PROP_BD_ParSearchPath" value="" time="0"/>
<Property name="PROP_BIT_AddressBitGen" value="Increment" time="0"/>
<Property name="PROP_BIT_AllowReadBitGen" value="Disable" time="0"/>
<Property name="PROP_BIT_ByteWideBitMirror" value="Disable" time="0"/>
<Property name="PROP_BIT_CapReadBitGen" value="Disable" time="0"/>
<Property name="PROP_BIT_ConModBitGen" value="Disable" time="0"/>
<Property name="PROP_BIT_CreateBitFile" value="True" time="0"/>
<Property name="PROP_BIT_DisRAMResBitGen" value="True" time="0"/>
<Property name="PROP_BIT_DisableUESBitgen" value="False" time="0"/>
<Property name="PROP_BIT_DonePinBitGen" value="Pullup" time="0"/>
<Property name="PROP_BIT_DoneSigBitGen" value="4" time="0"/>
<Property name="PROP_BIT_EnIOBitGen" value="TriStateDuringReConfig" time="0"/>
<Property name="PROP_BIT_EnIntOscBitGen" value="Disable" time="0"/>
<Property name="PROP_BIT_ExtClockBitGen" value="False" time="0"/>
<Property name="PROP_BIT_GSREnableBitGen" value="True" time="0"/>
<Property name="PROP_BIT_GSRRelOnBitGen" value="DoneIn" time="0"/>
<Property name="PROP_BIT_GranTimBitGen" value="0" time="0"/>
<Property name="PROP_BIT_IOTriRelBitGen" value="Cycle 2" time="0"/>
<Property name="PROP_BIT_JTAGEnableBitGen" value="False" time="0"/>
<Property name="PROP_BIT_LenBitsBitGen" value="24" time="0"/>
<Property name="PROP_BIT_MIFFileBitGen" value="" time="0"/>
<Property name="PROP_BIT_NoHeader" value="False" time="0"/>
<Property name="PROP_BIT_OutFormatBitGen" value="Bit File (Binary)" time="0"/>
<Property name="PROP_BIT_OutFormatBitGen_REF" value="" time="0"/>
<Property name="PROP_BIT_OutFormatPromGen" value="Intel Hex 32-bit" time="0"/>
<Property name="PROP_BIT_ParityCheckBitGen" value="True" time="0"/>
<Property name="PROP_BIT_RemZeroFramesBitGen" value="False" time="0"/>
<Property name="PROP_BIT_RunDRCBitGen" value="True" time="0"/>
<Property name="PROP_BIT_SearchPthBitGen" value="" time="0"/>
<Property name="PROP_BIT_StartUpClkBitGen" value="Cclk" time="0"/>
<Property name="PROP_BIT_SynchIOBitGen" value="True" time="0"/>
<Property name="PROP_BIT_SysClockConBitGen" value="Reset" time="0"/>
<Property name="PROP_BIT_SysConBitGen" value="Reset" time="0"/>
<Property name="PROP_BIT_WaitStTimBitGen" value="5" time="0"/>
<Property name="PROP_IOTIMING_AllSpeed" value="False" time="0"/>
<Property name="PROP_LST_AllowDUPMod" value="False" time="0"/>
<Property name="PROP_LST_CarryChain" value="True" time="0"/>
<Property name="PROP_LST_CarryChainLength" value="0" time="0"/>
<Property name="PROP_LST_CmdLineArgs" value="" time="0"/>
<Property name="PROP_LST_DSPStyle" value="DSP" time="0"/>
<Property name="PROP_LST_DSPUtil" value="100" time="0"/>
<Property name="PROP_LST_DecodeUnreachableStates" value="False" time="0"/>
<Property name="PROP_LST_DisableDistRam" value="False" time="0"/>
<Property name="PROP_LST_EBRUtil" value="100" time="0"/>
<Property name="PROP_LST_EdfFrequency" value="200" time="0"/>
<Property name="PROP_LST_EdfHardtimer" value="Enable" time="0"/>
<Property name="PROP_LST_EdfInLibPath" value="" time="0"/>
<Property name="PROP_LST_EdfInRemLoc" value="Off" time="0"/>
<Property name="PROP_LST_EdfMemPath" value="" time="0"/>
<Property name="PROP_LST_FIXGATEDCLKS" value="True" time="0"/>
<Property name="PROP_LST_FSMEncodeStyle" value="Auto" time="0"/>
<Property name="PROP_LST_ForceGSRInfer" value="Auto" time="0"/>
<Property name="PROP_LST_IOInsertion" value="True" time="0"/>
<Property name="PROP_LST_InterFileDump" value="False" time="0"/>
<Property name="PROP_LST_LoopLimit" value="1950" time="0"/>
<Property name="PROP_LST_MaxFanout" value="1000" time="0"/>
<Property name="PROP_LST_MuxStyle" value="Auto" time="0"/>
<Property name="PROP_LST_NumCriticalPaths" value="3" time="0"/>
<Property name="PROP_LST_OptimizeGoal" value="Timing" time="0"/>
<Property name="PROP_LST_PropagatConst" value="True" time="0"/>
<Property name="PROP_LST_RAMStyle" value="Auto" time="0"/>
<Property name="PROP_LST_ROMStyle" value="Auto" time="0"/>
<Property name="PROP_LST_RemoveDupRegs" value="True" time="0"/>
<Property name="PROP_LST_ResolvedMixedDrivers" value="False" time="0"/>
<Property name="PROP_LST_ResourceShare" value="True" time="0"/>
<Property name="PROP_LST_UseIOReg" value="Auto" time="0"/>
<Property name="PROP_LST_UseLPF" value="True" time="0"/>
<Property name="PROP_LST_VHDL2008" value="False" time="0"/>
<Property name="PROP_MAPSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
<Property name="PROP_MAPSTA_AutoTiming" value="True" time="0"/>
<Property name="PROP_MAPSTA_CheckUnconstrainedConns" value="False" time="0"/>
<Property name="PROP_MAPSTA_CheckUnconstrainedPaths" value="False" time="0"/>
<Property name="PROP_MAPSTA_FullName" value="False" time="0"/>
<Property name="PROP_MAPSTA_NumUnconstrainedPaths" value="0" time="0"/>
<Property name="PROP_MAPSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
<Property name="PROP_MAPSTA_RouteEstAlogtithm" value="0" time="0"/>
<Property name="PROP_MAPSTA_RptAsynTimLoop" value="False" time="0"/>
<Property name="PROP_MAPSTA_WordCasePaths" value="1" time="0"/>
<Property name="PROP_MAP_IgnorePreErr" value="True" time="0"/>
<Property name="PROP_MAP_MAPIORegister" value="Auto" time="0"/>
<Property name="PROP_MAP_MAPInferGSR" value="True" time="0"/>
<Property name="PROP_MAP_MapModArgs" value="" time="0"/>
<Property name="PROP_MAP_OvermapDevice" value="False" time="0"/>
<Property name="PROP_MAP_PackLogMapDes" value="" time="0"/>
<Property name="PROP_MAP_RegRetiming" value="False" time="0"/>
<Property name="PROP_MAP_SigCrossRef" value="False" time="0"/>
<Property name="PROP_MAP_SymCrossRef" value="False" time="0"/>
<Property name="PROP_MAP_TimingDriven" value="False" time="0"/>
<Property name="PROP_MAP_TimingDrivenNodeRep" value="False" time="0"/>
<Property name="PROP_MAP_TimingDrivenPack" value="False" time="0"/>
<Property name="PROP_PARSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
<Property name="PROP_PARSTA_AutoTiming" value="True" time="0"/>
<Property name="PROP_PARSTA_CheckUnconstrainedConns" value="False" time="0"/>
<Property name="PROP_PARSTA_CheckUnconstrainedPaths" value="False" time="0"/>
<Property name="PROP_PARSTA_FullName" value="False" time="0"/>
<Property name="PROP_PARSTA_NumUnconstrainedPaths" value="0" time="0"/>
<Property name="PROP_PARSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
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14
10-PipelinedOperators/Board/hdl/DFF_sim.vhd Normal file
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ARCHITECTURE sim OF DFF IS
BEGIN
process(clk, clr)
begin
if clr = '1' then
q <= '0';
elsif rising_edge(clk) then
q <= d;
end if;
end process;
END ARCHITECTURE sim;

7
10-PipelinedOperators/Board/hdl/buff_sim.vhd Normal file
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ARCHITECTURE sim OF buff IS
BEGIN
out1 <= in1;
END ARCHITECTURE sim;

7
10-PipelinedOperators/Board/hdl/inverterIn_sim.vhd Normal file
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ARCHITECTURE sim OF inverterIn IS
BEGIN
out1 <= NOT in1;
END ARCHITECTURE sim;

7
10-PipelinedOperators/Board/hdl/inverter_sim.vhd Normal file
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ARCHITECTURE sim OF inverter IS
BEGIN
out1 <= NOT in1;
END ARCHITECTURE sim;

1
10-PipelinedOperators/Board/hds/.hdlsidedata/_DFF_sim.vhd._fpf Normal file
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DIALECT atom VHDL_2008

1
10-PipelinedOperators/Board/hds/.hdlsidedata/_buff_sim.vhd._fpf Normal file
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@ -0,0 +1 @@
DIALECT atom VHDL_2008

1
10-PipelinedOperators/Board/hds/.hdlsidedata/_dff_entity.vhg._fpf Executable file
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DIALECT atom VHDL_2008

1
10-PipelinedOperators/Board/hds/.hdlsidedata/_inverterIn_sim.vhd._fpf Normal file
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@ -0,0 +1 @@
DIALECT atom VHDL_2008

1
10-PipelinedOperators/Board/hds/.hdlsidedata/_inverter_sim.vhd._fpf Normal file
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@ -0,0 +1 @@
DIALECT atom VHDL_2008

1
10-PipelinedOperators/Board/hds/.hdlsidedata/_inverterin_entity.vhg._fpf Executable file
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@ -0,0 +1 @@
DIALECT atom VHDL_2008

1
10-PipelinedOperators/Board/hds/.hdlsidedata/_pipelinecounter_circuit_entity.vhg._fpf Executable file
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DIALECT atom VHDL_2008

1
10-PipelinedOperators/Board/hds/.hdlsidedata/_pipelinecounter_circuit_struct.vhg._fpf Executable file
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@ -0,0 +1 @@
DIALECT atom VHDL_2008

1
10-PipelinedOperators/Board/hds/.hdlsidedata/_pipelinecounter_ebs2_entity.vhg._fpf Normal file
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@ -0,0 +1 @@
DIALECT atom VHDL_2008

1
10-PipelinedOperators/Board/hds/.hdlsidedata/_pipelinecounter_ebs2_struct.vhg._fpf Normal file
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@ -0,0 +1 @@
DIALECT atom VHDL_2008

1
10-PipelinedOperators/Board/hds/.hdlsidedata/_pipelinecounter_ebs3_entity.vhg._fpf Normal file
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@ -0,0 +1 @@
DIALECT atom VHDL_2008

1
10-PipelinedOperators/Board/hds/.hdlsidedata/_pipelinecounter_ebs3_struct.vhg._fpf Normal file
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@ -0,0 +1 @@
DIALECT atom VHDL_2008

1211
10-PipelinedOperators/Board/hds/@d@f@f/symbol.sb Normal file
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1571
10-PipelinedOperators/Board/hds/@f@p@g@a_sine@gen_tester/interface Normal file
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2
10-PipelinedOperators/Board/hds/_buff._epf Normal file
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DEFAULT_FILE atom buff_sim.vhd
DEFAULT_ARCHITECTURE atom sim

3
10-PipelinedOperators/Board/hds/_pipelinecounter_circuit._epf Normal file
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DEFAULT_FILE atom pipeline@counter_circuit/struct.bd
DEFAULT_ARCHITECTURE atom struct
TOP_MARKER atom 1

3
10-PipelinedOperators/Board/hds/_pipelinecounter_ebs2._epf Normal file
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@ -0,0 +1,3 @@
DEFAULT_FILE atom pipeline@counter_ebs2/struct.bd
DEFAULT_ARCHITECTURE atom struct
TOP_MARKER atom 1

3
10-PipelinedOperators/Board/hds/_pipelinecounter_ebs3._epf Normal file
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@ -0,0 +1,3 @@
DEFAULT_ARCHITECTURE atom struct
DEFAULT_FILE atom pipeline@counter_ebs3/struct.bd
TOP_MARKER atom 1

1107
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10-PipelinedOperators/Board/hds/inverter/symbol.sb Normal file
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10-PipelinedOperators/Board/hds/inverter@in/symbol.sb Normal file
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3650
10-PipelinedOperators/Board/hds/pipeline@counter_circuit/struct.bd Normal file
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1532
10-PipelinedOperators/Board/hds/pipeline@counter_circuit/symbol.sb Normal file
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3649
10-PipelinedOperators/Board/hds/pipeline@counter_ebs2/struct.bd Normal file
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1531
10-PipelinedOperators/Board/hds/pipeline@counter_ebs2/symbol.sb Normal file
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4418
10-PipelinedOperators/Board/hds/pipeline@counter_ebs3/struct.bd Normal file
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10-PipelinedOperators/Board/hds/pipeline@counter_ebs3/symbol.sb Normal file
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10-PipelinedOperators/Board/ise/pipelinedOperators.xise Normal file
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@ -0,0 +1,328 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="motherboard_FPGA" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
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<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
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<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
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<property xil_pn:name="PROP_DesignName" xil_pn:value="boardTester" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
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<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
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<bindings/>
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<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>

7
10-PipelinedOperators/PipelinedOperators/hdl/parallelAdder_studentVersion.vhd Normal file
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ARCHITECTURE studentVersion OF parallelAdder IS
BEGIN
sum <= (others => '0');
cOut <= '0';
END ARCHITECTURE studentVersion;

45
10-PipelinedOperators/PipelinedOperators/hdl/pipelineAdder_noPipe.vhd Normal file
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ARCHITECTURE noPipe OF pipelineAdder IS
constant stageBitNb : positive := sum'length/stageNb;
subtype stageOperandType is signed(stageBitNb-1 downto 0);
type stageOperandArrayType is array(stageNb-1 downto 0) of stageOperandType;
subtype carryType is std_ulogic_vector(stageNb downto 0);
signal a_int, b_int, sum_int : stageOperandArrayType;
signal carryIn : carryType;
COMPONENT parallelAdder
GENERIC (
bitNb : positive := 32
);
PORT (
sum : OUT signed (bitNb-1 DOWNTO 0);
cIn : IN std_ulogic ;
cOut : OUT std_ulogic ;
a : IN signed (bitNb-1 DOWNTO 0);
b : IN signed (bitNb-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
carryIn(0) <= cIn;
pipeline: for index in stageOperandArrayType'range generate
a_int(index) <= a(index*stageBitNb+stageBitNb-1 downto index*stageBitNb);
b_int(index) <= b(index*stageBitNb+stageBitNb-1 downto index*stageBitNb);
partialAdder: parallelAdder
GENERIC MAP (bitNb => stageBitNb)
PORT MAP (
a => a_int(index),
b => b_int(index),
sum => sum_int(index),
cIn => carryIn(index),
cOut => carryIn(index+1)
);
sum(index*stageBitNb+stageBitNb-1 downto index*stageBitNb) <= sum_int(index);
end generate pipeline;
cOut <= carryIn(carryIn'high);
END ARCHITECTURE noPipe;

7
10-PipelinedOperators/PipelinedOperators/hdl/pipelineAdder_studentVersion.vhd Normal file
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ARCHITECTURE studentVersion OF pipelineAdder IS
BEGIN
sum <= (others => '0');
cOut <= '0';
END ARCHITECTURE studentVersion;

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10-PipelinedOperators/PipelinedOperators/hdl/pipelineCounter_studentVersion.vhd Normal file
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ARCHITECTURE studentVersion OF pipelineCounter IS
signal b : signed(countOut'range);
signal sum : signed(countOut'range);
COMPONENT pipelineAdder
GENERIC (
bitNb : positive := 32;
stageNb : positive := 4
);
PORT (
reset : IN std_ulogic;
clock : IN std_ulogic;
cIn : IN std_ulogic;
a : IN signed (bitNb-1 DOWNTO 0);
b : IN signed (bitNb-1 DOWNTO 0);
sum : OUT signed (bitNb-1 DOWNTO 0);
cOut : OUT std_ulogic
);
END COMPONENT;
BEGIN
b <= to_signed(1, b'length);
adder: pipelineAdder
GENERIC MAP (
bitNb => countOut'length,
stageNb => stageNb
)
PORT MAP (
reset => reset,
clock => clock,
cIn => '0',
a => sum,
b => b,
sum => sum,
cOut => open
);
countOut <= unsigned(sum);
END ARCHITECTURE studentVersion;

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10-PipelinedOperators/PipelinedOperators/hds/.hdlsidedata/_parallelAdder_studentVersion.vhd._fpf Normal file
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DIALECT atom VHDL_2008

1
10-PipelinedOperators/PipelinedOperators/hds/.hdlsidedata/_paralleladder_entity.vhg._fpf Normal file
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1
10-PipelinedOperators/PipelinedOperators/hds/.hdlsidedata/_pipelineAdder_noPipe.vhd._fpf Normal file
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1
10-PipelinedOperators/PipelinedOperators/hds/.hdlsidedata/_pipelineAdder_studentVersion.vhd._fpf Normal file
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DIALECT atom VHDL_2008

1
10-PipelinedOperators/PipelinedOperators/hds/.hdlsidedata/_pipelineCounter_studentVersion.vhd._fpf Normal file
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1
10-PipelinedOperators/PipelinedOperators/hds/.hdlsidedata/_pipelineadder_entity.vhg._fpf Normal file
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1
10-PipelinedOperators/PipelinedOperators/hds/.hdlsidedata/_pipelinecounter_entity.vhg._fpf Normal file
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10-PipelinedOperators/PipelinedOperators/hds/_paralleladder._epf Normal file
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DEFAULT_FILE atom parallelAdder_studentVersion.vhd
DEFAULT_ARCHITECTURE atom studentVersion

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DEFAULT_FILE atom pipelineAdder_studentVersion.vhd
DEFAULT_ARCHITECTURE atom studentVersion
TOP_MARKER atom 1

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DEFAULT_FILE atom pipelineCounter_studentVersion.vhd
DEFAULT_ARCHITECTURE atom studentVersion
TOP_MARKER atom 1

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ARCHITECTURE test OF parallelAdder_tester IS
constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
signal sClock: std_uLogic := '1';
signal sReset: std_uLogic := '1';
constant aMax: signed(a'range) := (a'high => '0', others => '1');
constant aIncr: signed(a'range) := shift_right(aMax, 4)+1;
constant bIncr: signed(b'range) := shift_right(aMax, 4)+1;
signal a_int, b_int, sum_int: signed(a'range);
BEGIN
------------------------------------------------------------------------------
-- clock and reset
sClock <= not sClock after clockPeriod/2;
sReset <= '1', '0' after 2*clockPeriod;
------------------------------------------------------------------------------
-- test sequence
process
begin
a_int <= (a_int'high => '1', others => '0');
b_int <= (b_int'high => '1', others => '0');
wait until sReset = '0';
-- data values
while a_int < aMax-aIncr loop
a_int <= a_int + aIncr;
b_int <= b_int + bIncr;
wait until rising_edge(sClock);
assert sum = a_int + b_int
report "sum is wrong !"
severity error;
end loop;
-- stop simulation
assert false
report cr & cr &
"End of Simulation" &
cr
severity failure;
wait;
end process;
cIn <= '0';
a <= a_int;
b <= b_int;
sum_int <= a_int + b_int;
END ARCHITECTURE test;

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ARCHITECTURE test OF pipelineAdder_tester IS
constant clockFrequency: real := 66.0E6;
constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
signal sClock: std_uLogic := '1';
signal sReset: std_uLogic := '1';
constant pipeDelay: positive := 4;
constant aMax: signed(a'range) := (a'high => '0', others => '1');
constant aIncr: signed(a'range) := shift_right(aMax, 3)+1 + 32;
constant bIncr: signed(b'range) := shift_right(aMax, 3)+1 + 32;
signal a_int, b_int, sumNoPipe: signed(a'range);
type sumArrayType is array(1 to stageNb-1) of signed(sumNoPipe'range);
signal sumArray : sumArrayType := (others => (others => '0'));
BEGIN
------------------------------------------------------------------------------
-- clock and reset
sClock <= not sClock after clockPeriod/2;
clock <= transport sClock after clockPeriod*9/10;
sReset <= '1', '0' after 2*clockPeriod;
reset <= sReset;
------------------------------------------------------------------------------
-- test sequence
process
begin
a_int <= (a_int'high => '1', others => '0');
b_int <= (b_int'high => '1', others => '0');
wait until sReset = '0';
-- data values
while a_int < aMax-aIncr loop
a_int <= a_int + aIncr;
b_int <= b_int + bIncr;
wait until rising_edge(sClock);
end loop;
-- stop simulation
for index in 1 to pipeDelay loop
wait until rising_edge(sClock);
end loop;
assert false
report cr & cr &
"End of Simulation" &
cr
severity failure;
wait;
end process;
cIn <= '0';
a <= a_int;
b <= b_int;
sumNoPipe <= a_int + b_int;
------------------------------------------------------------------------------
-- delay sum
process(sClock)
begin
if rising_edge(sClock) then
sumArray(1) <= sumNoPipe;
sumArray(2 to sumArray'length) <= sumArray(1 to sumArray'length-1);
assert sum = sumArray(sumArray'length-1)
report "sum is wrong !"
severity error;
end if;
end process;
END ARCHITECTURE test;

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--
-- VHDL Architecture PipelinedOperators_test.PipelineCounter_tester.test
--
-- Created:
-- by - zas.UNKNOWN (ZELL)
-- at - 16:00:38 02/20/2020
--
-- using Mentor Graphics HDL Designer(TM) 2019.2 (Build 5)
--
ARCHITECTURE test OF PipelineCounter_tester IS
constant clockFrequency: real := 66.0E6;
constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
signal sClock: std_uLogic := '1';
BEGIN
------------------------------------------------------------------------------
-- clock and reset
sClock <= not sClock after clockPeriod/2;
clock <= transport sClock after clockPeriod*9/10;
reset <= '1', '0' after 2*clockPeriod;
END ARCHITECTURE test;

1
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1
10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_paralleladder_tb_entity.vhg._fpf Normal file
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DIALECT atom VHDL_2008

1
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DIALECT atom VHDL_2008

1
10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_paralleladder_tester_entity.vhg._fpf Normal file
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@ -0,0 +1 @@
DIALECT atom VHDL_ANY

1
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@ -0,0 +1 @@
DIALECT atom VHDL_2008

4
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@ -0,0 +1,4 @@
DIALECT atom VHDL_2008
INCLUDE list {
DEFAULT atom 1
}

1
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1
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1
10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_pipelineadder_tester_entity.vhg._fpf Normal file
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@ -0,0 +1 @@
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1
10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_pipelinecounter_tb_entity.vhg._fpf Normal file
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DIALECT atom VHDL_2008

1
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@ -0,0 +1 @@
DIALECT atom VHDL_2008

1
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2
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DEFAULT_FILE atom parallelAdder_tester_test.vhd

3
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2
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28
10-PipelinedOperators/Prefs/hds.hdp Normal file
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[Concat]
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23
10-PipelinedOperators/Prefs/hds_team/shared.hdp Normal file
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@ -0,0 +1,23 @@
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55
10-PipelinedOperators/Prefs/hds_team/v2018.1/hds_team_prefs Normal file
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55
10-PipelinedOperators/Prefs/hds_team/v2019.2/hds_team_prefs Normal file
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bg "0,0,32768"
font "Arial,8,0"
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xt "14200,68000,15900,69000"
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wrapOption 3
visibleHeight 1000
visibleWidth 4000
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position 1
ignorePrefs 1
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font "Arial,8,0"
)
xt "35200,67200,44000,68200"
st "
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tm "CommentText"
wrapOption 3
visibleHeight 4000
visibleWidth 20000
)
ignorePrefs 1
)
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shape (Rectangle
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
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text (MLText
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
font "Arial,8,0"
)
xt "39200,66000,48900,67000"
st "%project_name"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 16000
)
position 1
ignorePrefs 1
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va (VaSet
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tm "CommentText"
wrapOption 3
visibleHeight 2000
visibleWidth 21000
)
position 1
ignorePrefs 1
)
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font "Arial,8,0"
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xt "14200,69000,15900,70000"
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tm "CommentText"
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tm "CommentText"
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ignorePrefs 1
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55
10-PipelinedOperators/Prefs/hds_team/v2019.3/hds_team_prefs Normal file
View File

@ -0,0 +1,55 @@
version "8.0"
RenoirTeamPreferences [
(BaseTeamPreferences
version "1.1"
verConcat 0
ttDGProps [
]
fcDGProps [
]
smDGProps [
]
asmDGProps [
]
bdDGProps [
]
syDGProps [
]
)
(VersionControlTeamPreferences
version "1.1"
VMPlugin ""
VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository"
VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm"
VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm"
VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm"
VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository"
VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm"
VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm"
VMDsHdsRepository "sync://<host_name>:<port>/hds_scratch/hds_repository/hds_vm"
VMDsHdlRepository "sync://<host_name>:<port>/hds_scratch/hds_repository/hdl_vm"
VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm"
VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm"
VMSvnHdlRepository ""
VMDefaultView 1
VMCurrentDesignHierarchyOnly 0
VMUserData 1
VMGeneratedHDL 0
VMVerboseMode 0
VMAlwaysEmpty 0
VMSetTZ 1
VMSymbol 1
VMCurrentDesignHierarchy 0
VMMultipleRepositoryMode 0
VMSnapshotViewMode 0
backupNameClashes 1
clearCaseMaster 0
)
(CustomizeTeamPreferences
version "1.1"
FileTypes [
]
)
]

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