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334
10-PipelinedOperators/Board/concat/pipelinedOperators.lpf
Normal file
334
10-PipelinedOperators/Board/concat/pipelinedOperators.lpf
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@ -0,0 +1,334 @@
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### For reference, see TN1262 / FPGA-TN-02032
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# .lpf file format is not really documented by Lattice, normally generated through Diamond
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################
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#### sysCONFIG
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################
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# The BLOCK commands disable tracing of paths within clock domains (impacting overall timing score)
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# It can also be used on paths if the TRACE should not consider the clock domain crossing
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# like : BLOCK PATH FROM CLKNET "CLK_A" TO CLKNET "CLK_B" ;
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BLOCK RESETPATHS ;
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BLOCK ASYNCPATHS ;
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BLOCK JTAGPATHS ;
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BLOCK RD_DURING_WR_PATHS ;
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# Not comprehensive
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# dflt : CONFIG_IOVOLTAGE 1.2, 1.5, 1.8, 2.5(dflt), 3.3 voltage is 3.3V
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# dflt : COMPRESS_CONFIG OFF (dflt), ON no bitstream compression
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# mod : MCCLK_FREQ 2.4, 4.8, 9.7, 19.4, 38.8, 62 NOR program read @ 62MHz
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# mod : MASTER_SPI_PORT DISABLE (dflt), ENABLE master SPI port stays SPI and not GPIOs, other mods disabled by dflt
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# dflt : BACKGROUND_RECONFIG - no soft ERC when hot-loading bitstream (due to cosmic rays)
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# dflt : DONE_PULL ON (dflt), OFF IPU on DONE pin
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# dflt : DONE_EX OFF (dflt), ON not delaying end of the configuration (used for daisy chaining FPGAs)
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# mod : DONE_OD OFF (dflt), ON DONE pin as open-drain instead of push-pull
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# dflt : CONFIG_SECURE OFF (dflt), ON allows external access to current program
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# mod : CONFIG_MODE JTAG (dflt), SSPI, SPI_SERIAL, SPI_DUAL, SPI_QUAD, SLAVE_PARALLEL, SLAVE_SERIAL
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# which bus and mode is used to load configuration (for the Lattic IDE)
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# dflt : TRANSFR OFF (dflt), ON if using TransFR tool from Lattice
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# dflt : WAKE_UP 4 (set DONE=1 before starting user code, dflt for DONE_EX=ON)
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# 21 (set DONE=1 once FPGA is already running user code, dflt for DONE_EX=OFF)
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# mod : INBUF ON, OFF disable unused input buffers (not sure it impacts the ECP5 family)
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SYSCONFIG MCCLK_FREQ=62 MASTER_SPI_PORT=ENABLE DONE_OD=ON CONFIG_MODE=SPI_QUAD INBUF=OFF CONFIG_IOVOLTAGE=3.3 ;
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IOBUF ALLPORTS IO_TYPE=LVCMOS33 ;
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################
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#### Labs DB
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################
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### Clock and reset ###
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#INPUT_SETUP ALLPORTS 50.000000 ns HOLD 10.000000 ns CLKPORT "CLK" ;
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#INPUT_SETUP PORT "nRST" 50.000000 ns CLKPORT "CLK" ;
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FREQUENCY PORT "clock" 100.000000 MHz ;
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LOCATE COMP "clock" SITE "K16" ;
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IOBUF PORT "clock" PULLMODE=NONE ;
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LOCATE COMP "reset_n" SITE "E13" ;
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GSR_NET NET "resetSynch_n";
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### LEDs ###
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LOCATE COMP "LED1" SITE "T14" ;# red
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LOCATE COMP "LED2" SITE "R14" ;# green
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LOCATE COMP "LED3" SITE "T15" ;# blue
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################
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#### SODIMM-200
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################
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### PP2 ###
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LOCATE COMP "xOut" SITE "G3" ;
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LOCATE COMP "yOut" SITE "E1" ;
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#LOCATE COMP "" SITE "F3" ;
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#LOCATE COMP "" SITE "D1" ;
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LOCATE COMP "triggerOut" SITE "F4" ;
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#LOCATE COMP "" SITE "C1" ;
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#LOCATE COMP "" SITE "D7" ;
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#LOCATE COMP "" SITE "B6" ;
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#LOCATE COMP "" SITE "C7" ;
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#LOCATE COMP "" SITE "A6" ; # PP2 11
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#LOCATE COMP "" SITE "D8" ; # PP2 13
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#LOCATE COMP "" SITE "B7" ; # PP2 15
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#LOCATE COMP "" SITE "C8" ; # PP2 17
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#LOCATE COMP "" SITE "A7" ; # PP2 19
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#LOCATE COMP "" SITE "E9" ; # PP2 21
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#LOCATE COMP "" SITE "A8" ; # PP2 23
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#LOCATE COMP "" SITE "D9" ; # PP2 25
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### PP1 ###
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#LOCATE COMP "" SITE "A9" ;
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#LOCATE COMP "" SITE "D10" ;
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#LOCATE COMP "" SITE "A10" ;
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#LOCATE COMP "" SITE "C10" ;
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#LOCATE COMP "" SITE "B10" ;
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#LOCATE COMP "" SITE "C12" ;
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#LOCATE COMP "" SITE "B12" ;
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#LOCATE COMP "" SITE "D13" ;
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#LOCATE COMP "" SITE "A13" ;
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#LOCATE COMP "" SITE "M5" ; # PP1 11
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#LOCATE COMP "" SITE "L5" ; # PP1 13
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#LOCATE COMP "" SITE "K5" ; # PP1 15
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#LOCATE COMP "" SITE "H5" ; # PP1 17
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#LOCATE COMP "" SITE "E8" ; # PP1 19
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#LOCATE COMP "" SITE "E5" ; # PP1 21
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LOCATE COMP "selSinCos_n" SITE "E6" ; # PP1 23
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#LOCATE COMP "" SITE "E7" ; # PP1 25
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### USB (FTDI2232HL located on the daughterboard) ###
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LOCATE COMP "TxD" SITE "A14" ;
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IOBUF PORT "TxD" SLEWRATE=FAST ;
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LOCATE COMP "RxD" SITE "B14" ;
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IOBUF PORT "RxD" PULLMODE=UP ;
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#LOCATE COMP "USB_DB_RTS" SITE "B13" ;
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#IOBUF PORT "USB_DB_RTS" SLEWRATE=FAST ;
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#LOCATE COMP "USB_DB_CTS" SITE "C13" ;
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#IOBUF PORT "USB_DB_CTS" PULLMODE=UP ;
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################
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#### Extras
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################
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### SD Flash (External SD card) ###
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#LOCATE COMP "SD_DETECT" SITE "G12" ;
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#IOBUF PORT "SD_DETECT" PULLMODE=UP ;
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#LOCATE COMP "SD_CMD" SITE "C15" ;
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#IOBUF PORT "SD_CMD" SLEWRATE=FAST ;
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#LOCATE COMP "SD_CLK" SITE "B15" ;
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#IOBUF PORT "SD_CLK" SLEWRATE=FAST ;
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#LOCATE COMP "SD_DTA[0]" SITE "B16" ;
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##IOBUF PORT "SD_DTA[0]" SLEWRATE=FAST ;
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#LOCATE COMP "SD_DTA[1]" SITE "C16" ;
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##IOBUF PORT "SD_DTA[1]" SLEWRATE=FAST ;
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#LOCATE COMP "SD_DTA[2]" SITE "F12" ;
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##IOBUF PORT "SD_DTA[2]" SLEWRATE=FAST ;
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#LOCATE COMP "SD_DTA[3]" SITE "C14" ;
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##IOBUF PORT "SD_DTA[3]" SLEWRATE=FAST ;
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### DRAM ###
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#LOCATE COMP "DRAM_ADDR[0]" SITE "J15" ;
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#IOBUF PORT "DRAM_ADDR[0]" SLEWRATE=FAST ;
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#LOCATE COMP "DRAM_ADDR[1]" SITE "L16" ;
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#IOBUF PORT "DRAM_ADDR[1]" SLEWRATE=FAST ;
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#LOCATE COMP "DRAM_ADDR[2]" SITE "L15" ;
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#IOBUF PORT "DRAM_ADDR[2]" SLEWRATE=FAST ;
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#LOCATE COMP "DRAM_ADDR[3]" SITE "K15" ;
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#IOBUF PORT "DRAM_ADDR[3]" SLEWRATE=FAST ;
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#LOCATE COMP "DRAM_ADDR[4]" SITE "G15" ;
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#IOBUF PORT "DRAM_ADDR[4]" SLEWRATE=FAST ;
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#LOCATE COMP "DRAM_ADDR[5]" SITE "F15" ;
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#IOBUF PORT "DRAM_ADDR[5]" SLEWRATE=FAST ;
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#LOCATE COMP "DRAM_ADDR[6]" SITE "F16" ;
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#IOBUF PORT "DRAM_ADDR[6]" SLEWRATE=FAST ;
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#LOCATE COMP "DRAM_ADDR[7]" SITE "E16" ;
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#IOBUF PORT "DRAM_ADDR[7]" SLEWRATE=FAST ;
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#LOCATE COMP "DRAM_ADDR[8]" SITE "E15" ;
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#IOBUF PORT "DRAM_ADDR[8]" SLEWRATE=FAST ;
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#LOCATE COMP "DRAM_ADDR[9]" SITE "G13" ;
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#IOBUF PORT "DRAM_ADDR[9]" SLEWRATE=FAST ;
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#LOCATE COMP "DRAM_ADDR[10]" SITE "M16" ;
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#IOBUF PORT "DRAM_ADDR[10]" SLEWRATE=FAST ;
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#LOCATE COMP "DRAM_ADDR[11]" SITE "F13" ;
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#IOBUF PORT "DRAM_ADDR[11]" SLEWRATE=FAST ;
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#LOCATE COMP "DRAM_ADDR[12]" SITE "D16" ;
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#IOBUF PORT "DRAM_ADDR[12]" SLEWRATE=FAST ;
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#LOCATE COMP "DRAM_BA[0]" SITE "L14" ;
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#IOBUF PORT "DRAM_BA[0]" SLEWRATE=FAST ;
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#LOCATE COMP "DRAM_BA[1]" SITE "L13" ;
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#IOBUF PORT "DRAM_BA[1]" SLEWRATE=FAST ;
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#LOCATE COMP "DRAM_CLK" SITE "G14" ;
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#IOBUF PORT "DRAM_CLK" SLEWRATE=FAST ;
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#LOCATE COMP "DRAM_CKE" SITE "G16" ;
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#IOBUF PORT "DRAM_CKE" SLEWRATE=FAST ;
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#LOCATE COMP "DRAM_nRAS" SITE "M14" ;
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#IOBUF PORT "DRAM_nRAS" SLEWRATE=FAST ;
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#LOCATE COMP "DRAM_nCAS" SITE "K13" ;
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#IOBUF PORT "DRAM_nCAS" SLEWRATE=FAST ;
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#LOCATE COMP "DRAM_nWE" SITE "N16" ;
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#IOBUF PORT "DRAM_nWE" SLEWRATE=FAST ;
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#LOCATE COMP "DRAM_nCS" SITE "M15" ;
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#LOCATE COMP "DRAM_DQ[0]" SITE "P14" ;
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#LOCATE COMP "DRAM_DQ[1]" SITE "R15" ;
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#LOCATE COMP "DRAM_DQ[2]" SITE "N14" ;
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#LOCATE COMP "DRAM_DQ[3]" SITE "R16" ;
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#LOCATE COMP "DRAM_DQ[4]" SITE "J14" ;
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#LOCATE COMP "DRAM_DQ[5]" SITE "P15" ;
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#LOCATE COMP "DRAM_DQ[6]" SITE "K14" ;
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#LOCATE COMP "DRAM_DQ[7]" SITE "P16" ;
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#LOCATE COMP "DRAM_DQ[8]" SITE "D14" ;
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#LOCATE COMP "DRAM_DQ[9]" SITE "H14" ;
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#LOCATE COMP "DRAM_DQ[10]" SITE "H12" ;
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#LOCATE COMP "DRAM_DQ[11]" SITE "H13" ;
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#LOCATE COMP "DRAM_DQ[12]" SITE "E14" ;
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#LOCATE COMP "DRAM_DQ[13]" SITE "H15" ;
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#LOCATE COMP "DRAM_DQ[14]" SITE "J13" ;
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#LOCATE COMP "DRAM_DQ[15]" SITE "J16" ;
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#LOCATE COMP "DRAM_DQM[0]" SITE "M13" ;
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#IOBUF PORT "DRAM_DQM[0]" SLEWRATE=FAST ;
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#LOCATE COMP "DRAM_DQM[1]" SITE "F14" ;
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#IOBUF PORT "DRAM_DQM[1]" SLEWRATE=FAST ;
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### USB (chip located on the motherboard) ###
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#LOCATE COMP "USB_MB_TX" SITE "M11" ;
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#IOBUF PORT "USB_MB_TX" SLEWRATE=FAST ;
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#LOCATE COMP "USB_MB_RX" SITE "N12" ;
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#IOBUF PORT "USB_MB_RX" PULLMODE=UP ;
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#LOCATE COMP "USB_MB_RTS" SITE "N11" ;
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#IOBUF PORT "USB_MB_RTS" SLEWRATE=FAST ;
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#LOCATE COMP "USB_MB_CTS" SITE "M12" ;
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#IOBUF PORT "USB_MB_CTS" PULLMODE=UP ;
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### PMOD1 ###
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#LOCATE COMP "dbg_leds[16]" SITE "P1" ;
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#LOCATE COMP "dbg_leds[17]" SITE "N4" ;
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#LOCATE COMP "dbg_leds[18]" SITE "P2" ;
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#LOCATE COMP "dbg_leds[19]" SITE "P5" ;
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#LOCATE COMP "dbg_leds[20]" SITE "R1" ;
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#LOCATE COMP "dbg_leds[21]" SITE "N5" ;
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#LOCATE COMP "dbg_leds[22]" SITE "R2" ;
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#LOCATE COMP "dbg_leds[23]" SITE "N6" ;
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### PMOD2 ###
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#LOCATE COMP "dbg_leds[24]" SITE "R3" ;
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#LOCATE COMP "dbg_leds[25]" SITE "P11" ;
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#LOCATE COMP "dbg_leds[26]" SITE "P12" ;
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#LOCATE COMP "dbg_leds[27]" SITE "T3" ;
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#LOCATE COMP "dbg_leds[28]" SITE "R4" ;
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#LOCATE COMP "dbg_leds[29]" SITE "R12" ;
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#LOCATE COMP "dbg_leds[30]" SITE "T13" ;
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#LOCATE COMP "dbg_leds[31]" SITE "R5" ;
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### PMOD3 ###
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#LOCATE COMP "dbg_leds[8]" SITE "B2" ;
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#LOCATE COMP "dbg_leds[9]" SITE "B3" ;
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#LOCATE COMP "dbg_leds[10]" SITE "A4" ;
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#LOCATE COMP "dbg_leds[11]" SITE "D4" ;
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#LOCATE COMP "dbg_leds[12]" SITE "A2" ;
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#LOCATE COMP "dbg_leds[13]" SITE "B4" ;
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#LOCATE COMP "dbg_leds[14]" SITE "C3" ;
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#LOCATE COMP "dbg_leds[15]" SITE "C4" ;
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### PMOD4 ###
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#LOCATE COMP "dbg_leds[0]" SITE "J4" ;
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#LOCATE COMP "dbg_leds[1]" SITE "J5" ;
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#LOCATE COMP "dbg_leds[2]" SITE "H4" ;
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#LOCATE COMP "dbg_leds[3]" SITE "E4" ;
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#LOCATE COMP "dbg_leds[4]" SITE "J3" ;
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#LOCATE COMP "dbg_leds[5]" SITE "H3" ;
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#LOCATE COMP "dbg_leds[6]" SITE "E3" ;
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#LOCATE COMP "dbg_leds[7]" SITE "D3" ;
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||||
|
||||
|
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### Ethernet ###
|
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#LOCATE COMP "ETH_CLK_EN" SITE "B1" ;
|
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#LOCATE COMP "ETH_nRESET" SITE "C2" ;
|
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|
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#LOCATE COMP "ETH_nLED_Y" SITE "F1" ;
|
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#LOCATE COMP "ETH_nLED_G" SITE "G2" ;
|
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|
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#LOCATE COMP "ETH_MDC" SITE "J1" ;
|
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#LOCATE COMP "ETH_MDIO" SITE "H2" ;
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#IOBUF PORT "ETH_MDIO" OPENDRAIN=ON SLEWRATE=FAST ;
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#LOCATE COMP "ETH_MDINT" SITE "G1" ;
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#IOBUF PORT "ETH_MDINT" SLEWRATE=FAST ;
|
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|
||||
#LOCATE COMP "ETH_REF_CLK" SITE "P3" ;
|
||||
|
||||
#LOCATE COMP "ETH_TX_CLK" SITE "M4" ;
|
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#IOBUF PORT "ETH_TX_CLK" SLEWRATE=FAST ;
|
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#LOCATE COMP "ETH_TX_CTL" SITE "N3" ;
|
||||
#IOBUF PORT "ETH_TX_CTL" SLEWRATE=FAST ;
|
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#LOCATE COMP "ETH_TXD[0]" SITE "M3" ;
|
||||
#IOBUF PORT "ETH_TXD[0]" SLEWRATE=FAST ;
|
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#LOCATE COMP "ETH_TXD[1]" SITE "L4" ;
|
||||
#IOBUF PORT "ETH_TXD[1]" SLEWRATE=FAST ;
|
||||
#LOCATE COMP "ETH_TXD[2]" SITE "K4" ;
|
||||
#IOBUF PORT "ETH_TXD[2]" SLEWRATE=FAST ;
|
||||
#LOCATE COMP "ETH_TXD[3]" SITE "K3" ;
|
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#IOBUF PORT "ETH_TXD[3]" SLEWRATE=FAST ;
|
||||
|
||||
#LOCATE COMP "ETH_RX_CLK" SITE "K1" ;
|
||||
#LOCATE COMP "ETH_RX_CTL" SITE "K2" ;
|
||||
#LOCATE COMP "ETH_RXD[0]" SITE "L1" ;
|
||||
#LOCATE COMP "ETH_RXD[1]" SITE "L2" ;
|
||||
#LOCATE COMP "ETH_RXD[2]" SITE "M1" ;
|
||||
#LOCATE COMP "ETH_RXD[3]" SITE "M2" ;
|
||||
|
||||
|
||||
### Extras ###
|
||||
#LOCATE COMP "EXT[1]" SITE "P13" ;
|
||||
#LOCATE COMP "EXT[2]" SITE "R13" ;
|
||||
#LOCATE COMP "EXT[3]" SITE "A3" ;
|
||||
#LOCATE COMP "EXT[4]" SITE "A5" ;
|
||||
#LOCATE COMP "EXT[5]" SITE "B5" ;
|
||||
#LOCATE COMP "EXT[6]" SITE "C5" ;
|
||||
#LOCATE COMP "EXT[7]" SITE "C6" ;
|
||||
#LOCATE COMP "EXT[8]" SITE "D5" ;
|
||||
#LOCATE COMP "EXT[9]" SITE "D6" ;
|
||||
#LOCATE COMP "EXT[10]" SITE "A11" ;
|
||||
#LOCATE COMP "EXT[11]" SITE "A12" ;
|
||||
#LOCATE COMP "EXT[12]" SITE "B8" ;
|
||||
#LOCATE COMP "EXT[13]" SITE "B9" ;
|
||||
#LOCATE COMP "EXT[14]" SITE "B11" ;
|
||||
#LOCATE COMP "EXT[15]" SITE "C9" ;
|
||||
#LOCATE COMP "EXT[16]" SITE "C11" ;
|
||||
#LOCATE COMP "EXT[17]" SITE "D11" ;
|
||||
#LOCATE COMP "EXT[18]" SITE "D12" ;
|
||||
#LOCATE COMP "EXT[19]" SITE "E10" ;
|
||||
#LOCATE COMP "EXT[20]" SITE "E11" ;
|
||||
#LOCATE COMP "EXT[21]" SITE "E12" ;
|
||||
#LOCATE COMP "EXT[22]" SITE "L3" ;
|
||||
#LOCATE COMP "EXT[23]" SITE "M6" ;
|
||||
#LOCATE COMP "EXT[24]" SITE "N1" ;
|
||||
#LOCATE COMP "EXT[25]" SITE "P4" ;
|
||||
#LOCATE COMP "EXT[26]" SITE "P6" ;
|
||||
#LOCATE COMP "EXT[27]" SITE "T2" ;
|
||||
#LOCATE COMP "EXT[28]" SITE "T4" ;
|
||||
#LOCATE COMP "EXT[29]" SITE "E2" ;
|
||||
#LOCATE COMP "EXT[30]" SITE "F2" ;
|
||||
#LOCATE COMP "EXT[31]" SITE "F5" ;
|
||||
#LOCATE COMP "EXT[32]" SITE "G4" ;
|
||||
#LOCATE COMP "EXT[33]" SITE "G5" ;
|
||||
#LOCATE COMP "EXT[34]" SITE "J2" ;
|
||||
19
10-PipelinedOperators/Board/concat/pipelinedOperators.ucf
Normal file
19
10-PipelinedOperators/Board/concat/pipelinedOperators.ucf
Normal file
@ -0,0 +1,19 @@
|
||||
#-------------------------------------------------------------------------------
|
||||
# Clock and reset
|
||||
#
|
||||
NET "clock" LOC = "A10";
|
||||
NET "reset_N" LOC = "D3" | PULLUP;
|
||||
|
||||
#-------------------------------------------------------------------------------
|
||||
# Analog outputs
|
||||
#
|
||||
NET "xOut" LOC = "G4" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW;
|
||||
NET "yOut" LOC = "G5" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW;
|
||||
#NET "xOut" LOC = "G4" ;
|
||||
#NET "yOut" LOC = "G5" ;
|
||||
|
||||
#-------------------------------------------------------------------------------
|
||||
# Trigger output
|
||||
#
|
||||
NET "triggerOut" LOC = "D2" | IOSTANDARD = LVTTL | DRIVE = 2 | SLEW = SLOW;
|
||||
#NET "triggerOut" LOC = "D2" ;
|
||||
623
10-PipelinedOperators/Board/concat/pipelinedOperators.vhd
Normal file
623
10-PipelinedOperators/Board/concat/pipelinedOperators.vhd
Normal file
@ -0,0 +1,623 @@
|
||||
-- VHDL Entity Board.pipelineCounter_ebs3.symbol
|
||||
--
|
||||
-- Created:
|
||||
-- by - axel.amand.UNKNOWN (WE7860)
|
||||
-- at - 11:16:01 08.05.2023
|
||||
--
|
||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.numeric_std.all;
|
||||
|
||||
ENTITY pipelineCounter_ebs3 IS
|
||||
GENERIC(
|
||||
counterBitNb : positive := 16
|
||||
);
|
||||
PORT(
|
||||
clock : IN std_ulogic;
|
||||
reset_n : IN std_ulogic;
|
||||
countOut : OUT unsigned (counterBitNb-1 DOWNTO 0)
|
||||
);
|
||||
|
||||
-- Declarations
|
||||
|
||||
END pipelineCounter_ebs3 ;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
-- VHDL Entity PipelinedOperators.pipelineCounter.symbol
|
||||
--
|
||||
-- Created:
|
||||
-- by - francois.francois (Aphelia)
|
||||
-- at - 08:50:00 03/11/19
|
||||
--
|
||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.numeric_std.all;
|
||||
|
||||
ENTITY pipelineCounter IS
|
||||
GENERIC(
|
||||
bitNb : positive;
|
||||
stageNb : positive
|
||||
);
|
||||
PORT(
|
||||
countOut : OUT unsigned (bitNb-1 DOWNTO 0);
|
||||
clock : IN std_ulogic;
|
||||
reset : IN std_ulogic
|
||||
);
|
||||
|
||||
-- Declarations
|
||||
|
||||
END pipelineCounter ;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
-- VHDL Entity PipelinedOperators.pipelineAdder.symbol
|
||||
--
|
||||
-- Created:
|
||||
-- by - francois.francois (Aphelia)
|
||||
-- at - 08:50:15 03/11/19
|
||||
--
|
||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.numeric_std.all;
|
||||
|
||||
ENTITY pipelineAdder IS
|
||||
GENERIC(
|
||||
bitNb : positive;
|
||||
stageNb : positive
|
||||
);
|
||||
PORT(
|
||||
sum : OUT signed (bitNb-1 DOWNTO 0);
|
||||
clock : IN std_ulogic;
|
||||
reset : IN std_ulogic;
|
||||
cIn : IN std_ulogic;
|
||||
cOut : OUT std_ulogic;
|
||||
a : IN signed (bitNb-1 DOWNTO 0);
|
||||
b : IN signed (bitNb-1 DOWNTO 0)
|
||||
);
|
||||
|
||||
-- Declarations
|
||||
|
||||
END pipelineAdder ;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
-- VHDL Entity PipelinedOperators.parallelAdder.symbol
|
||||
--
|
||||
-- Created:
|
||||
-- by - axel.amand.UNKNOWN (WE7860)
|
||||
-- at - 11:43:49 28.04.2023
|
||||
--
|
||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.numeric_std.all;
|
||||
|
||||
ENTITY parallelAdder IS
|
||||
GENERIC(
|
||||
bitNb : positive := 32
|
||||
);
|
||||
PORT(
|
||||
sum : OUT signed (bitNb-1 DOWNTO 0);
|
||||
cIn : IN std_ulogic;
|
||||
cOut : OUT std_ulogic;
|
||||
a : IN signed (bitNb-1 DOWNTO 0);
|
||||
b : IN signed (bitNb-1 DOWNTO 0)
|
||||
);
|
||||
|
||||
-- Declarations
|
||||
|
||||
END parallelAdder ;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
ARCHITECTURE masterVersion OF parallelAdder IS
|
||||
|
||||
signal sum_int: unsigned(sum'high+1 downto 0);
|
||||
|
||||
BEGIN
|
||||
|
||||
sum_int <= resize(unsigned(a), sum_int'length) +
|
||||
resize(unsigned(b), sum_int'length) +
|
||||
resize('0' & cIn, sum_int'length);
|
||||
|
||||
sum <= signed(sum_int(sum'range));
|
||||
cOut <= sum_int(sum_int'high);
|
||||
|
||||
END ARCHITECTURE masterVersion;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
ARCHITECTURE masterVersion OF pipelineAdder IS
|
||||
|
||||
constant stageBitNb : positive := sum'length/stageNb;
|
||||
subtype stageOperandType is signed(stageBitNb-1 downto 0);
|
||||
type stageOperandVectorType is array(stageNb-1 downto 0) of stageOperandType;
|
||||
type stageOperandMatrixType is array(stageNb-1 downto 0) of stageOperandVectorType;
|
||||
subtype carryType is std_ulogic_vector(stageNb downto 0);
|
||||
|
||||
signal a_int, b_int, sum_int : stageOperandMatrixType;
|
||||
signal carryIn, carryOut : carryType;
|
||||
|
||||
COMPONENT parallelAdder
|
||||
GENERIC (
|
||||
bitNb : positive := 32
|
||||
);
|
||||
PORT (
|
||||
sum : OUT signed (bitNb-1 DOWNTO 0);
|
||||
cIn : IN std_ulogic ;
|
||||
cOut : OUT std_ulogic ;
|
||||
a : IN signed (bitNb-1 DOWNTO 0);
|
||||
b : IN signed (bitNb-1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
|
||||
carryIn(0) <= cIn;
|
||||
|
||||
distributeInput: for wordIndex in stageOperandVectorType'range generate
|
||||
a_int(wordIndex)(0) <= a(wordIndex*stageBitNb+stageBitNb-1 downto wordIndex*stageBitNb);
|
||||
b_int(wordIndex)(0) <= b(wordIndex*stageBitNb+stageBitNb-1 downto wordIndex*stageBitNb);
|
||||
end generate distributeInput;
|
||||
|
||||
inputRegistersX: for wordIndex in stageOperandVectorType'high downto 1 generate
|
||||
inputRegistersY: for pipeIndex in stageOperandMatrixType'high downto 1 generate
|
||||
upperTriangle: if wordIndex >= pipeIndex generate
|
||||
inputRegisters: process(reset, clock)
|
||||
begin
|
||||
if reset = '1' then
|
||||
a_int(wordIndex)(pipeIndex) <= (others => '0');
|
||||
b_int(wordIndex)(pipeIndex) <= (others => '0');
|
||||
elsif rising_edge(clock) then
|
||||
a_int(wordIndex)(pipeIndex) <= a_int(wordIndex)(pipeIndex-1);
|
||||
b_int(wordIndex)(pipeIndex) <= b_int(wordIndex)(pipeIndex-1);
|
||||
end if;
|
||||
end process inputRegisters;
|
||||
end generate upperTriangle;
|
||||
end generate inputRegistersY;
|
||||
end generate inputRegistersX;
|
||||
|
||||
operation: for index in stageOperandVectorType'range generate
|
||||
partialAdder: parallelAdder
|
||||
GENERIC MAP (bitNb => stageBitNb)
|
||||
PORT MAP (
|
||||
a => a_int(index)(index),
|
||||
b => b_int(index)(index),
|
||||
sum => sum_int(index)(index),
|
||||
cIn => carryIn(index),
|
||||
cOut => carryOut(index)
|
||||
);
|
||||
carryRegisters: process(reset, clock)
|
||||
begin
|
||||
if reset = '1' then
|
||||
carryIn(index+1) <= '0';
|
||||
elsif rising_edge(clock) then
|
||||
carryIn(index+1) <= carryOut(index);
|
||||
end if;
|
||||
end process carryRegisters;
|
||||
end generate operation;
|
||||
|
||||
outputRegistersX: for wordIndex in stageOperandVectorType'range generate
|
||||
outputRegistersY: for pipeIndex in stageOperandMatrixType'range generate
|
||||
lowerTriangle: if wordIndex < pipeIndex generate
|
||||
outputRegisters: process(reset, clock)
|
||||
begin
|
||||
if reset = '1' then
|
||||
sum_int(wordIndex)(pipeIndex) <= (others => '0');
|
||||
elsif rising_edge(clock) then
|
||||
sum_int(wordIndex)(pipeIndex) <= sum_int(wordIndex)(pipeIndex-1);
|
||||
end if;
|
||||
end process outputRegisters;
|
||||
end generate lowerTriangle;
|
||||
end generate outputRegistersY;
|
||||
end generate outputRegistersX;
|
||||
|
||||
packOutput: for index in stageOperandVectorType'range generate
|
||||
sum(index*stageBitNb+stageBitNb-1 downto index*stageBitNb) <=
|
||||
sum_int(index)(stageOperandMatrixType'high);
|
||||
end generate packOutput;
|
||||
|
||||
cOut <= carryOut(carryOut'high-1);
|
||||
|
||||
END ARCHITECTURE masterVersion;
|
||||
|
||||
|
||||
|
||||
|
||||
ARCHITECTURE masterVersion OF pipelineCounter IS
|
||||
|
||||
signal initCounter : unsigned(countOut'length/stageNb-1 downto 0);
|
||||
signal b : signed(countOut'range);
|
||||
signal sum : signed(countOut'range);
|
||||
|
||||
COMPONENT pipelineAdder
|
||||
GENERIC (
|
||||
bitNb : positive := 32;
|
||||
stageNb : positive := 4
|
||||
);
|
||||
PORT (
|
||||
reset : IN std_ulogic;
|
||||
clock : IN std_ulogic;
|
||||
cIn : IN std_ulogic;
|
||||
a : IN signed (bitNb-1 DOWNTO 0);
|
||||
b : IN signed (bitNb-1 DOWNTO 0);
|
||||
sum : OUT signed (bitNb-1 DOWNTO 0);
|
||||
cOut : OUT std_ulogic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
|
||||
adder: pipelineAdder
|
||||
GENERIC MAP (
|
||||
bitNb => countOut'length,
|
||||
stageNb => stageNb
|
||||
)
|
||||
PORT MAP (
|
||||
reset => reset,
|
||||
clock => clock,
|
||||
cIn => '0',
|
||||
a => sum,
|
||||
b => b,
|
||||
sum => sum,
|
||||
cOut => open
|
||||
);
|
||||
|
||||
prepareBInput: process(reset, clock)
|
||||
begin
|
||||
if reset = '1' then
|
||||
initCounter <= (others => '0');
|
||||
elsif rising_edge(clock) then
|
||||
if initCounter < stageNb then
|
||||
initCounter <= initCounter + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process prepareBInput;
|
||||
|
||||
selectInitOrRun: process(initCounter, sum)
|
||||
begin
|
||||
if initCounter < stageNb-1 then
|
||||
b <= signed(resize(initCounter+stageNb-1, b'length));
|
||||
countOut <= resize(initCounter, countOut'length);
|
||||
else
|
||||
b <= to_signed(stageNb-1, b'length);
|
||||
countOut <= unsigned(sum);
|
||||
end if;
|
||||
end process selectInitOrRun;
|
||||
|
||||
END ARCHITECTURE masterVersion;
|
||||
|
||||
|
||||
|
||||
|
||||
-- VHDL Entity Board.DFF.symbol
|
||||
--
|
||||
-- Created:
|
||||
-- by - francois.francois (Aphelia)
|
||||
-- at - 13:07:05 02/19/19
|
||||
--
|
||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
ENTITY DFF IS
|
||||
PORT(
|
||||
CLK : IN std_uLogic;
|
||||
CLR : IN std_uLogic;
|
||||
D : IN std_uLogic;
|
||||
Q : OUT std_uLogic
|
||||
);
|
||||
|
||||
-- Declarations
|
||||
|
||||
END DFF ;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
ARCHITECTURE sim OF DFF IS
|
||||
BEGIN
|
||||
|
||||
process(clk, clr)
|
||||
begin
|
||||
if clr = '1' then
|
||||
q <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
q <= d;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
END ARCHITECTURE sim;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
-- VHDL Entity Board.inverterIn.symbol
|
||||
--
|
||||
-- Created:
|
||||
-- by - francois.francois (Aphelia)
|
||||
-- at - 13:07:14 02/19/19
|
||||
--
|
||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
ENTITY inverterIn IS
|
||||
PORT(
|
||||
in1 : IN std_uLogic;
|
||||
out1 : OUT std_uLogic
|
||||
);
|
||||
|
||||
-- Declarations
|
||||
|
||||
END inverterIn ;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
ARCHITECTURE sim OF inverterIn IS
|
||||
BEGIN
|
||||
|
||||
out1 <= NOT in1;
|
||||
|
||||
END ARCHITECTURE sim;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454
|
||||
-- Module Version: 5.7
|
||||
--C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n pll -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00 -type pll -fin 100.00 -fclkop 60 -fclkop_tol 10.0 -fclkos 75 -fclkos_tol 10.0 -phases 0 -fclkos2 50 -fclkos2_tol 10.0 -phases2 0 -fclkos3 10 -fclkos3_tol 10.0 -phases3 0 -phase_cntl STATIC -enable_s -enable_s2 -enable_s3 -pllLocked -fb_mode 1 -fdc C:/temp/clocker/pll/pll.fdc
|
||||
|
||||
-- Offers 10MHz, 50MHz, 60MHz and 75MHz clocks
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
library ECP5U;
|
||||
use ECP5U.components.all;
|
||||
|
||||
ENTITY pll IS
|
||||
PORT(
|
||||
clkIn100M : IN std_ulogic;
|
||||
en75M : IN std_ulogic;
|
||||
en50M : IN std_ulogic;
|
||||
en10M : IN std_ulogic;
|
||||
clk60MHz : OUT std_ulogic;
|
||||
clk75MHz : OUT std_ulogic;
|
||||
clk50MHz : OUT std_ulogic;
|
||||
clk10MHz : OUT std_ulogic;
|
||||
pllLocked : OUT std_ulogic
|
||||
);
|
||||
|
||||
-- Declarations
|
||||
|
||||
END pll ;
|
||||
|
||||
architecture rtl of pll is
|
||||
|
||||
-- internal signal declarations
|
||||
signal REFCLK: std_logic;
|
||||
signal CLKOS3_t: std_logic;
|
||||
signal CLKOS2_t: std_logic;
|
||||
signal CLKOS_t: std_logic;
|
||||
signal CLKOP_t: std_logic;
|
||||
signal scuba_vhi: std_logic;
|
||||
signal scuba_vlo: std_logic;
|
||||
|
||||
attribute FREQUENCY_PIN_CLKOS3 : string;
|
||||
attribute FREQUENCY_PIN_CLKOS2 : string;
|
||||
attribute FREQUENCY_PIN_CLKOS : string;
|
||||
attribute FREQUENCY_PIN_CLKOP : string;
|
||||
attribute FREQUENCY_PIN_CLKI : string;
|
||||
attribute ICP_CURRENT : string;
|
||||
attribute LPF_RESISTOR : string;
|
||||
attribute FREQUENCY_PIN_CLKOS3 of PLLInst_0 : label is "10.000000";
|
||||
attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "50.000000";
|
||||
attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "75.000000";
|
||||
attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "60.000000";
|
||||
attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "100.000000";
|
||||
attribute ICP_CURRENT of PLLInst_0 : label is "5";
|
||||
attribute LPF_RESISTOR of PLLInst_0 : label is "16";
|
||||
attribute syn_keep : boolean;
|
||||
attribute NGD_DRC_MASK : integer;
|
||||
attribute NGD_DRC_MASK of rtl : architecture is 1;
|
||||
|
||||
begin
|
||||
-- component instantiation statements
|
||||
scuba_vhi_inst: VHI
|
||||
port map (Z=>scuba_vhi);
|
||||
|
||||
scuba_vlo_inst: VLO
|
||||
port map (Z=>scuba_vlo);
|
||||
|
||||
PLLInst_0: EHXPLLL
|
||||
generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED",
|
||||
STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED",
|
||||
CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 59, CLKOS2_FPHASE=> 0,
|
||||
CLKOS2_CPHASE=> 11, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 7,
|
||||
CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 9, PLL_LOCK_MODE=> 0,
|
||||
CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING",
|
||||
CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING",
|
||||
OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED",
|
||||
OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "DISABLED",
|
||||
OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "DISABLED",
|
||||
OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 60,
|
||||
CLKOS2_DIV=> 12, CLKOS_DIV=> 8, CLKOP_DIV=> 10, CLKFB_DIV=> 3,
|
||||
CLKI_DIV=> 5, FEEDBK_PATH=> "CLKOP")
|
||||
port map (CLKI=>clkIn100M, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo,
|
||||
PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo,
|
||||
PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo,
|
||||
STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo,
|
||||
ENCLKOP=>scuba_vlo, ENCLKOS=>en75M, ENCLKOS2=>en50M,
|
||||
ENCLKOS3=>en10M, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t,
|
||||
CLKOS2=>CLKOS2_t, CLKOS3=>CLKOS3_t, LOCK=>pllLocked,
|
||||
INTLOCK=>open, REFCLK=>REFCLK, CLKINTFB=>open);
|
||||
|
||||
clk10MHz <= CLKOS3_t;
|
||||
clk50MHz <= CLKOS2_t;
|
||||
clk75MHz <= CLKOS_t;
|
||||
clk60MHz <= CLKOP_t;
|
||||
end rtl;
|
||||
|
||||
|
||||
|
||||
|
||||
--
|
||||
-- VHDL Architecture Board.pipelineCounter_ebs3.struct
|
||||
--
|
||||
-- Created:
|
||||
-- by - axel.amand.UNKNOWN (WE7860)
|
||||
-- at - 11:16:01 08.05.2023
|
||||
--
|
||||
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.numeric_std.all;
|
||||
|
||||
-- LIBRARY Board;
|
||||
-- LIBRARY Lattice;
|
||||
-- LIBRARY PipelinedOperators;
|
||||
|
||||
ARCHITECTURE struct OF pipelineCounter_ebs3 IS
|
||||
|
||||
-- Architecture declarations
|
||||
constant pipelineStageNb: positive := 5;
|
||||
|
||||
-- Internal signal declarations
|
||||
SIGNAL clk_sys : std_ulogic;
|
||||
SIGNAL logic0 : std_ulogic;
|
||||
SIGNAL logic1 : std_uLogic;
|
||||
SIGNAL reset : std_ulogic;
|
||||
SIGNAL resetSynch : std_ulogic;
|
||||
SIGNAL resetSynch_n : std_ulogic;
|
||||
|
||||
|
||||
-- Component Declarations
|
||||
COMPONENT DFF
|
||||
PORT (
|
||||
CLK : IN std_uLogic ;
|
||||
CLR : IN std_uLogic ;
|
||||
D : IN std_uLogic ;
|
||||
Q : OUT std_uLogic
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT inverterIn
|
||||
PORT (
|
||||
in1 : IN std_uLogic ;
|
||||
out1 : OUT std_uLogic
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT pll
|
||||
PORT (
|
||||
clkIn100M : IN std_ulogic ;
|
||||
en75M : IN std_ulogic ;
|
||||
en50M : IN std_ulogic ;
|
||||
en10M : IN std_ulogic ;
|
||||
clk60MHz : OUT std_ulogic ;
|
||||
clk75MHz : OUT std_ulogic ;
|
||||
clk50MHz : OUT std_ulogic ;
|
||||
clk10MHz : OUT std_ulogic ;
|
||||
pllLocked : OUT std_ulogic
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT pipelineCounter
|
||||
GENERIC (
|
||||
bitNb : positive;
|
||||
stageNb : positive
|
||||
);
|
||||
PORT (
|
||||
countOut : OUT unsigned (bitNb-1 DOWNTO 0);
|
||||
clock : IN std_ulogic ;
|
||||
reset : IN std_ulogic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
-- Optional embedded configurations
|
||||
-- pragma synthesis_off
|
||||
-- FOR ALL : DFF USE ENTITY Board.DFF;
|
||||
-- FOR ALL : inverterIn USE ENTITY Board.inverterIn;
|
||||
-- FOR ALL : pipelineCounter USE ENTITY PipelinedOperators.pipelineCounter;
|
||||
-- FOR ALL : pll USE ENTITY Lattice.pll;
|
||||
-- pragma synthesis_on
|
||||
|
||||
|
||||
BEGIN
|
||||
-- Architecture concurrent statements
|
||||
-- HDL Embedded Text Block 5 eb5
|
||||
logic1 <= '1';
|
||||
|
||||
-- HDL Embedded Text Block 6 eb6
|
||||
logic0 <= '0';
|
||||
|
||||
|
||||
-- Instance port mappings.
|
||||
I_dff : DFF
|
||||
PORT MAP (
|
||||
CLK => clock,
|
||||
CLR => reset,
|
||||
D => logic1,
|
||||
Q => resetSynch_n
|
||||
);
|
||||
I_inv1 : inverterIn
|
||||
PORT MAP (
|
||||
in1 => reset_n,
|
||||
out1 => reset
|
||||
);
|
||||
I_inv2 : inverterIn
|
||||
PORT MAP (
|
||||
in1 => resetSynch_n,
|
||||
out1 => resetSynch
|
||||
);
|
||||
I_pll : pll
|
||||
PORT MAP (
|
||||
clkIn100M => clock,
|
||||
en75M => logic0,
|
||||
en50M => logic0,
|
||||
en10M => logic0,
|
||||
clk60MHz => clk_sys,
|
||||
clk75MHz => OPEN,
|
||||
clk50MHz => OPEN,
|
||||
clk10MHz => OPEN,
|
||||
pllLocked => OPEN
|
||||
);
|
||||
I_cnt : pipelineCounter
|
||||
GENERIC MAP (
|
||||
bitNb => counterBitNb,
|
||||
stageNb => pipelineStageNb
|
||||
)
|
||||
PORT MAP (
|
||||
countOut => countOut,
|
||||
clock => clk_sys,
|
||||
reset => resetSynch
|
||||
);
|
||||
|
||||
END struct;
|
||||
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user