Initial commit

10-PipelinedOperators/Board/hdl/DFF_sim.vhd

@@ -0,0 +1,14 @@
+ARCHITECTURE sim OF DFF IS
+BEGIN
+
+  process(clk, clr)
+  begin
+    if clr = '1' then
+      q <= '0';
+    elsif rising_edge(clk) then
+      q <= d;
+    end if;
+  end process;
+
+END ARCHITECTURE sim;
+

10-PipelinedOperators/Board/hdl/buff_sim.vhd

@@ -0,0 +1,7 @@
+ARCHITECTURE sim OF buff IS
+BEGIN
+
+  out1 <= in1;
+
+END ARCHITECTURE sim;
+

10-PipelinedOperators/Board/hdl/inverterIn_sim.vhd

@@ -0,0 +1,7 @@
+ARCHITECTURE sim OF inverterIn IS
+BEGIN
+
+  out1 <= NOT in1;
+
+END ARCHITECTURE sim;
+

10-PipelinedOperators/Board/hdl/inverter_sim.vhd

@@ -0,0 +1,7 @@
+ARCHITECTURE sim OF inverter IS
+BEGIN
+
+  out1 <= NOT in1;
+
+END ARCHITECTURE sim;
+