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2024-02-23 13:01:05 +00:00
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48
10-PipelinedOperators/PipelinedOperators_test/hdl/parallelAdder_tester_test.vhd Normal file
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ARCHITECTURE test OF parallelAdder_tester IS
constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
signal sClock: std_uLogic := '1';
signal sReset: std_uLogic := '1';
constant aMax: signed(a'range) := (a'high => '0', others => '1');
constant aIncr: signed(a'range) := shift_right(aMax, 4)+1;
constant bIncr: signed(b'range) := shift_right(aMax, 4)+1;
signal a_int, b_int, sum_int: signed(a'range);
BEGIN
------------------------------------------------------------------------------
-- clock and reset
sClock <= not sClock after clockPeriod/2;
sReset <= '1', '0' after 2*clockPeriod;
------------------------------------------------------------------------------
-- test sequence
process
begin
a_int <= (a_int'high => '1', others => '0');
b_int <= (b_int'high => '1', others => '0');
wait until sReset = '0';
-- data values
while a_int < aMax-aIncr loop
a_int <= a_int + aIncr;
b_int <= b_int + bIncr;
wait until rising_edge(sClock);
assert sum = a_int + b_int
report "sum is wrong !"
severity error;
end loop;
-- stop simulation
assert false
report cr & cr &
"End of Simulation" &
cr
severity failure;
wait;
end process;
cIn <= '0';
a <= a_int;
b <= b_int;
sum_int <= a_int + b_int;
END ARCHITECTURE test;

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ARCHITECTURE test OF pipelineAdder_tester IS
constant clockFrequency: real := 66.0E6;
constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
signal sClock: std_uLogic := '1';
signal sReset: std_uLogic := '1';
constant pipeDelay: positive := 4;
constant aMax: signed(a'range) := (a'high => '0', others => '1');
constant aIncr: signed(a'range) := shift_right(aMax, 3)+1 + 32;
constant bIncr: signed(b'range) := shift_right(aMax, 3)+1 + 32;
signal a_int, b_int, sumNoPipe: signed(a'range);
type sumArrayType is array(1 to stageNb-1) of signed(sumNoPipe'range);
signal sumArray : sumArrayType := (others => (others => '0'));
BEGIN
------------------------------------------------------------------------------
-- clock and reset
sClock <= not sClock after clockPeriod/2;
clock <= transport sClock after clockPeriod*9/10;
sReset <= '1', '0' after 2*clockPeriod;
reset <= sReset;
------------------------------------------------------------------------------
-- test sequence
process
begin
a_int <= (a_int'high => '1', others => '0');
b_int <= (b_int'high => '1', others => '0');
wait until sReset = '0';
-- data values
while a_int < aMax-aIncr loop
a_int <= a_int + aIncr;
b_int <= b_int + bIncr;
wait until rising_edge(sClock);
end loop;
-- stop simulation
for index in 1 to pipeDelay loop
wait until rising_edge(sClock);
end loop;
assert false
report cr & cr &
"End of Simulation" &
cr
severity failure;
wait;
end process;
cIn <= '0';
a <= a_int;
b <= b_int;
sumNoPipe <= a_int + b_int;
------------------------------------------------------------------------------
-- delay sum
process(sClock)
begin
if rising_edge(sClock) then
sumArray(1) <= sumNoPipe;
sumArray(2 to sumArray'length) <= sumArray(1 to sumArray'length-1);
assert sum = sumArray(sumArray'length-1)
report "sum is wrong !"
severity error;
end if;
end process;
END ARCHITECTURE test;

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10-PipelinedOperators/PipelinedOperators_test/hdl/pipelineCounter_tester_test.vhd Normal file
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--
-- VHDL Architecture PipelinedOperators_test.PipelineCounter_tester.test
--
-- Created:
-- by - zas.UNKNOWN (ZELL)
-- at - 16:00:38 02/20/2020
--
-- using Mentor Graphics HDL Designer(TM) 2019.2 (Build 5)
--
ARCHITECTURE test OF PipelineCounter_tester IS
constant clockFrequency: real := 66.0E6;
constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
signal sClock: std_uLogic := '1';
BEGIN
------------------------------------------------------------------------------
-- clock and reset
sClock <= not sClock after clockPeriod/2;
clock <= transport sClock after clockPeriod*9/10;
reset <= '1', '0' after 2*clockPeriod;
END ARCHITECTURE test;

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10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_parallelAdder_tester_test.vhd._fpf Normal file
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DIALECT atom VHDL_2008

1
10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_paralleladder_tb_entity.vhg._fpf Normal file
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DIALECT atom VHDL_2008

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10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_paralleladder_tb_struct.vhg._fpf Normal file
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DIALECT atom VHDL_2008

1
10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_paralleladder_tester_entity.vhg._fpf Normal file
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DIALECT atom VHDL_ANY

1
10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_pipelineAdder_tester_test.vhd._fpf Normal file
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DIALECT atom VHDL_2008

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10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_pipelineCounter_tester_test.vhd._fpf Normal file
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DIALECT atom VHDL_2008
INCLUDE list {
DEFAULT atom 1
}

1
10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_pipelineadder_tb_entity.vhg._fpf Normal file
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DIALECT atom VHDL_2008

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10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_pipelineadder_tb_struct.vhg._fpf Normal file
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DIALECT atom VHDL_2008

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10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_pipelineadder_tester_entity.vhg._fpf Normal file
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DIALECT atom VHDL_ANY

1
10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_pipelinecounter_tb_entity.vhg._fpf Normal file
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DIALECT atom VHDL_2008

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10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_pipelinecounter_tb_struct.vhg._fpf Normal file
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DIALECT atom VHDL_2008

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10-PipelinedOperators/PipelinedOperators_test/hds/.hdlsidedata/_pipelinecounter_tester_entity.vhg._fpf Normal file
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DIALECT atom VHDL_2008

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10-PipelinedOperators/PipelinedOperators_test/hds/_paralleladder_tb._epf Normal file
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DEFAULT_FILE atom parallel@adder_tb/struct.bd
DEFAULT_ARCHITECTURE atom struct
TOP_MARKER atom 0

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10-PipelinedOperators/PipelinedOperators_test/hds/_paralleladder_tester._epf Normal file
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DEFAULT_ARCHITECTURE atom test
DEFAULT_FILE atom parallelAdder_tester_test.vhd

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10-PipelinedOperators/PipelinedOperators_test/hds/_pipelineadder_tb._epf Normal file
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DEFAULT_FILE atom pipeline@adder_tb/struct.bd
DEFAULT_ARCHITECTURE atom struct
TOP_MARKER atom 1

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10-PipelinedOperators/PipelinedOperators_test/hds/_pipelineadder_tester._epf Normal file
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DEFAULT_ARCHITECTURE atom test
DEFAULT_FILE atom pipelineAdder_tester_test.vhd

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10-PipelinedOperators/PipelinedOperators_test/hds/_pipelinecounter_tb._epf Normal file
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DEFAULT_FILE atom pipeline@counter_tb/struct.bd
DEFAULT_ARCHITECTURE atom struct
TOP_MARKER atom 1

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10-PipelinedOperators/PipelinedOperators_test/hds/_pipelinecounter_tester._epf Normal file
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DEFAULT_ARCHITECTURE atom test
DEFAULT_FILE atom pipelineCounter_tester_test.vhd

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