Initial commit

Libs/AhbLite/hdl/ahbDecoder_RTL.vhd

@@ -0,0 +1,19 @@
+LIBRARY AhbLite;
+  USE AhbLite.ahbLite.all;
+
+ARCHITECTURE RTL OF ahbDecoder IS
+BEGIN
+
+  decodeAddress: process(hAddr)
+    variable mask: unsigned(hAddr'range);
+  begin
+    hSel <= (others => '0');
+    for index in hSel'range loop
+      mask := to_unsigned(ahbMemoryLocation(index).addressMask, mask'length);
+      if (hAddr and mask) = ahbMemoryLocation(index).baseAddress then
+        hSel(index) <= '1';
+      end if;
+    end loop;
+  end process decodeAddress;
+
+END ARCHITECTURE RTL;

Libs/AhbLite/hdl/ahbLite_pkg.vhd

@@ -0,0 +1,59 @@
+LIBRARY ieee;
+  USE ieee.std_logic_1164.all;
+
+PACKAGE ahbLite IS
+  ------------------------------------------------------------------------------
+                                                         -- bus components sizes
+  constant ahbAddressBitNb  : positive := 16;
+  constant ahbDataBitNb     : positive := 16;
+  constant ahbSlaveNb       : positive := 16;
+
+  constant ahbTransBitNb    : positive := 2;
+  constant ahbSizeBitNb     : positive := 1;
+  constant ahbBurstBitNb    : positive := 3;
+  constant ahbProtBitNb     : positive := 4;
+
+  ------------------------------------------------------------------------------
+                                                         -- bus data vector type
+  subtype ahbDataType is std_logic_vector(ahbDataBitNb-1 downto 0);
+  type ahbDataVector is array(1 to ahbSlaveNb) of ahbDataType;
+
+  ------------------------------------------------------------------------------
+                                                              -- address decoder
+  type ahbMemoryLocationType is
+    record
+      baseAddress: natural;
+      addressMask: natural;
+    end record;
+  type ahbMemoryLocationVector is array(1 to ahbSlaveNb) of ahbMemoryLocationType;
+
+  ------------------------------------------------------------------------------
+                                                                  -- bus signals
+  subtype transferType is std_ulogic_vector(ahbTransBitNb-1 downto 0);
+  constant transIdle  : transferType := "00";
+  constant transBusy  : transferType := "01";
+  constant transNonSeq: transferType := "10";
+  constant transSeq   : transferType := "11";
+
+  subtype transferSizeType is std_ulogic_vector(ahbSizeBitNb-1 downto 0);
+  constant size8   : transferSizeType := "0";
+  constant size16  : transferSizeType := "1";
+
+  subtype burstType is std_ulogic_vector(ahbBurstBitNb-1 downto 0);
+  constant burstSingle : burstType := "000";
+  constant burstIncr   : burstType := "001";
+  constant burstWrap4  : burstType := "010";
+  constant burstIncr4  : burstType := "011";
+  constant burstWrap8  : burstType := "100";
+  constant burstIncr8  : burstType := "101";
+  constant burstWrap16 : burstType := "110";
+  constant burstIncr16 : burstType := "111";
+
+  subtype protectionType is std_ulogic_vector(ahbProtBitNb-1 downto 0);
+  constant protDefault : protectionType := "0011";
+
+  ------------------------------------------------------------------------------
+                                                                         -- log2
+  function addressBitNb (addressNb : natural) return natural;
+
+END ahbLite;

Libs/AhbLite/hdl/ahbLite_pkg_body.vhd

@@ -0,0 +1,15 @@
+PACKAGE BODY ahbLite IS
+
+  function addressBitNb (addressNb : natural) return natural is
+    variable powerOfTwo, bitNb : natural;
+  begin
+    powerOfTwo := 1;
+    bitNb := 0;
+    while powerOfTwo <= addressNb loop
+      powerOfTwo := 2 * powerOfTwo;
+      bitNb := bitNb + 1;
+    end loop;
+    return bitNb;
+  end addressBitNb;
+
+END ahbLite;

Libs/AhbLite/hdl/ahbMasterInterface_RTL.vhd

@@ -0,0 +1,70 @@
+ARCHITECTURE RTL OF ahbMasterInterface IS
+
+  signal addressReg: unsigned(pAddress'range);
+  signal newAddress: std_ulogic;
+  signal writeReg: std_ulogic;
+
+BEGIN
+  ------------------------------------------------------------------------------
+                                                              -- reset and clock
+  hReset_n <= not reset;
+  hClk <= clock;
+
+  ------------------------------------------------------------------------------
+                                                         -- address and controls
+  newAddress <= pReadStrobe or pWriteStrobe;
+
+  storeAddress: process(reset, clock)
+  begin
+    if reset = '1' then
+      addressReg <= (others => '0');
+    elsif rising_edge(clock) then
+      if newAddress = '1' then
+        addressReg <= pAddress;
+      end if;
+    end if;
+  end process storeAddress;
+
+  hAddr <= pAddress when newAddress = '1'
+    else addressReg;
+
+  storeWrite: process(reset, clock)
+  begin
+    if reset = '1' then
+      writeReg <= '0';
+    elsif rising_edge(clock) then
+      if newAddress = '1' then
+        writeReg <= pWriteStrobe;
+      end if;
+    end if;
+  end process storeWrite;
+
+  hWrite <= pWriteStrobe when newAddress = '1'
+    else writeReg;
+
+  hTrans <= transNonSeq when newAddress = '1'
+    else transIdle;
+
+  hSize <= size16;
+  hBurst <= burstSingle;
+  hProt <= protDefault;
+  hMastLock <= '0';
+
+  ------------------------------------------------------------------------------
+                                                                     -- data out
+  delayData: process(reset, clock)
+  begin
+    if reset = '1' then
+      hWData <= (others => '0');
+    elsif rising_edge(clock) then
+      if pWriteStrobe = '1' then
+        hWData <= pDataOut;
+      end if;
+    end if;
+  end process delayData;
+
+  ------------------------------------------------------------------------------
+                                                                      -- data in
+  pDataIn <= hRData;
+
+END ARCHITECTURE RTL;

Libs/AhbLite/hdl/ahbMultiplexor_RTL.vhd

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+ARCHITECTURE RTL OF ahbMultiplexor IS
+BEGIN
+
+  multiplexData: process(hSel, hRDataV, hReadyV, hRespV)
+  begin
+    hRData <= (others => '0');
+    hReady <= '1';
+    hResp  <= '0';
+    for index in hSel'range loop
+      if hSel(index) = '1' then
+        hRData <= std_ulogic_vector(hRDataV(index));
+        hReady <= hReadyV(index);
+        hResp  <= hRespV(index);
+      end if;
+    end loop;
+  end process multiplexData;
+
+END ARCHITECTURE RTL;

Libs/AhbLite/hdl/ahbMuxConnector_RTL.vhd

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+ARCHITECTURE RTL OF ahbMuxConnector IS
+BEGIN
+
+  hSel <= hSelV(index);
+
+  hRDataV(index) <= std_logic_vector(hRData);
+  hReadyV(index) <= hReady;
+  hRespV(index)  <= hResp;
+
+  hRDataV <= (others => (others => 'Z'));
+  hReadyV <= (others => 'Z');
+  hRespV  <= (others => 'Z');
+
+END ARCHITECTURE RTL;