Initial commit

Libs/RiscV/HEIRV32_test/hdl/heirv32_mc_tester_test.vhd

@@ -0,0 +1,118 @@
+LIBRARY std;
+  USE std.textio.ALL;
+
+LIBRARY ieee;
+  USE ieee.std_logic_textio.ALL;
+
+LIBRARY Common_test;
+  USE Common_test.testutils.all;
+
+ARCHITECTURE test OF heirv32_mc_tester IS
+
+  constant clockPeriod  : time := 1.0/66E6 * 1 sec;
+  signal sClock         : std_uLogic := '1';
+  signal sReset         : std_uLogic ;
+
+  signal testInfo       : string(1 to 40) := (others => ' ');
+
+BEGIN
+
+ ------------------------------------------------------------------------------
+                                                              -- reset and clock
+  sReset <= '1', '0' after 3.5*clockPeriod;
+  rst <= sReset;
+
+  sClock <= not sClock after clockPeriod/2;
+  clk <= transport sClock after 0.9*clockPeriod;
+
+  btns <= (others => '0');
+
+  process
+    -- Wait list
+    -- 3 clk for beq
+    -- 4 clk for others
+    -- 5 clk for lw
+  begin
+    en <= '0';
+
+    testInfo <= pad("Wait reset", testInfo'length);
+    wait until rst = '0';
+
+    while true loop
+      en <= '1';
+
+      testInfo <= pad("Addi, addr. 00", testInfo'length);
+      wait until clk'event and clk = '1';
+      wait for 3*clockPeriod;
+
+      testInfo <= pad("Addi, addr. 04", testInfo'length);
+      wait for 4*clockPeriod;
+
+      testInfo <= pad("Addi, addr. 08", testInfo'length);
+      wait for 4*clockPeriod;
+
+      testInfo <= pad("Or, addr. 0C", testInfo'length);
+      wait for 4*clockPeriod;
+
+      testInfo <= pad("And, addr. 10", testInfo'length);
+      wait for 4*clockPeriod;
+
+      testInfo <= pad("Add, addr. 14", testInfo'length);
+      wait for 4*clockPeriod;
+
+      testInfo <= pad("Beq, addr. 18", testInfo'length);
+      wait for 3*clockPeriod;
+
+      testInfo <= pad("Slt, addr. 1C", testInfo'length);
+      wait for 4*clockPeriod;
+
+      testInfo <= pad("Beq, addr. 20", testInfo'length);
+      wait for 3*clockPeriod;
+
+      --testInfo <= pad("Addi, addr. 24", testInfo'length);
+      --wait for 4*clockPeriod;
+
+      testInfo <= pad("Slt, addr. 28", testInfo'length);
+      wait for 4*clockPeriod;
+
+      testInfo <= pad("Add, addr. 2C", testInfo'length);
+      wait for 4*clockPeriod;
+
+      testInfo <= pad("Sub, addr. 30", testInfo'length);
+      wait for 4*clockPeriod;
+
+      testInfo <= pad("Sw, addr. 34", testInfo'length);
+      wait for 4*clockPeriod;
+
+      testInfo <= pad("Lw, addr. 38", testInfo'length);
+      wait for 5*clockPeriod;
+
+      testInfo <= pad("Add, addr. 3C", testInfo'length);
+      wait for 4*clockPeriod;
+
+      testInfo <= pad("Jal, addr. 40", testInfo'length);
+      wait for 4*clockPeriod;
+
+      --testInfo <= pad("Addi, addr. 44", testInfo'length);
+      --wait for 4*clockPeriod;
+
+      testInfo <= pad("Add, addr. 48", testInfo'length);
+      wait for 4*clockPeriod;
+
+      testInfo <= pad("Sw, addr.4C", testInfo'length);
+      wait for 4*clockPeriod;
+
+      testInfo <= pad("Beq, addr. 50", testInfo'length);
+      wait for 2.8*clockPeriod;
+
+      en <= '0';
+      testInfo <= pad("Wait a bit, program should restart", testInfo'length);
+      wait for 9.2*clockPeriod;
+      testInfo <= pad("PC should go to 0 on clock", testInfo'length);
+      en <= '1';
+      wait until clk'event and clk = '1';
+
+    end loop;
+  end process;
+
+END ARCHITECTURE test;

Libs/RiscV/HEIRV32_test/hdl/heirv32_sc_tester_rtl.vhd

@@ -0,0 +1,116 @@
+LIBRARY std;
+  USE std.textio.ALL;
+
+LIBRARY ieee;
+  USE ieee.std_logic_textio.ALL;
+
+LIBRARY Common_test;
+  USE Common_test.testutils.all;
+
+ARCHITECTURE rtl OF heirv32_sc_tester IS
+
+  constant clockPeriod  : time := 1.0/66E6 * 1 sec;
+  signal sClock         : std_uLogic := '1';
+  signal sReset         : std_uLogic ;
+
+  signal testInfo       : string(1 to 40) := (others => ' ');
+
+BEGIN
+
+ ------------------------------------------------------------------------------
+                                                              -- reset and clock
+  sReset <= '1', '0' after 3.5*clockPeriod;
+  rst <= sReset;
+
+  sClock <= not sClock after clockPeriod/2;
+  clk <= transport sClock after 0.9*clockPeriod;
+
+  btns <= (others => '0');
+
+  process
+    -- Wait list
+    -- 1 for all
+  begin
+    en <= '0';
+
+    testInfo <= pad("Wait reset", testInfo'length);
+    wait until rst = '0';
+
+    while true loop
+      en <= '1';
+
+      testInfo <= pad("Addi, addr. 00", testInfo'length);
+      wait until clk'event and clk = '1';
+      wait for clockPeriod;
+
+      testInfo <= pad("Addi, addr. 04", testInfo'length);
+      wait for clockPeriod;
+
+      testInfo <= pad("Addi, addr. 08", testInfo'length);
+      wait for clockPeriod;
+
+      testInfo <= pad("Or, addr. 0C", testInfo'length);
+      wait for clockPeriod;
+
+      testInfo <= pad("And, addr. 10", testInfo'length);
+      wait for clockPeriod;
+
+      testInfo <= pad("Add, addr. 14", testInfo'length);
+      wait for clockPeriod;
+
+      testInfo <= pad("Beq, addr. 18", testInfo'length);
+      wait for clockPeriod;
+
+      testInfo <= pad("Slt, addr. 1C", testInfo'length);
+      wait for clockPeriod;
+
+      testInfo <= pad("Beq, addr. 20", testInfo'length);
+      wait for clockPeriod;
+
+      --testInfo <= pad("Addi, addr. 24", testInfo'length);
+      --wait for clockPeriod;
+
+      testInfo <= pad("Slt, addr. 28", testInfo'length);
+      wait for clockPeriod;
+
+      testInfo <= pad("Add, addr. 2C", testInfo'length);
+      wait for clockPeriod;
+
+      testInfo <= pad("Sub, addr. 30", testInfo'length);
+      wait for clockPeriod;
+
+      testInfo <= pad("Sw, addr. 34", testInfo'length);
+      wait for clockPeriod;
+
+      testInfo <= pad("Lw, addr. 38", testInfo'length);
+      wait for clockPeriod;
+
+      testInfo <= pad("Add, addr. 3C", testInfo'length);
+      wait for clockPeriod;
+
+      testInfo <= pad("Jal, addr. 40", testInfo'length);
+      wait for clockPeriod;
+
+      --testInfo <= pad("Addi, addr. 44", testInfo'length);
+      --wait for clockPeriod;
+
+      testInfo <= pad("Add, addr. 48", testInfo'length);
+      wait for clockPeriod;
+
+      testInfo <= pad("Sw, addr.4C", testInfo'length);
+      wait for clockPeriod;
+
+      testInfo <= pad("Beq, addr. 50", testInfo'length);
+      wait for 0.8*clockPeriod;
+
+      en <= '0';
+      testInfo <= pad("Wait a bit, PC should be 0", testInfo'length);
+      wait for 9.2*clockPeriod;
+      testInfo <= pad("Enabling system", testInfo'length);
+      en <= '1';
+      wait until clk'event and clk = '1';
+
+    end loop;
+  end process;
+
+END ARCHITECTURE rtl;

Libs/RiscV/HEIRV32_test/hdl/universalTester_test.vhd

@@ -0,0 +1,51 @@
+LIBRARY std;
+  USE std.textio.ALL;
+
+LIBRARY ieee;
+  USE ieee.std_logic_textio.ALL;
+
+LIBRARY Common_test;
+  USE Common_test.testutils.all;
+
+ARCHITECTURE test OF universalTester IS
+
+  constant clockPeriod  : time := 1.0/66E6 * 1 sec;
+  signal sClock         : std_uLogic := '1';
+  signal sReset         : std_uLogic ;
+
+  signal testInfo       : string(1 to 40) := (others => ' ');
+
+BEGIN
+
+ ------------------------------------------------------------------------------
+                                                              -- reset and clock
+  sReset <= '1', '0' after 3.5*clockPeriod;
+  rst <= sReset;
+
+  sClock <= not sClock after clockPeriod/2;
+  clk <= transport sClock after 0.9*clockPeriod;
+
+  btns <= (others => '1'), (others=>'0') after 4.15 us;
+
+  process
+    -- Wait list
+    -- 3 clk for beq
+    -- 4 clk for others
+    -- 5 clk for lw
+  begin
+    en <= '0';
+
+    testInfo <= pad("Wait reset", testInfo'length);
+    wait until rst = '0';
+
+    while true loop
+      en <= '1';
+
+      testInfo <= pad("Running", testInfo'length);
+      wait;
+
+    end loop;
+  end process;
+
+END ARCHITECTURE test;
+

Libs/RiscV/HEIRV32_test/hds/.hdlsidedata/_heirv32_mc_tester_test.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/RiscV/HEIRV32_test/hds/.hdlsidedata/_heirv32_sc_tester_rtl.vhd._fpf

@@ -0,0 +1,4 @@
+DIALECT atom VHDL_2008
+INCLUDE list {
+ DEFAULT atom 1
+}

Libs/RiscV/HEIRV32_test/hds/.hdlsidedata/_heirv32_sc_tester_test.vhd._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_93

Libs/RiscV/HEIRV32_test/hds/.hdlsidedata/_heirv32_tb_universal.vhg._fpf

@@ -0,0 +1 @@
+DIALECT atom VHDL_2008

Libs/RiscV/HEIRV32_test/hds/.hdlsidedata/_heirv32_tester_test.vhd._fpf

@@ -0,0 +1,4 @@
+DIALECT atom VHDL_2008
+INCLUDE list {
+ DEFAULT atom 1
+}

Libs/RiscV/HEIRV32_test/hds/.hdlsidedata/_universalTester_test.vhd._fpf

@@ -0,0 +1,4 @@
+DIALECT atom VHDL_2008
+INCLUDE list {
+ DEFAULT atom 1
+}

Libs/RiscV/HEIRV32_test/hds/_heirv32_mc_tb._epf

@@ -0,0 +1,3 @@
+DEFAULT_FILE atom heirv32_mc_tb/struct.bd
+DEFAULT_ARCHITECTURE atom struct
+TOP_MARKER atom 1

Libs/RiscV/HEIRV32_test/hds/_heirv32_mc_tester._epf

@@ -0,0 +1,2 @@
+DEFAULT_FILE atom heirv32_mc_tester_test.vhd
+DEFAULT_ARCHITECTURE atom test

Libs/RiscV/HEIRV32_test/hds/_heirv32_sc_tb._epf

@@ -0,0 +1,3 @@
+DEFAULT_ARCHITECTURE atom struct
+DEFAULT_FILE atom heirv32_sc_tb/struct.bd
+TOP_MARKER atom 1

Libs/RiscV/HEIRV32_test/hds/_heirv32_sc_tester._epf

@@ -0,0 +1,2 @@
+DEFAULT_ARCHITECTURE atom rtl
+DEFAULT_FILE atom heirv32_sc_tester_rtl.vhd

Libs/RiscV/HEIRV32_test/hds/_universaltester._epf

@@ -0,0 +1,2 @@
+DEFAULT_FILE atom universalTester_test.vhd
+DEFAULT_ARCHITECTURE atom test