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65
Libs/RiscV/NEORV32/setups/README.md
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Libs/RiscV/NEORV32/setups/README.md
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# Exemplary FPGA Board Setups
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||||
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* [Setups using Commercial Toolchains](#Setups-using-Commercial-Toolchains)
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* [Setups using Open-Source Toolchains](#Setups-using-Open-Source-Toolchains)
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* [Adding Your Project Setup](#Adding-Your-Project-Setup)
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* [Setup-Specific NEORV32 Software Framework Modification](#Setup-Specific-NEORV32-Software-Framework-Modification)
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||||
|
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This folder provides exemplary NEORV32 SoC setups and projects for different FPGA platforms/boards.
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You can directly use one of the provided setups or use them as starting point to build your own setup.
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Project maintainers may make pull requests against this repository to [add or link their setups](#Adding-Your-Project-Setup).
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## Setups using Commercial Toolchains
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| Setup | Toolchain | Board :books: | FPGA | Author(s) |
|
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|:------|:----------|:--------------|:------|:----------|
|
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| :file_folder: [`de0-nano-test-setup`](https://github.com/stnolting/neorv32/tree/master/setups/quartus/de0-nano-test-setup) | Intel Quartus Prime | [Terasic DE0-Nano](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593) | Intel Cyclone IV `EP4CE22F17C6N` | [stnolting](https://github.com/stnolting) |
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| :file_folder: [`de0-nano-test-setup-qsys`](quartus/de0-nano-test-setup-qsys) | Intel Quartus Prime | [Terasic DE0-Nano](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593) | Intel Cyclone IV `EP4CE22F17C6N` | [torerams](https://github.com/torerams) |
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| :file_folder: [`de0-nano-test-setup-avalonmm`](quartus/de0-nano-test-setup-avalonmm-wrapper) | Intel Quartus Prime | [Terasic DE0-Nano](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593) | Intel Cyclone IV `EP4CE22F17C6N` | [torerams](https://github.com/torerams) |
|
||||
| :file_folder: [`terasic-cyclone-V-gx-starter-kit-test-setup`](https://github.com/stnolting/neorv32/tree/master/setups/quartus/terasic-cyclone-V-gx-starter-kit-test-setup) | Intel Quartus Prime | [Terasic Cyclone-V GX Starter Kit](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=830) | Intel Cyclone V `5CGXFC5C6F27C7N` | zs6mue |
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| :file_folder: [`UPduino_v3`](https://github.com/stnolting/neorv32/tree/master/setups/radiant/UPduino_v3) | Lattice Radiant | [tinyVision.ai Inc. UPduino `v3.0`](https://www.tindie.com/products/tinyvision_ai/upduino-v30-low-cost-lattice-ice40-fpga-board/) | Lattice iCE40 UltraPlus `iCE40UP5K-SG48I` | [stnolting](https://github.com/stnolting) |
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| :file_folder: [`arty-a7-35-test-setup`](https://github.com/stnolting/neorv32/tree/master/setups/vivado/arty-a7-test-setup) | Xilinx Vivado | [Digilent Arty A7-35](https://reference.digilentinc.com/reference/programmable-logic/arty-a7/start) | Xilinx Artix-7 `XC7A35TICSG324-1L` | [stnolting](https://github.com/stnolting) |
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| :file_folder: [`nexys-a7-test-setup`](https://github.com/stnolting/neorv32/tree/master/setups/vivado/nexys-a7-test-setup) | Xilinx Vivado | [Digilent Nexys A7](https://reference.digilentinc.com/reference/programmable-logic/nexys-a7/start) | Xilinx Artix-7 `XC7A50TCSG324-1` | [AWenzel83](https://github.com/AWenzel83) |
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| :file_folder: [`nexys-a7-test-setup`](https://github.com/stnolting/neorv32/tree/master/setups/vivado/nexys-a7-test-setup) | Xilinx Vivado | [Digilent Nexys 4 DDR](https://reference.digilentinc.com/reference/programmable-logic/nexys-4-ddr/start) | Xilinx Artix-7 `XC7A100TCSG324-1` | [AWenzel83](https://github.com/AWenzel83) |
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| :earth_africa: [custom CRC32 processor module for the nexys-a7 boards (**tutorial**)](https://github.com/motius/neorv32/tree/add-custom-crc32-module) | Xilinx Vivado | [Digilent Nexys A7](https://reference.digilentinc.com/reference/programmable-logic/nexys-a7/start) | Xilinx Artix-7 `XC7A50TCSG324-1` | [motius](https://github.com/motius) ([ikstvn](https://github.com/ikstvn), [turbinenreiter](https://github.com/turbinenreiter)) |
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| :earth_africa: [neorv32-examples](https://github.com/emb4fun/neorv32-examples) | Intel Quartus Prime | Different Terasic boards | Different Intel FPGAs | [emb4fun](https://github.com/emb4fun) |
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## Setups using Open-Source Toolchains
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| Setup | Toolchain | Board :books: | FPGA | Author(s) |
|
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|:------|:----------|:--------------|:------|:----------|
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| :file_folder: [`UPduino v3`](https://github.com/stnolting/neorv32/tree/master/setups/osflow) | GHDL, Yosys, nextPNR | [UPduino v3.0](https://www.tindie.com/products/tinyvision_ai/upduino-v30-low-cost-lattice-ice40-fpga-board/) | Lattice iCE40 UltraPlus `iCE40UP5K-SG48I` | [tmeissner](https://github.com/tmeissner) |
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| :file_folder: [`FOMU`](https://github.com/stnolting/neorv32/tree/master/setups/osflow) | GHDL, Yosys, nextPNR | [FOMU](https://tomu.im/fomu.html) | Lattice iCE40 UltraPlus `iCE40UP5K-SG48I` | [umarcor](https://github.com/umarcor) |
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| :file_folder: [`iCESugar`](https://github.com/stnolting/neorv32/tree/master/setups/osflow) | GHDL, Yosys, nextPNR | [iCESugar](https://github.com/wuxx/icesugar/blob/master/README_en.md) | Lattice iCE40 UltraPlus `iCE40UP5K-SG48I` | [umarcor](https://github.com/umarcor) |
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| :file_folder: [`AlhambraII`](https://github.com/stnolting/neorv32/tree/master/setups/osflow) | GHDL, Yosys, nextPNR | [AlhambraII](https://alhambrabits.com/alhambra/) | Lattice iCE40HX4K | [zipotron](https://github.com/zipotron) |
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| :file_folder: [`Orange Crab`](https://github.com/stnolting/neorv32/tree/master/setups/osflow) | GHDL, Yosys, nextPNR | [Orange Crab](https://github.com/gregdavill/OrangeCrab) | Lattice ECP5-25F | [umarcor](https://github.com/umarcor), [jeremyherbert](https://github.com/jeremyherbert) |
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| :file_folder: [`ULX3S`](https://github.com/stnolting/neorv32/tree/master/setups/osflow) | GHDL, Yosys, nextPNR | [ULX3S](https://radiona.org/ulx3s/) | Lattice ECP5 `LFE5U-85F-6BG381C` | [zipotron](https://github.com/zipotron) |
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| :earth_africa: [`ULX3S-SDRAM`](https://github.com/zipotron/neorv32-complex-setups) | GHDL, Yosys, nextPNR | [ULX3S](https://radiona.org/ulx3s/) | Lattice ECP5 `LFE5U-85F-6BG381C` | [zipotron](https://github.com/zipotron) |
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:information_source: All setups using open-source toolchains are located in the
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[`osflow`](https://github.com/stnolting/neorv32/tree/master/setups/osflow) folder.
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See the README there for more information how to run a specific setup / configuration.
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## Adding Your Project Setup
|
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|
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Please respect the following guidelines if you'd like to add (or link) your setup to the list.
|
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|
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* check out the project's [code of conduct](https://github.com/stnolting/neorv32/tree/master/CODE_OF_CONDUCT.md)
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* add a link if the board you are using provides online documentation (and/or can be purchased somewhere)
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* use the :file_folder: emoji (`:file_folder:`) if the setup is located *in this* folder; use the :earth_africa:
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emoji (`:earth_africa:`) if it is a link to your local project
|
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* please add a `README` to give some brief information about the setup and a `.gitignore` to keep things clean;
|
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take a look at [`UPduino_v3`](https://github.com/stnolting/neorv32/tree/master/setups/radiant/UPduino_v3) to get some ideas what a project setup might look like
|
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## Setup-Specific NEORV32 Software Framework Modification
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|
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In order to use the features provided by the setups, minor *optional* changes can be made to the default NEORV32 setup.
|
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|
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* To change the default data memory size take a look at the :books: User Guide section
|
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[_General Software Framework Setup_](https://stnolting.github.io/neorv32/ug/#_general_software_framework_setup)
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* To modify the SPI flash base address for storing/booting software application see :books: User Guide section
|
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[_Customizing the Internal Bootloader_](https://stnolting.github.io/neorv32/ug/#_customizing_the_internal_bootloader)
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8
Libs/RiscV/NEORV32/setups/osflow/.gitignore
vendored
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8
Libs/RiscV/NEORV32/setups/osflow/.gitignore
vendored
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@ -0,0 +1,8 @@
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*.asc
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*.bit
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*.cfg
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*.dfu
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*.history
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*.json
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*.svf
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*-report.txt
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134
Libs/RiscV/NEORV32/setups/osflow/Makefile
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134
Libs/RiscV/NEORV32/setups/osflow/Makefile
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TEMPLATES := ../../rtl/processor_templates
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MV := mv
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.DEFAULT_GOAL := help
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TASK := clean $(BITSTREAM)
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FOMU_REV ?= pvt
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OrangeCrab_REV ?= r02-25F
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UPduino_REV ?= v3
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#ifndef BOARD
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#$(error BOARD needs to be set to 'Fomu', 'iCESugar', 'UPDuino', 'iCEBreaker' or 'OrangeCrab' !)
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#endif
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run:
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$(eval TASK ?= clean $(BITSTREAM))
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$(MAKE) -f common.mk \
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BOARD_SRC=./board_tops/neorv32_$(BOARD)_BoardTop_$(DESIGN).vhd \
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TOP=neorv32_$(BOARD)_BoardTop_$(DESIGN) \
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ID=$(DESIGN) \
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$(TASK)
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IMPL="$${BITSTREAM%%.*}"; for item in ".bit" ".svf"; do \
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if [ -f "./$$IMPL$$item" ]; then \
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$(MV) "./$$IMPL$$item" ./; \
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fi \
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done
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# Boards
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Fomu:
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$(eval BITSTREAM ?= neorv32_$(BOARD)_$(FOMU_REV)_$(DESIGN).bit)
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ifeq ($(DESIGN),Minimal)
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$(eval IMEM_SRC := ../../rtl/core/mem/neorv32_imem.default.vhd)
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else
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$(eval IMEM_SRC := devices/ice40/neorv32_imem.ice40up_spram.vhd)
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endif
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$(eval NEORV32_MEM_SRC ?= ${IMEM_SRC} devices/ice40/neorv32_dmem.ice40up_spram.vhd)
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$(MAKE) \
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BITSTREAM="$(BITSTREAM)" \
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NEORV32_MEM_SRC="$(NEORV32_MEM_SRC)" \
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run
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iCESugar:
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$(eval BITSTREAM ?= neorv32_$(BOARD)_$(DESIGN).bit)
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$(eval NEORV32_MEM_SRC ?= devices/ice40/neorv32_imem.ice40up_spram.vhd devices/ice40/neorv32_dmem.ice40up_spram.vhd)
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$(MAKE) \
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BITSTREAM="$(BITSTREAM)" \
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NEORV32_MEM_SRC="$(NEORV32_MEM_SRC)" \
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run
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UPduino:
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$(eval BITSTREAM ?= neorv32_$(BOARD)_$(UPduino_REV)_$(DESIGN).bit)
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$(eval NEORV32_MEM_SRC ?= devices/ice40/neorv32_imem.ice40up_spram.vhd devices/ice40/neorv32_dmem.ice40up_spram.vhd)
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$(MAKE) \
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BITSTREAM="$(BITSTREAM)" \
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NEORV32_MEM_SRC="$(NEORV32_MEM_SRC)" \
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run
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OrangeCrab:
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$(eval BITSTREAM ?= neorv32_$(BOARD)_$(OrangeCrab_REV)_$(DESIGN).bit)
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$(eval NEORV32_MEM_SRC ?= ../../rtl/core/mem/neorv32_imem.default.vhd ../../rtl/core/mem/neorv32_dmem.default.vhd)
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$(MAKE) \
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BITSTREAM="$(BITSTREAM)" \
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NEORV32_MEM_SRC="$(NEORV32_MEM_SRC)" \
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run
|
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AlhambraII:
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$(eval BITSTREAM ?= neorv32_$(BOARD)_$(DESIGN).bit)
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$(eval NEORV32_MEM_SRC ?= ../../rtl/core/mem/neorv32_imem.default.vhd ../../rtl/core/mem/neorv32_dmem.default.vhd)
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$(MAKE) \
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BITSTREAM="$(BITSTREAM)" \
|
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NEORV32_MEM_SRC="$(NEORV32_MEM_SRC)" \
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run
|
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|
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ULX3S:
|
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$(eval BITSTREAM ?= neorv32_$(BOARD)_$(DESIGN).bit)
|
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$(eval NEORV32_MEM_SRC ?= ../../rtl/core/mem/neorv32_imem.default.vhd ../../rtl/core/mem/neorv32_dmem.default.vhd)
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$(MAKE) \
|
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BITSTREAM="$(BITSTREAM)" \
|
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NEORV32_MEM_SRC="$(NEORV32_MEM_SRC)" \
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run
|
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|
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iCEBreaker:
|
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$(eval BITSTREAM ?= neorv32_$(BOARD)_$(DESIGN).bit)
|
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$(eval NEORV32_MEM_SRC ?= devices/ice40/neorv32_imem.ice40up_spram.vhd devices/ice40/neorv32_dmem.ice40up_spram.vhd)
|
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$(MAKE) \
|
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BITSTREAM="$(BITSTREAM)" \
|
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NEORV32_MEM_SRC="$(NEORV32_MEM_SRC)" \
|
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run
|
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|
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# Designs
|
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|
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Minimal:
|
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$(eval DESIGN ?= $@)
|
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$(eval DESIGN_SRC ?= $(TEMPLATES)/neorv32_ProcessorTop_Minimal*.vhd)
|
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$(MAKE) \
|
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DESIGN="$(DESIGN)" \
|
||||
DESIGN_SRC="$(DESIGN_SRC)" \
|
||||
$(BOARD)
|
||||
|
||||
MinimalBoot:
|
||||
$(eval DESIGN ?= $@)
|
||||
$(eval DESIGN_SRC ?= $(TEMPLATES)/neorv32_ProcessorTop_MinimalBoot.vhd)
|
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$(MAKE) \
|
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DESIGN="$(DESIGN)" \
|
||||
DESIGN_SRC="$(DESIGN_SRC)" \
|
||||
$(BOARD)
|
||||
|
||||
UP5KDemo:
|
||||
$(eval DESIGN ?= $@)
|
||||
$(eval DESIGN_SRC ?= $(TEMPLATES)/neorv32_ProcessorTop_UP5KDemo.vhd)
|
||||
$(MAKE) \
|
||||
DESIGN="$(DESIGN)" \
|
||||
DESIGN_SRC="$(DESIGN_SRC)" \
|
||||
$(BOARD)
|
||||
|
||||
MixedLanguage:
|
||||
$(eval DESIGN ?= $@)
|
||||
$(eval DESIGN_SRC ?= $(TEMPLATES)/neorv32_ProcessorTop_Minimal*.vhd)
|
||||
$(eval NEORV32_VERILOG_SRC ?= devices/ice40/sb_ice40_components.v board_tops/neorv32_Fomu_MixedLanguage_ClkGen.v)
|
||||
$(MAKE) \
|
||||
DESIGN="$(DESIGN)" \
|
||||
DESIGN_SRC="$(DESIGN_SRC)" \
|
||||
NEORV32_VERILOG_SRC="$(NEORV32_VERILOG_SRC)" \
|
||||
$(BOARD)
|
||||
|
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# Help
|
||||
|
||||
help:
|
||||
@echo "Open-Source Synthesis, P&R, Routing and Bitstream Generation"
|
||||
@echo "Usage: make BOARD=<fpga board> <board top>"
|
||||
@echo "Example: make BOARD=Fomu Minimal"
|
||||
|
||||
14
Libs/RiscV/NEORV32/setups/osflow/PnR_Bit.mk
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14
Libs/RiscV/NEORV32/setups/osflow/PnR_Bit.mk
Normal file
@ -0,0 +1,14 @@
|
||||
${IMPL}.${PNR2BIT_EXT}: $(IMPL).json $(CONSTRAINTS)
|
||||
$(NEXTPNR) \
|
||||
$(PNRFLAGS) \
|
||||
--$(CONSTRAINTS_FORMAT) $(CONSTRAINTS) \
|
||||
--json $(IMPL).json \
|
||||
--${NEXTPNR_OUT} $@ 2>&1 | tee nextpnr-report.txt
|
||||
|
||||
${IMPL}.bit: ${IMPL}.${PNR2BIT_EXT}
|
||||
$(PACKTOOL) $< $@
|
||||
|
||||
ifeq ($(DEVICE_SERIES),ecp5)
|
||||
${IMPL}.svf: ${IMPL}.${PNR2BIT_EXT}
|
||||
$(PACKTOOL) $(PACKARGS) --svf $@ $<
|
||||
endif
|
||||
145
Libs/RiscV/NEORV32/setups/osflow/README.md
Normal file
145
Libs/RiscV/NEORV32/setups/osflow/README.md
Normal file
@ -0,0 +1,145 @@
|
||||
# Exemplary FPAG Board Setups - Using Open Source Toolchains
|
||||
|
||||
* [Folder Structure](#Folder-Structure)
|
||||
* [Prerequisites](#Prerequisites)
|
||||
* [How To Run](#How-To-Run)
|
||||
* [Porting to a new FPGA or Board](#Porting-to-a-new-FPGA-or-Board)
|
||||
|
||||
This folder provides the infrastructure for generating bitstream for various FPGAs using
|
||||
open-source toolchains. Synthesis is based on [ghdl-yosys](https://github.com/ghdl/ghdl-yosys-plugin).
|
||||
|
||||
:information_source: Note that the provided setups just implement very basic SoC configurations.
|
||||
These setups are intended as minimal example (how to synthesize the processor) for a given FPGA + board
|
||||
that can be used as starting point to build more complex user-defined SoCs.
|
||||
|
||||
## Folder Structure
|
||||
|
||||
* `.`: Main makefile (main entry point) and partial-makefiles for synthesis, place & route and bitstream generation
|
||||
* `boards`: board-specific _partial makefiles_ (used by main makefile "`Makefile`") for generating bitstreams
|
||||
* `board_top`: board-specific top entities (board wrappers; may include FPGA-specific modules)
|
||||
* `constraints`: physical constraints (mainly pin mappings)
|
||||
* `devices`: FPGA-specific primitives and optimized processor modules (like memories)
|
||||
|
||||
|
||||
## Prerequisites
|
||||
|
||||
:construction: TODO :construction:
|
||||
|
||||
* local installation of the tools
|
||||
* using containers
|
||||
|
||||
|
||||
## How To Run
|
||||
|
||||
:construction: TODO :construction:
|
||||
|
||||
The `Makefile` in this folder is the main entry point. To run the whole process of synthesis, place & route and bitstream
|
||||
generation run:
|
||||
|
||||
**Prototype:**
|
||||
```
|
||||
make BOARD=<FPGA_board> <System_Top_HDL>
|
||||
```
|
||||
|
||||
**Example:**
|
||||
```
|
||||
make BOARD=Fomu Minimal
|
||||
```
|
||||
|
||||
`<FPGA_board>` specifies the actual FPGA board and implicitly sets the FPGA type. The currently supported FPGA board
|
||||
targets are listed in the `boards/` folder where each partial-makefile corresponds to a supported platform.
|
||||
|
||||
`<System_Top_HDL>` is used to define the actual SoC top. Available SoCs are located in
|
||||
[`rtl/processor_templates`](https://github.com/stnolting/neorv32/tree/master/rtl/processor_templates).
|
||||
|
||||
|
||||
## Porting to a new FPGA or Board
|
||||
|
||||
This sections illustrates how to add a new basic setup for a specific FPGA and board. This tutorial used the iCEBreaker
|
||||
"MinimalBoot" setup as reference.
|
||||
|
||||
#### 1. Setup a board- and FPGA-specific top entity
|
||||
|
||||
1. Write a new top design unit that instantiates one of the provided processor templates from
|
||||
[`rtl/processor_templates`](https://github.com/stnolting/neorv32/tree/master/rtl/processor_templates).
|
||||
This new top unit can be a Verilog or VHDL file.
|
||||
2. _Optional:_ You can also include FPGA-specific primitives like PLLs or block RAMs (but keep it simple). These components
|
||||
need to be added to a FPGA-specific library in [`setups/osflow/devices`](https://github.com/stnolting/neorv32/tree/master/setups/osflow/devices).
|
||||
3. Try to keep the external IO at a minimum even if the targeted FPGA boards provides cool features. Besides of clock and reset
|
||||
you need to add at least one kind of IO interface like a UART, GPIO or PWM.
|
||||
4. Give your new top entity file a specific name that includes the board's name and the instantiated processor template.
|
||||
The name scheme is `neorv32_[board-name]_BoardTop_[template-name].[v/vhd]`.
|
||||
5. Put this file in `setups/osflow/board_tops`.
|
||||
6. Take a look at the iCEBreaker MinimalBoot top entity as a reference:
|
||||
[`setups/osflow/board_tops/neorv32_iCEBreaker_BoardTop_MinimalBoot.vhd`](https://github.com/stnolting/neorv32/blob/master/setups/osflow/board_tops/neorv32_iCEBreaker_BoardTop_MinimalBoot.vhd)
|
||||
|
||||
#### 2. Pin mapping
|
||||
|
||||
1. Add a new constraints file to define the mapping between the your top unit's IO and the FPGA's physical pins.
|
||||
You can add _all_ of the FPGA's physical pins even though just a subset is used by the new setup.
|
||||
2. Name the new constraints file according to the board `[board-name].pcf`.
|
||||
3. Put this file in `setups/osflow/constraints`.
|
||||
4. Take a look at the iCEBreaker pin mapping as a reference:
|
||||
[`setups/osflow/constraints/iCEBreaker.pcf`](https://github.com/stnolting/neorv32/blob/master/setups/osflow/constraints/iCEBreaker.pcf)
|
||||
|
||||
#### 3. Adding a board-specific makefile
|
||||
|
||||
1. Add a board-specific makefile to the `setups/osflow/boards` folder. Name the new constraints file according to the board `[board-name].mk`.
|
||||
2. The makefile contains (at least) one target to build the final bitstream:
|
||||
```makefile
|
||||
.PHONY: all
|
||||
|
||||
all: bit
|
||||
echo "! Built $(IMPL) for $(BOARD)"
|
||||
```
|
||||
3. Take a look at the iCEBreaker pin mapping as a reference:
|
||||
[` setups/osflow/boards/iCEBreaker.mk`](https://github.com/stnolting/neorv32/blob/master/setups/osflow/boards/iCEBreaker.mk)
|
||||
|
||||
#### 4. Adding a new target to `index.mk`
|
||||
|
||||
1. Add a new conditional section to the boards management makefile `setups/osflow/boards/index.mk`.
|
||||
2. This board-specific section sets variables that are required to run synthesis, mapping, place & route and bitstream generation:
|
||||
* `CONSTRAINTS` defines the physical pin mapping file
|
||||
* `PNRFLAGS` defines the FPGA-specific flags for mapping and place & route
|
||||
* `IMPL` defines the setup's implementation name
|
||||
```makefile
|
||||
ifeq ($(BOARD),iCEBreaker)
|
||||
$(info Setting constraints and implementation args for BOARD iCEBreaker)
|
||||
|
||||
CONSTRAINTS ?= $(PCF_PATH)/$(BOARD).pcf
|
||||
PNRFLAGS ?= --up5k --package sg48 --ignore-loops --timing-allow-fail
|
||||
IMPL ?= neorv32_$(BOARD)_$(ID)
|
||||
|
||||
endif
|
||||
```
|
||||
|
||||
#### 5. Adding a new target to the main makefile
|
||||
|
||||
1. As final step add the new setup to the main osflow makefile `setups/osflow/Makefile`.
|
||||
2. Use the board's name to create a new makefile target.
|
||||
* The new target should set the final bitstream's name using the `BITSTREAM` variable.
|
||||
* Alternative _memory_ HDL sources like FPGA-optimized module can be set using the `NEORV32_MEM_SRC` variable.
|
||||
```makefile
|
||||
iCEBreaker:
|
||||
$(eval BITSTREAM ?= neorv32_$(BOARD)_$(DESIGN).bit)
|
||||
$(eval NEORV32_MEM_SRC ?= devices/ice40/neorv32_imem.ice40up_spram.vhd devices/ice40/neorv32_dmem.ice40up_spram.vhd)
|
||||
$(MAKE) \
|
||||
BITSTREAM="$(BITSTREAM)" \
|
||||
NEORV32_MEM_SRC="$(NEORV32_MEM_SRC)" \
|
||||
run
|
||||
```
|
||||
|
||||
#### 6. _Optional:_ Add the new setup to the automatic "Implementation" github workflow
|
||||
|
||||
If you like you can add the new setup to the automatic build environment of the project. The project's "Implementation"
|
||||
workflow will generate bitstreams for all configured osflow setups on every repository push. This is used to check for
|
||||
regressions and also to provide up-to-date bitstreams that can be used right away.
|
||||
|
||||
1. Add the new setup to the job matrix file `.github/generate-job-matrix.py`.
|
||||
```python
|
||||
{
|
||||
'board': 'iCEBreaker',
|
||||
'design': 'MinimalBoot',
|
||||
'bitstream': 'neorv32_iCEBreaker_MinimalBoot.bit'
|
||||
},
|
||||
```
|
||||
@ -0,0 +1,128 @@
|
||||
-- #################################################################################################
|
||||
-- # << NEORV32 - Example setup including the bootloader, for the AlhambraII (c) Board >> #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # BSD 3-Clause License #
|
||||
-- # #
|
||||
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
|
||||
-- # #
|
||||
-- # Redistribution and use in source and binary forms, with or without modification, are #
|
||||
-- # permitted provided that the following conditions are met: #
|
||||
-- # #
|
||||
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
|
||||
-- # conditions and the following disclaimer. #
|
||||
-- # #
|
||||
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
|
||||
-- # conditions and the following disclaimer in the documentation and/or other materials #
|
||||
-- # provided with the distribution. #
|
||||
-- # #
|
||||
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
|
||||
-- # endorse or promote products derived from this software without specific prior written #
|
||||
-- # permission. #
|
||||
-- # #
|
||||
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
|
||||
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
|
||||
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
|
||||
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
|
||||
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
|
||||
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
|
||||
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
|
||||
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
|
||||
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
|
||||
-- #################################################################################################
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library iCE40;
|
||||
use iCE40.components.all; -- for device primitives and macros
|
||||
|
||||
entity neorv32_AlhambraII_BoardTop_MinimalBoot is
|
||||
port (
|
||||
-- external clock (12 MHz)
|
||||
AlhambraII_CLK : in std_logic;
|
||||
-- LED outputs
|
||||
AlhambraII_LED0 : out std_logic;
|
||||
AlhambraII_LED1 : out std_logic;
|
||||
AlhambraII_LED2 : out std_logic;
|
||||
AlhambraII_LED3 : out std_logic;
|
||||
AlhambraII_LED4 : out std_logic;
|
||||
AlhambraII_LED5 : out std_logic;
|
||||
AlhambraII_LED6 : out std_logic;
|
||||
AlhambraII_LED7 : out std_logic;
|
||||
-- UART0
|
||||
AlhambraII_RX : in std_logic;
|
||||
AlhambraII_TX : out std_logic
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture neorv32_AlhambraII_BoardTop_MinimalBoot_rtl of neorv32_AlhambraII_BoardTop_MinimalBoot is
|
||||
|
||||
-- configuration --
|
||||
constant f_clock_c : natural := 12000000; -- clock frequency in Hz
|
||||
|
||||
-- reset generator --
|
||||
signal rst_cnt : std_logic_vector(8 downto 0) := (others => '0'); -- initialized by bitstream
|
||||
signal sys_rstn : std_logic;
|
||||
|
||||
-- internal IO connection --
|
||||
signal con_gpio_o : std_ulogic_vector(3 downto 0);
|
||||
signal con_pwm : std_logic_vector(2 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
-- Reset Generator ------------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
reset_generator: process(AlhambraII_CLK)
|
||||
begin
|
||||
if rising_edge(AlhambraII_CLK) then
|
||||
if (rst_cnt(rst_cnt'left) = '0') then
|
||||
rst_cnt <= std_logic_vector(unsigned(rst_cnt) + 1);
|
||||
end if;
|
||||
end if;
|
||||
end process reset_generator;
|
||||
|
||||
sys_rstn <= rst_cnt(rst_cnt'left);
|
||||
|
||||
|
||||
-- The core of the problem ----------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot
|
||||
generic map (
|
||||
CLOCK_FREQUENCY => f_clock_c, -- clock frequency of clk_i in Hz
|
||||
MEM_INT_IMEM_SIZE => 4*1024, -- size of processor-internal instruction memory in bytes
|
||||
MEM_INT_DMEM_SIZE => 2*1024 -- size of processor-internal data memory in bytes
|
||||
)
|
||||
port map (
|
||||
-- Global control --
|
||||
clk_i => std_ulogic(AlhambraII_CLK),
|
||||
rstn_i => std_ulogic(sys_rstn),
|
||||
|
||||
-- GPIO --
|
||||
gpio_o => con_gpio_o,
|
||||
|
||||
-- primary UART --
|
||||
uart_txd_o => AlhambraII_TX, -- UART0 send data
|
||||
uart_rxd_i => AlhambraII_RX, -- UART0 receive data
|
||||
uart_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
|
||||
uart_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional
|
||||
|
||||
-- PWM (to on-board RGB LED) --
|
||||
pwm_o => con_pwm
|
||||
);
|
||||
|
||||
-- IO Connection --------------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
AlhambraII_LED0 <= con_gpio_o(0);
|
||||
AlhambraII_LED1 <= con_gpio_o(1);
|
||||
AlhambraII_LED2 <= con_gpio_o(2);
|
||||
AlhambraII_LED3 <= con_gpio_o(3);
|
||||
AlhambraII_LED4 <= '0'; -- unused
|
||||
AlhambraII_LED5 <= con_pwm(0);
|
||||
AlhambraII_LED6 <= con_pwm(1);
|
||||
AlhambraII_LED7 <= con_pwm(2);
|
||||
|
||||
|
||||
end architecture;
|
||||
@ -0,0 +1,149 @@
|
||||
-- #################################################################################################
|
||||
-- # << NEORV32 - Example minimal setup for the Fomu (c) Board >> #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # BSD 3-Clause License #
|
||||
-- # #
|
||||
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
|
||||
-- # #
|
||||
-- # Redistribution and use in source and binary forms, with or without modification, are #
|
||||
-- # permitted provided that the following conditions are met: #
|
||||
-- # #
|
||||
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
|
||||
-- # conditions and the following disclaimer. #
|
||||
-- # #
|
||||
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
|
||||
-- # conditions and the following disclaimer in the documentation and/or other materials #
|
||||
-- # provided with the distribution. #
|
||||
-- # #
|
||||
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
|
||||
-- # endorse or promote products derived from this software without specific prior written #
|
||||
-- # permission. #
|
||||
-- # #
|
||||
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
|
||||
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
|
||||
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
|
||||
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
|
||||
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
|
||||
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
|
||||
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
|
||||
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
|
||||
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
|
||||
-- #################################################################################################
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library iCE40;
|
||||
use iCE40.components.all; -- for device primitives and macros
|
||||
|
||||
entity neorv32_Fomu_BoardTop_Minimal is
|
||||
port (
|
||||
-- 48MHz Clock input
|
||||
clki : in std_logic;
|
||||
-- LED outputs
|
||||
rgb : out std_logic_vector(2 downto 0);
|
||||
-- USB Pins (which should be statically driven if not being used)
|
||||
usb_dp : out std_logic;
|
||||
usb_dn : out std_logic;
|
||||
usb_dp_pu : out std_logic
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture neorv32_Fomu_BoardTop_Minimal_rtl of neorv32_Fomu_BoardTop_Minimal is
|
||||
|
||||
-- configuration --
|
||||
constant f_clock_c : natural := 22000000; -- PLL output clock frequency in Hz
|
||||
|
||||
-- Globals
|
||||
signal pll_rstn : std_logic;
|
||||
signal pll_clk : std_logic;
|
||||
|
||||
-- internal IO connection --
|
||||
signal con_pwm : std_logic_vector(2 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
-- Assign USB pins to "0" so as to disconnect Fomu from
|
||||
-- the host system. Otherwise it would try to talk to
|
||||
-- us over USB, which wouldn't work since we have no stack.
|
||||
usb_dp <= '0';
|
||||
usb_dn <= '0';
|
||||
usb_dp_pu <= '0';
|
||||
|
||||
-- System PLL -----------------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
-- Settings generated by icepll -i 48 -o 21:
|
||||
-- F_PLLIN: 48.000 MHz (given)
|
||||
-- F_PLLOUT: 22.000 MHz (requested)
|
||||
-- F_PLLOUT: 22.000 MHz (achieved)
|
||||
-- FEEDBACK: SIMPLE
|
||||
-- F_PFD: 16.000 MHz
|
||||
-- F_VCO: 704.000 MHz
|
||||
-- DIVR: 2 (4'b0010)
|
||||
-- DIVF: 43 (7'b0101011)
|
||||
-- DIVQ: 5 (3'b101)
|
||||
-- FILTER_RANGE: 1 (3'b001)
|
||||
Pll_inst : SB_PLL40_CORE
|
||||
generic map (
|
||||
FEEDBACK_PATH => "SIMPLE",
|
||||
DIVR => x"2",
|
||||
DIVF => 7x"2B",
|
||||
DIVQ => 3x"5",
|
||||
FILTER_RANGE => 3x"1"
|
||||
)
|
||||
port map (
|
||||
REFERENCECLK => clki,
|
||||
PLLOUTCORE => open,
|
||||
PLLOUTGLOBAL => pll_clk,
|
||||
EXTFEEDBACK => '0',
|
||||
DYNAMICDELAY => x"00",
|
||||
LOCK => pll_rstn,
|
||||
BYPASS => '0',
|
||||
RESETB => '1',
|
||||
LATCHINPUTVALUE => '0',
|
||||
SDO => open,
|
||||
SDI => '0',
|
||||
SCLK => '0'
|
||||
);
|
||||
|
||||
-- The core of the problem ----------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
|
||||
neorv32_inst: entity work.neorv32_ProcessorTop_Minimal
|
||||
generic map (
|
||||
CLOCK_FREQUENCY => f_clock_c -- clock frequency of clk_i in Hz
|
||||
)
|
||||
port map (
|
||||
-- Global control --
|
||||
clk_i => std_ulogic(pll_clk),
|
||||
rstn_i => std_ulogic(pll_rstn),
|
||||
|
||||
-- PWM (to on-board RGB LED) --
|
||||
pwm_o => con_pwm
|
||||
);
|
||||
|
||||
-- IO Connection --------------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
|
||||
RGB_inst: SB_RGBA_DRV
|
||||
generic map (
|
||||
CURRENT_MODE => "0b1",
|
||||
RGB0_CURRENT => "0b000011",
|
||||
RGB1_CURRENT => "0b000011",
|
||||
RGB2_CURRENT => "0b000011"
|
||||
)
|
||||
port map (
|
||||
CURREN => '1', -- I
|
||||
RGBLEDEN => '1', -- I
|
||||
RGB2PWM => con_pwm(2), -- I - blue - pwm channel 2
|
||||
RGB1PWM => con_pwm(1), -- I - red - pwm channel 1 || BOOT blink
|
||||
RGB0PWM => con_pwm(0), -- I - green - pwm channel 0
|
||||
RGB2 => rgb(2), -- O - blue
|
||||
RGB1 => rgb(1), -- O - red
|
||||
RGB0 => rgb(0) -- O - green
|
||||
);
|
||||
|
||||
end architecture;
|
||||
@ -0,0 +1,174 @@
|
||||
-- #################################################################################################
|
||||
-- # << NEORV32 - Example setup including the bootloader, for the Fomu (c) Board >> #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # BSD 3-Clause License #
|
||||
-- # #
|
||||
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
|
||||
-- # #
|
||||
-- # Redistribution and use in source and binary forms, with or without modification, are #
|
||||
-- # permitted provided that the following conditions are met: #
|
||||
-- # #
|
||||
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
|
||||
-- # conditions and the following disclaimer. #
|
||||
-- # #
|
||||
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
|
||||
-- # conditions and the following disclaimer in the documentation and/or other materials #
|
||||
-- # provided with the distribution. #
|
||||
-- # #
|
||||
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
|
||||
-- # endorse or promote products derived from this software without specific prior written #
|
||||
-- # permission. #
|
||||
-- # #
|
||||
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
|
||||
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
|
||||
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
|
||||
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
|
||||
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
|
||||
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
|
||||
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
|
||||
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
|
||||
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
|
||||
-- #################################################################################################
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library iCE40;
|
||||
use iCE40.components.all; -- for device primitives and macros
|
||||
|
||||
entity neorv32_Fomu_BoardTop_MinimalBoot is
|
||||
port (
|
||||
-- 48MHz Clock input
|
||||
clki : in std_logic;
|
||||
-- LED outputs
|
||||
rgb : out std_logic_vector(2 downto 0);
|
||||
-- USB Pins (which should be statically driven if not being used)
|
||||
usb_dp : out std_logic;
|
||||
usb_dn : out std_logic;
|
||||
usb_dp_pu : out std_logic
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture neorv32_Fomu_BoardTop_MinimalBoot_rtl of neorv32_Fomu_BoardTop_MinimalBoot is
|
||||
|
||||
-- configuration --
|
||||
constant f_clock_c : natural := 18000000; -- PLL output clock frequency in Hz
|
||||
|
||||
-- On-chip oscillator --
|
||||
signal hf_osc_clk : std_logic;
|
||||
|
||||
-- Globals
|
||||
signal pll_rstn : std_logic;
|
||||
signal pll_clk : std_logic;
|
||||
|
||||
-- internal IO connection --
|
||||
signal con_gpio_o : std_ulogic_vector(3 downto 0);
|
||||
signal con_pwm : std_logic_vector(2 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
-- Assign USB pins to "0" so as to disconnect Fomu from
|
||||
-- the host system. Otherwise it would try to talk to
|
||||
-- us over USB, which wouldn't work since we have no stack.
|
||||
usb_dp <= '0';
|
||||
usb_dn <= '0';
|
||||
usb_dp_pu <= '0';
|
||||
|
||||
-- On-Chip HF Oscillator ------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
HSOSC_inst : SB_HFOSC
|
||||
generic map (
|
||||
CLKHF_DIV => "0b10" -- 12 MHz
|
||||
)
|
||||
port map (
|
||||
CLKHFPU => '1',
|
||||
CLKHFEN => '1',
|
||||
CLKHF => hf_osc_clk
|
||||
);
|
||||
|
||||
-- System PLL -----------------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
-- Settings generated by icepll -i 12 -o 18:
|
||||
-- F_PLLIN: 12.000 MHz (given)
|
||||
-- F_PLLOUT: 18.000 MHz (requested)
|
||||
-- F_PLLOUT: 18.000 MHz (achieved)
|
||||
-- FEEDBACK: SIMPLE
|
||||
-- F_PFD: 12.000 MHz
|
||||
-- F_VCO: 576.000 MHz
|
||||
-- DIVR: 0 (4'b0000)
|
||||
-- DIVF: 47 (7'b0101111)
|
||||
-- DIVQ: 5 (3'b101)
|
||||
-- FILTER_RANGE: 1 (3'b001)
|
||||
Pll_inst : SB_PLL40_CORE
|
||||
generic map (
|
||||
FEEDBACK_PATH => "SIMPLE",
|
||||
DIVR => x"0",
|
||||
DIVF => 7x"2F",
|
||||
DIVQ => 3x"5",
|
||||
FILTER_RANGE => 3x"1"
|
||||
)
|
||||
port map (
|
||||
REFERENCECLK => hf_osc_clk,
|
||||
PLLOUTCORE => open,
|
||||
PLLOUTGLOBAL => pll_clk,
|
||||
EXTFEEDBACK => '0',
|
||||
DYNAMICDELAY => x"00",
|
||||
LOCK => pll_rstn,
|
||||
BYPASS => '0',
|
||||
RESETB => '1',
|
||||
LATCHINPUTVALUE => '0',
|
||||
SDO => open,
|
||||
SDI => '0',
|
||||
SCLK => '0'
|
||||
);
|
||||
|
||||
-- The core of the problem ----------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
|
||||
neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot
|
||||
generic map (
|
||||
CLOCK_FREQUENCY => f_clock_c -- clock frequency of clk_i in Hz
|
||||
)
|
||||
port map (
|
||||
-- Global control --
|
||||
clk_i => std_ulogic(pll_clk),
|
||||
rstn_i => std_ulogic(pll_rstn),
|
||||
|
||||
-- GPIO --
|
||||
gpio_o => con_gpio_o,
|
||||
|
||||
-- primary UART --
|
||||
uart_txd_o => open, -- UART0 send data
|
||||
uart_rxd_i => '0', -- UART0 receive data
|
||||
uart_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
|
||||
uart_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional
|
||||
|
||||
-- PWM (to on-board RGB LED) --
|
||||
pwm_o => con_pwm
|
||||
);
|
||||
|
||||
-- IO Connection --------------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
|
||||
RGB_inst: SB_RGBA_DRV
|
||||
generic map (
|
||||
CURRENT_MODE => "0b1",
|
||||
RGB0_CURRENT => "0b000011",
|
||||
RGB1_CURRENT => "0b000011",
|
||||
RGB2_CURRENT => "0b000011"
|
||||
)
|
||||
port map (
|
||||
CURREN => '1', -- I
|
||||
RGBLEDEN => '1', -- I
|
||||
RGB2PWM => con_pwm(2), -- I - blue - pwm channel 2
|
||||
RGB1PWM => con_pwm(1) or con_gpio_o(0), -- I - red - pwm channel 1 || BOOT blink
|
||||
RGB0PWM => con_pwm(0), -- I - green - pwm channel 0
|
||||
RGB2 => rgb(2), -- O - blue
|
||||
RGB1 => rgb(1), -- O - red
|
||||
RGB0 => rgb(0) -- O - green
|
||||
);
|
||||
|
||||
end architecture;
|
||||
@ -0,0 +1,139 @@
|
||||
-- #################################################################################################
|
||||
-- # << NEORV32 - Example setup including the bootloader, for the Fomu (c) Board >> #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # BSD 3-Clause License #
|
||||
-- # #
|
||||
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
|
||||
-- # #
|
||||
-- # Redistribution and use in source and binary forms, with or without modification, are #
|
||||
-- # permitted provided that the following conditions are met: #
|
||||
-- # #
|
||||
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
|
||||
-- # conditions and the following disclaimer. #
|
||||
-- # #
|
||||
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
|
||||
-- # conditions and the following disclaimer in the documentation and/or other materials #
|
||||
-- # provided with the distribution. #
|
||||
-- # #
|
||||
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
|
||||
-- # endorse or promote products derived from this software without specific prior written #
|
||||
-- # permission. #
|
||||
-- # #
|
||||
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
|
||||
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
|
||||
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
|
||||
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
|
||||
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
|
||||
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
|
||||
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
|
||||
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
|
||||
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
|
||||
-- #################################################################################################
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library iCE40;
|
||||
use iCE40.components.all; -- for device primitives and macros
|
||||
|
||||
entity neorv32_Fomu_BoardTop_MixedLanguage is
|
||||
port (
|
||||
-- 48MHz Clock input
|
||||
clki : in std_logic;
|
||||
-- LED outputs
|
||||
rgb : out std_logic_vector(2 downto 0);
|
||||
-- USB Pins (which should be statically driven if not being used)
|
||||
usb_dp : out std_logic;
|
||||
usb_dn : out std_logic;
|
||||
usb_dp_pu : out std_logic
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture neorv32_Fomu_BoardTop_MixedLanguage_rtl of neorv32_Fomu_BoardTop_MixedLanguage is
|
||||
|
||||
-- configuration --
|
||||
constant f_clock_c : natural := 18000000; -- PLL output clock frequency in Hz
|
||||
|
||||
component neorv32_Fomu_MixedLanguage_ClkGen
|
||||
port (
|
||||
clk_o : out std_logic;
|
||||
rstn_o : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
-- Globals
|
||||
signal pll_rstn : std_logic;
|
||||
signal pll_clk : std_logic;
|
||||
|
||||
-- internal IO connection --
|
||||
signal con_gpio_o : std_ulogic_vector(3 downto 0);
|
||||
signal con_pwm : std_logic_vector(2 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
-- Assign USB pins to "0" so as to disconnect Fomu from
|
||||
-- the host system. Otherwise it would try to talk to
|
||||
-- us over USB, which wouldn't work since we have no stack.
|
||||
usb_dp <= '0';
|
||||
usb_dn <= '0';
|
||||
usb_dp_pu <= '0';
|
||||
|
||||
-- On-Chip HF Oscillator and System PLL -----------------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
|
||||
Clk_inst : neorv32_Fomu_MixedLanguage_ClkGen
|
||||
port map (
|
||||
clk_o => pll_clk,
|
||||
rstn_o => pll_rstn
|
||||
);
|
||||
|
||||
-- The core of the problem ----------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
|
||||
neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot
|
||||
generic map (
|
||||
CLOCK_FREQUENCY => f_clock_c -- clock frequency of clk_i in Hz
|
||||
)
|
||||
port map (
|
||||
-- Global control --
|
||||
clk_i => std_ulogic(pll_clk),
|
||||
rstn_i => std_ulogic(pll_rstn),
|
||||
|
||||
-- GPIO --
|
||||
gpio_o => con_gpio_o,
|
||||
|
||||
-- primary UART --
|
||||
uart_txd_o => open, -- UART0 send data
|
||||
uart_rxd_i => '0', -- UART0 receive data
|
||||
uart_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
|
||||
uart_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional
|
||||
|
||||
-- PWM (to on-board RGB LED) --
|
||||
pwm_o => con_pwm
|
||||
);
|
||||
|
||||
-- IO Connection --------------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
|
||||
RGB_inst: SB_RGBA_DRV
|
||||
generic map (
|
||||
CURRENT_MODE => "0b1",
|
||||
RGB0_CURRENT => "0b000011",
|
||||
RGB1_CURRENT => "0b000011",
|
||||
RGB2_CURRENT => "0b000011"
|
||||
)
|
||||
port map (
|
||||
CURREN => '1', -- I
|
||||
RGBLEDEN => '1', -- I
|
||||
RGB2PWM => con_pwm(2), -- I - blue - pwm channel 2
|
||||
RGB1PWM => con_pwm(1) or con_gpio_o(0), -- I - red - pwm channel 1 || BOOT blink
|
||||
RGB0PWM => con_pwm(0), -- I - green - pwm channel 0
|
||||
RGB2 => rgb(2), -- O - blue
|
||||
RGB1 => rgb(1), -- O - red
|
||||
RGB0 => rgb(0) -- O - green
|
||||
);
|
||||
|
||||
end architecture;
|
||||
@ -0,0 +1,185 @@
|
||||
-- #################################################################################################
|
||||
-- # << NEORV32 - Example setup for the Fomu (c) Board >> #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # BSD 3-Clause License #
|
||||
-- # #
|
||||
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
|
||||
-- # #
|
||||
-- # Redistribution and use in source and binary forms, with or without modification, are #
|
||||
-- # permitted provided that the following conditions are met: #
|
||||
-- # #
|
||||
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
|
||||
-- # conditions and the following disclaimer. #
|
||||
-- # #
|
||||
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
|
||||
-- # conditions and the following disclaimer in the documentation and/or other materials #
|
||||
-- # provided with the distribution. #
|
||||
-- # #
|
||||
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
|
||||
-- # endorse or promote products derived from this software without specific prior written #
|
||||
-- # permission. #
|
||||
-- # #
|
||||
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
|
||||
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
|
||||
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
|
||||
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
|
||||
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
|
||||
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
|
||||
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
|
||||
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
|
||||
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
|
||||
-- #################################################################################################
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library iCE40;
|
||||
use iCE40.components.all; -- for device primitives and macros
|
||||
|
||||
entity neorv32_Fomu_BoardTop_UP5KDemo is
|
||||
port (
|
||||
-- 48MHz Clock input
|
||||
clki : in std_logic;
|
||||
-- LED outputs
|
||||
rgb : out std_logic_vector(2 downto 0);
|
||||
-- USB Pins (which should be statically driven if not being used)
|
||||
usb_dp : out std_logic;
|
||||
usb_dn : out std_logic;
|
||||
usb_dp_pu : out std_logic
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture neorv32_Fomu_BoardTop_UP5KDemo_rtl of neorv32_Fomu_BoardTop_UP5KDemo is
|
||||
|
||||
-- configuration --
|
||||
constant f_clock_c : natural := 18000000; -- PLL output clock frequency in Hz
|
||||
|
||||
-- On-chip oscillator --
|
||||
signal hf_osc_clk : std_logic;
|
||||
|
||||
-- Globals
|
||||
signal pll_rstn : std_logic;
|
||||
signal pll_clk : std_logic;
|
||||
|
||||
-- internal IO connection --
|
||||
signal con_pwm : std_ulogic_vector(2 downto 0);
|
||||
signal con_gpio_o : std_ulogic_vector(3 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
-- Assign USB pins to "0" so as to disconnect Fomu from
|
||||
-- the host system. Otherwise it would try to talk to
|
||||
-- us over USB, which wouldn't work since we have no stack.
|
||||
usb_dp <= '0';
|
||||
usb_dn <= '0';
|
||||
usb_dp_pu <= '0';
|
||||
|
||||
-- On-Chip HF Oscillator ------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
HSOSC_inst : SB_HFOSC
|
||||
generic map (
|
||||
CLKHF_DIV => "0b10" -- 12 MHz
|
||||
)
|
||||
port map (
|
||||
CLKHFPU => '1',
|
||||
CLKHFEN => '1',
|
||||
CLKHF => hf_osc_clk
|
||||
);
|
||||
|
||||
-- System PLL -----------------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
-- Settings generated by icepll -i 12 -o 18:
|
||||
-- F_PLLIN: 12.000 MHz (given)
|
||||
-- F_PLLOUT: 18.000 MHz (requested)
|
||||
-- F_PLLOUT: 18.000 MHz (achieved)
|
||||
-- FEEDBACK: SIMPLE
|
||||
-- F_PFD: 12.000 MHz
|
||||
-- F_VCO: 576.000 MHz
|
||||
-- DIVR: 0 (4'b0000)
|
||||
-- DIVF: 47 (7'b0101111)
|
||||
-- DIVQ: 5 (3'b101)
|
||||
-- FILTER_RANGE: 1 (3'b001)
|
||||
Pll_inst : SB_PLL40_CORE
|
||||
generic map (
|
||||
FEEDBACK_PATH => "SIMPLE",
|
||||
DIVR => x"0",
|
||||
DIVF => 7x"2F",
|
||||
DIVQ => 3x"5",
|
||||
FILTER_RANGE => 3x"1"
|
||||
)
|
||||
port map (
|
||||
REFERENCECLK => hf_osc_clk,
|
||||
PLLOUTCORE => open,
|
||||
PLLOUTGLOBAL => pll_clk,
|
||||
EXTFEEDBACK => '0',
|
||||
DYNAMICDELAY => x"00",
|
||||
LOCK => pll_rstn,
|
||||
BYPASS => '0',
|
||||
RESETB => '1',
|
||||
LATCHINPUTVALUE => '0',
|
||||
SDO => open,
|
||||
SDI => '0',
|
||||
SCLK => '0'
|
||||
);
|
||||
|
||||
-- The core of the problem ----------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
|
||||
neorv32_inst: entity work.neorv32_ProcessorTop_UP5KDemo
|
||||
generic map (
|
||||
CLOCK_FREQUENCY => f_clock_c -- clock frequency of clk_i in Hz
|
||||
)
|
||||
port map (
|
||||
-- Global control --
|
||||
clk_i => std_ulogic(pll_clk),
|
||||
rstn_i => std_ulogic(pll_rstn),
|
||||
-- primary UART --
|
||||
uart_txd_o => open,
|
||||
uart_rxd_i => '0',
|
||||
uart_rts_o => open,
|
||||
uart_cts_i => '0',
|
||||
-- SPI to on-board flash --
|
||||
flash_sck_o => open,
|
||||
flash_sdo_o => open,
|
||||
flash_sdi_i => '0',
|
||||
flash_csn_o => open,
|
||||
-- SPI to IO pins --
|
||||
spi_sck_o => open,
|
||||
spi_sdo_o => open,
|
||||
spi_sdi_i => '0',
|
||||
spi_csn_o => open,
|
||||
-- TWI --
|
||||
twi_sda_io => open,
|
||||
twi_scl_io => open,
|
||||
-- GPIO --
|
||||
gpio_i => (others=>'0'),
|
||||
gpio_o => con_gpio_o,
|
||||
-- PWM (to on-board RGB LED) --
|
||||
pwm_o => con_pwm
|
||||
);
|
||||
|
||||
-- IO Connection --------------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
|
||||
RGB_inst: SB_RGBA_DRV
|
||||
generic map (
|
||||
CURRENT_MODE => "0b1",
|
||||
RGB0_CURRENT => "0b000011",
|
||||
RGB1_CURRENT => "0b000011",
|
||||
RGB2_CURRENT => "0b000011"
|
||||
)
|
||||
port map (
|
||||
CURREN => '1', -- I
|
||||
RGBLEDEN => '1', -- I
|
||||
RGB2PWM => con_pwm(2), -- I - blue - pwm channel 2
|
||||
RGB1PWM => con_pwm(1) or con_gpio_o(0), -- I - red - pwm channel 1 || BOOT blink
|
||||
RGB0PWM => con_pwm(0), -- I - green - pwm channel 0
|
||||
RGB2 => rgb(2), -- O - blue
|
||||
RGB1 => rgb(1), -- O - red
|
||||
RGB0 => rgb(0) -- O - green
|
||||
);
|
||||
|
||||
end architecture;
|
||||
@ -0,0 +1,130 @@
|
||||
-- #################################################################################################
|
||||
-- # << NEORV32 - Example setup including the bootloader, for the OrangeCrab (c) Board >> #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # BSD 3-Clause License #
|
||||
-- # #
|
||||
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
|
||||
-- # #
|
||||
-- # Redistribution and use in source and binary forms, with or without modification, are #
|
||||
-- # permitted provided that the following conditions are met: #
|
||||
-- # #
|
||||
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
|
||||
-- # conditions and the following disclaimer. #
|
||||
-- # #
|
||||
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
|
||||
-- # conditions and the following disclaimer in the documentation and/or other materials #
|
||||
-- # provided with the distribution. #
|
||||
-- # #
|
||||
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
|
||||
-- # endorse or promote products derived from this software without specific prior written #
|
||||
-- # permission. #
|
||||
-- # #
|
||||
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
|
||||
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
|
||||
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
|
||||
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
|
||||
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
|
||||
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
|
||||
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
|
||||
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
|
||||
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
|
||||
-- #################################################################################################
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library ECP5;
|
||||
use ECP5.components.all; -- for device primitives and macros
|
||||
|
||||
entity neorv32_OrangeCrab_BoardTop_MinimalBoot is
|
||||
port (
|
||||
-- Clock and Reset inputs
|
||||
OrangeCrab_CLK : in std_logic;
|
||||
OrangeCrab_RST_N : in std_logic;
|
||||
-- LED outputs
|
||||
OrangeCrab_LED_RGB_R : out std_logic;
|
||||
OrangeCrab_LED_RGB_G : out std_logic;
|
||||
OrangeCrab_LED_RGB_B : out std_logic;
|
||||
-- UART0
|
||||
OrangeCrab_GPIO_0 : in std_logic;
|
||||
OrangeCrab_GPIO_1 : out std_logic;
|
||||
OrangeCrab_GPIO_9 : out std_logic;
|
||||
-- USB Pins (which should be statically driven if not being used)
|
||||
OrangeCrab_USB_D_P : out std_logic;
|
||||
OrangeCrab_USB_D_N : out std_logic;
|
||||
OrangeCrab_USB_DP_PU : out std_logic
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture neorv32_OrangeCrab_BoardTop_MinimalBoot_rtl of neorv32_OrangeCrab_BoardTop_MinimalBoot is
|
||||
|
||||
-- configuration --
|
||||
constant f_clock_c : natural := 24000000; -- PLL output clock frequency in Hz
|
||||
|
||||
-- Globals
|
||||
signal pll_clk: std_logic;
|
||||
|
||||
-- internal IO connection --
|
||||
signal con_pwm : std_logic_vector(2 downto 0);
|
||||
signal con_gpio_o : std_ulogic_vector(3 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
-- Assign USB pins to "0" so as to disconnect OrangeCrab from
|
||||
-- the host system. Otherwise it would try to talk to
|
||||
-- us over USB, which wouldn't work since we have no stack.
|
||||
OrangeCrab_USB_D_P <= '0';
|
||||
OrangeCrab_USB_D_N <= '0';
|
||||
OrangeCrab_USB_DP_PU <= '0';
|
||||
|
||||
-- System PLL -----------------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
PLL_inst: EHXPLLL
|
||||
generic map (
|
||||
CLKI_DIV => 2, -- from `ecppll -i 48 -o 24`
|
||||
CLKFB_DIV => 1,
|
||||
CLKOP_DIV => 25
|
||||
)
|
||||
port map (
|
||||
CLKI => OrangeCrab_CLK,
|
||||
CLKFB => pll_clk,
|
||||
ENCLKOP => '1',
|
||||
CLKOP => pll_clk,
|
||||
LOCK => OrangeCrab_GPIO_9
|
||||
);
|
||||
|
||||
-- The core of the problem ----------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
|
||||
neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot
|
||||
generic map (
|
||||
CLOCK_FREQUENCY => f_clock_c, -- clock frequency of clk_i in Hz
|
||||
MEM_INT_IMEM_SIZE => 16*1024,
|
||||
MEM_INT_DMEM_SIZE => 8*1024
|
||||
)
|
||||
port map (
|
||||
-- Global control --
|
||||
clk_i => std_ulogic(pll_clk),
|
||||
rstn_i => std_ulogic(OrangeCrab_RST_N),
|
||||
|
||||
-- GPIO --
|
||||
gpio_o => con_gpio_o,
|
||||
|
||||
-- primary UART --
|
||||
uart_txd_o => OrangeCrab_GPIO_1, -- UART0 send data
|
||||
uart_rxd_i => OrangeCrab_GPIO_0, -- UART0 receive data
|
||||
uart_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
|
||||
uart_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional
|
||||
|
||||
-- PWM (to on-board RGB LED) --
|
||||
pwm_o => con_pwm
|
||||
);
|
||||
|
||||
OrangeCrab_LED_RGB_R <= con_pwm(0) or not con_gpio_o(0);
|
||||
OrangeCrab_LED_RGB_G <= con_pwm(1);
|
||||
OrangeCrab_LED_RGB_B <= con_pwm(2);
|
||||
|
||||
end architecture;
|
||||
@ -0,0 +1,110 @@
|
||||
-- #################################################################################################
|
||||
-- # << NEORV32 - Example setup including the bootloader, for the ULX3S (c) Board >> #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # BSD 3-Clause License #
|
||||
-- # #
|
||||
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
|
||||
-- # #
|
||||
-- # Redistribution and use in source and binary forms, with or without modification, are #
|
||||
-- # permitted provided that the following conditions are met: #
|
||||
-- # #
|
||||
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
|
||||
-- # conditions and the following disclaimer. #
|
||||
-- # #
|
||||
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
|
||||
-- # conditions and the following disclaimer in the documentation and/or other materials #
|
||||
-- # provided with the distribution. #
|
||||
-- # #
|
||||
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
|
||||
-- # endorse or promote products derived from this software without specific prior written #
|
||||
-- # permission. #
|
||||
-- # #
|
||||
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
|
||||
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
|
||||
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
|
||||
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
|
||||
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
|
||||
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
|
||||
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
|
||||
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
|
||||
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
|
||||
-- #################################################################################################
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library ECP5;
|
||||
use ECP5.components.all; -- for device primitives and macros
|
||||
|
||||
entity neorv32_ULX3S_BoardTop_MinimalBoot is
|
||||
port (
|
||||
-- Clock and Reset inputs
|
||||
ULX3S_CLK : in std_logic;
|
||||
ULX3S_RST_N : in std_logic;
|
||||
-- LED outputs
|
||||
ULX3S_LED0 : out std_logic;
|
||||
ULX3S_LED1 : out std_logic;
|
||||
ULX3S_LED2 : out std_logic;
|
||||
ULX3S_LED3 : out std_logic;
|
||||
ULX3S_LED4 : out std_logic;
|
||||
ULX3S_LED5 : out std_logic;
|
||||
ULX3S_LED6 : out std_logic;
|
||||
ULX3S_LED7 : out std_logic;
|
||||
-- UART0
|
||||
ULX3S_RX : in std_logic;
|
||||
ULX3S_TX : out std_logic
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture neorv32_ULX3S_BoardTop_MinimalBoot_rtl of neorv32_ULX3S_BoardTop_MinimalBoot is
|
||||
|
||||
-- configuration --
|
||||
constant f_clock_c : natural := 25000000; -- clock frequency in Hz
|
||||
|
||||
-- internal IO connection --
|
||||
signal con_pwm : std_logic_vector(2 downto 0);
|
||||
signal con_gpio_o : std_ulogic_vector(3 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
-- The core of the problem ----------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot
|
||||
generic map (
|
||||
CLOCK_FREQUENCY => f_clock_c, -- clock frequency of clk_i in Hz
|
||||
MEM_INT_IMEM_SIZE => 16*1024,
|
||||
MEM_INT_DMEM_SIZE => 8*1024
|
||||
)
|
||||
port map (
|
||||
-- Global control --
|
||||
clk_i => std_ulogic(ULX3S_CLK),
|
||||
rstn_i => std_ulogic(ULX3S_RST_N),
|
||||
|
||||
-- GPIO --
|
||||
gpio_o => con_gpio_o,
|
||||
|
||||
-- primary UART --
|
||||
uart_txd_o => ULX3S_TX, -- UART0 send data
|
||||
uart_rxd_i => ULX3S_RX, -- UART0 receive data
|
||||
uart_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
|
||||
uart_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional
|
||||
|
||||
-- PWM (to on-board RGB LED) --
|
||||
pwm_o => con_pwm
|
||||
);
|
||||
|
||||
-- IO Connection --------------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
ULX3S_LED0 <= con_gpio_o(0);
|
||||
ULX3S_LED1 <= con_gpio_o(1);
|
||||
ULX3S_LED2 <= con_gpio_o(2);
|
||||
ULX3S_LED3 <= con_gpio_o(3);
|
||||
ULX3S_LED4 <= '0'; -- unused
|
||||
ULX3S_LED5 <= con_pwm(0);
|
||||
ULX3S_LED6 <= con_pwm(1);
|
||||
ULX3S_LED7 <= con_pwm(2);
|
||||
|
||||
end architecture;
|
||||
@ -0,0 +1,163 @@
|
||||
-- #################################################################################################
|
||||
-- # << NEORV32 - Example setup for the tinyVision.ai Inc. "UPduino v3" (c) Board >> #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # BSD 3-Clause License #
|
||||
-- # #
|
||||
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
|
||||
-- # #
|
||||
-- # Redistribution and use in source and binary forms, with or without modification, are #
|
||||
-- # permitted provided that the following conditions are met: #
|
||||
-- # #
|
||||
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
|
||||
-- # conditions and the following disclaimer. #
|
||||
-- # #
|
||||
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
|
||||
-- # conditions and the following disclaimer in the documentation and/or other materials #
|
||||
-- # provided with the distribution. #
|
||||
-- # #
|
||||
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
|
||||
-- # endorse or promote products derived from this software without specific prior written #
|
||||
-- # permission. #
|
||||
-- # #
|
||||
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
|
||||
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
|
||||
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
|
||||
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
|
||||
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
|
||||
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
|
||||
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
|
||||
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
|
||||
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
|
||||
-- #################################################################################################
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library iCE40;
|
||||
use iCE40.components.all; -- for device primitives and macros
|
||||
|
||||
entity neorv32_UPduino_BoardTop_MinimalBoot is
|
||||
port (
|
||||
-- UART (uart0) --
|
||||
uart_txd_o : out std_ulogic;
|
||||
uart_rxd_i : in std_ulogic;
|
||||
-- GPIO --
|
||||
gpio_o : out std_ulogic_vector(3 downto 0);
|
||||
-- PWM (to on-board RGB power LED) --
|
||||
pwm_o : out std_logic_vector(2 downto 0)
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture neorv32_UPduino_BoardTop_MinimalBoot_rtl of neorv32_UPduino_BoardTop_MinimalBoot is
|
||||
|
||||
-- configuration --
|
||||
constant f_clock_c : natural := 18000000; -- PLL output clock frequency in Hz
|
||||
|
||||
-- On-chip oscillator --
|
||||
signal hf_osc_clk : std_logic;
|
||||
|
||||
-- Globals
|
||||
signal pll_rstn : std_logic;
|
||||
signal pll_clk : std_logic;
|
||||
|
||||
-- internal IO connection --
|
||||
signal con_pwm : std_logic_vector(2 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
-- On-Chip HF Oscillator ------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
HSOSC_inst : SB_HFOSC
|
||||
generic map (
|
||||
CLKHF_DIV => "0b10" -- 12 MHz
|
||||
)
|
||||
port map (
|
||||
CLKHFPU => '1',
|
||||
CLKHFEN => '1',
|
||||
CLKHF => hf_osc_clk
|
||||
);
|
||||
|
||||
-- System PLL -----------------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
-- Settings generated by icepll -i 12 -o 18:
|
||||
-- F_PLLIN: 12.000 MHz (given)
|
||||
-- F_PLLOUT: 18.000 MHz (requested)
|
||||
-- F_PLLOUT: 18.000 MHz (achieved)
|
||||
-- FEEDBACK: SIMPLE
|
||||
-- F_PFD: 12.000 MHz
|
||||
-- F_VCO: 576.000 MHz
|
||||
-- DIVR: 0 (4'b0000)
|
||||
-- DIVF: 47 (7'b0101111)
|
||||
-- DIVQ: 5 (3'b101)
|
||||
-- FILTER_RANGE: 1 (3'b001)
|
||||
Pll_inst : SB_PLL40_CORE
|
||||
generic map (
|
||||
FEEDBACK_PATH => "SIMPLE",
|
||||
DIVR => x"0",
|
||||
DIVF => 7x"2F",
|
||||
DIVQ => 3x"5",
|
||||
FILTER_RANGE => 3x"1"
|
||||
)
|
||||
port map (
|
||||
REFERENCECLK => hf_osc_clk,
|
||||
PLLOUTCORE => open,
|
||||
PLLOUTGLOBAL => pll_clk,
|
||||
EXTFEEDBACK => '0',
|
||||
DYNAMICDELAY => x"00",
|
||||
LOCK => pll_rstn,
|
||||
BYPASS => '0',
|
||||
RESETB => '1',
|
||||
LATCHINPUTVALUE => '0',
|
||||
SDO => open,
|
||||
SDI => '0',
|
||||
SCLK => '0'
|
||||
);
|
||||
|
||||
-- The core of the problem ----------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot
|
||||
generic map (
|
||||
CLOCK_FREQUENCY => f_clock_c -- clock frequency of clk_i in Hz
|
||||
)
|
||||
port map (
|
||||
-- Global control --
|
||||
clk_i => std_ulogic(pll_clk),
|
||||
rstn_i => std_ulogic(pll_rstn),
|
||||
|
||||
-- GPIO --
|
||||
gpio_o => gpio_o,
|
||||
|
||||
-- primary UART --
|
||||
uart_txd_o => uart_txd_o, -- UART0 send data
|
||||
uart_rxd_i => uart_rxd_i, -- UART0 receive data
|
||||
uart_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
|
||||
uart_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional
|
||||
|
||||
-- PWM (to on-board RGB LED) --
|
||||
pwm_o => con_pwm
|
||||
);
|
||||
|
||||
-- IO Connection --------------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
RGB_inst: SB_RGBA_DRV
|
||||
generic map (
|
||||
CURRENT_MODE => "0b1",
|
||||
RGB0_CURRENT => "0b000011",
|
||||
RGB1_CURRENT => "0b000011",
|
||||
RGB2_CURRENT => "0b000011"
|
||||
)
|
||||
port map (
|
||||
CURREN => '1', -- I
|
||||
RGBLEDEN => '1', -- I
|
||||
RGB0PWM => con_pwm(1), -- I - green - pwm channel 1
|
||||
RGB1PWM => con_pwm(2), -- I - blue - pwm channel 2
|
||||
RGB2PWM => con_pwm(0), -- I - red - pwm channel 0
|
||||
RGB2 => pwm_o(2), -- O - red
|
||||
RGB1 => pwm_o(1), -- O - blue
|
||||
RGB0 => pwm_o(0) -- O - green
|
||||
);
|
||||
|
||||
end architecture;
|
||||
@ -0,0 +1,204 @@
|
||||
-- #################################################################################################
|
||||
-- # << NEORV32 - Example setup for the tinyVision.ai Inc. "UPduino v3" (c) Board >> #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # BSD 3-Clause License #
|
||||
-- # #
|
||||
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
|
||||
-- # #
|
||||
-- # Redistribution and use in source and binary forms, with or without modification, are #
|
||||
-- # permitted provided that the following conditions are met: #
|
||||
-- # #
|
||||
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
|
||||
-- # conditions and the following disclaimer. #
|
||||
-- # #
|
||||
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
|
||||
-- # conditions and the following disclaimer in the documentation and/or other materials #
|
||||
-- # provided with the distribution. #
|
||||
-- # #
|
||||
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
|
||||
-- # endorse or promote products derived from this software without specific prior written #
|
||||
-- # permission. #
|
||||
-- # #
|
||||
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
|
||||
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
|
||||
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
|
||||
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
|
||||
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
|
||||
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
|
||||
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
|
||||
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
|
||||
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
|
||||
-- #################################################################################################
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library iCE40;
|
||||
use iCE40.components.all; -- for device primitives and macros
|
||||
|
||||
entity neorv32_UPduino_BoardTop_UP5KDemo is
|
||||
port (
|
||||
-- UART (uart0) --
|
||||
uart_txd_o : out std_ulogic;
|
||||
uart_rxd_i : in std_ulogic;
|
||||
-- SPI to on-board flash --
|
||||
flash_sck_o : out std_ulogic;
|
||||
flash_sdo_o : out std_ulogic;
|
||||
flash_sdi_i : in std_ulogic;
|
||||
flash_csn_o : out std_ulogic; -- NEORV32.SPI_CS(0)
|
||||
-- SPI to IO pins --
|
||||
spi_sck_o : out std_ulogic;
|
||||
spi_sdo_o : out std_ulogic;
|
||||
spi_sdi_i : in std_ulogic;
|
||||
spi_csn_o : out std_ulogic; -- NEORV32.SPI_CS(1)
|
||||
-- TWI --
|
||||
twi_sda_io : inout std_logic;
|
||||
twi_scl_io : inout std_logic;
|
||||
-- GPIO --
|
||||
gpio_i : in std_ulogic_vector(3 downto 0);
|
||||
gpio_o : out std_ulogic_vector(3 downto 0);
|
||||
-- PWM (to on-board RGB power LED) --
|
||||
pwm_o : out std_ulogic_vector(2 downto 0)
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture neorv32_UPduino_BoardTop_UP5KDemo_rtl of neorv32_UPduino_BoardTop_UP5KDemo is
|
||||
|
||||
-- configuration --
|
||||
constant f_clock_c : natural := 18000000; -- PLL output clock frequency in Hz
|
||||
|
||||
-- On-chip oscillator --
|
||||
signal hf_osc_clk : std_logic;
|
||||
|
||||
-- Globals
|
||||
signal pll_rstn : std_logic;
|
||||
signal pll_clk : std_logic;
|
||||
|
||||
-- internal IO connection --
|
||||
signal con_pwm : std_ulogic_vector(2 downto 0);
|
||||
signal con_spi_sdi : std_ulogic;
|
||||
signal con_spi_csn : std_ulogic;
|
||||
|
||||
begin
|
||||
|
||||
-- On-Chip HF Oscillator ------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
HSOSC_inst : SB_HFOSC
|
||||
generic map (
|
||||
CLKHF_DIV => "0b10" -- 12 MHz
|
||||
)
|
||||
port map (
|
||||
CLKHFPU => '1',
|
||||
CLKHFEN => '1',
|
||||
CLKHF => hf_osc_clk
|
||||
);
|
||||
|
||||
|
||||
-- System PLL -----------------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
-- Settings generated by icepll -i 12 -o 18:
|
||||
-- F_PLLIN: 12.000 MHz (given)
|
||||
-- F_PLLOUT: 18.000 MHz (requested)
|
||||
-- F_PLLOUT: 18.000 MHz (achieved)
|
||||
-- FEEDBACK: SIMPLE
|
||||
-- F_PFD: 12.000 MHz
|
||||
-- F_VCO: 576.000 MHz
|
||||
-- DIVR: 0 (4'b0000)
|
||||
-- DIVF: 47 (7'b0101111)
|
||||
-- DIVQ: 5 (3'b101)
|
||||
-- FILTER_RANGE: 1 (3'b001)
|
||||
Pll_inst : SB_PLL40_CORE
|
||||
generic map (
|
||||
FEEDBACK_PATH => "SIMPLE",
|
||||
DIVR => x"0",
|
||||
DIVF => 7x"2F",
|
||||
DIVQ => 3x"5",
|
||||
FILTER_RANGE => 3x"1"
|
||||
)
|
||||
port map (
|
||||
REFERENCECLK => hf_osc_clk,
|
||||
PLLOUTCORE => open,
|
||||
PLLOUTGLOBAL => pll_clk,
|
||||
EXTFEEDBACK => '0',
|
||||
DYNAMICDELAY => x"00",
|
||||
LOCK => pll_rstn,
|
||||
BYPASS => '0',
|
||||
RESETB => '1',
|
||||
LATCHINPUTVALUE => '0',
|
||||
SDO => open,
|
||||
SDI => '0',
|
||||
SCLK => '0'
|
||||
);
|
||||
|
||||
-- The core of the problem ----------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
|
||||
neorv32_inst: entity work.neorv32_ProcessorTop_UP5KDemo
|
||||
generic map (
|
||||
CLOCK_FREQUENCY => f_clock_c -- clock frequency of clk_i in Hz
|
||||
)
|
||||
port map (
|
||||
-- Global control --
|
||||
clk_i => std_ulogic(pll_clk),
|
||||
rstn_i => std_ulogic(pll_rstn),
|
||||
|
||||
-- primary UART --
|
||||
uart_txd_o => uart_txd_o,
|
||||
uart_rxd_i => uart_rxd_i,
|
||||
uart_rts_o => open,
|
||||
uart_cts_i => '0',
|
||||
|
||||
-- SPI to on-board flash --
|
||||
flash_sck_o => flash_sck_o,
|
||||
flash_sdo_o => flash_sdo_o,
|
||||
flash_sdi_i => flash_sdi_i,
|
||||
flash_csn_o => flash_csn_o,
|
||||
|
||||
-- SPI to IO pins --
|
||||
spi_sck_o => spi_sck_o,
|
||||
spi_sdo_o => spi_sdo_o,
|
||||
spi_sdi_i => con_spi_sdi,
|
||||
spi_csn_o => con_spi_csn,
|
||||
|
||||
-- TWI --
|
||||
twi_sda_io => twi_sda_io,
|
||||
twi_scl_io => twi_scl_io,
|
||||
|
||||
-- GPIO --
|
||||
gpio_i => gpio_i,
|
||||
gpio_o => gpio_o,
|
||||
|
||||
-- PWM (to on-board RGB power LED) --
|
||||
pwm_o => con_pwm
|
||||
);
|
||||
|
||||
-- IO Connection --------------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
|
||||
-- SPI sdi read-back --
|
||||
spi_csn_o <= con_spi_csn;
|
||||
con_spi_sdi <= flash_sdi_i when (con_spi_csn = '0') else spi_sdi_i;
|
||||
|
||||
-- RGB --
|
||||
RGB_inst: SB_RGBA_DRV
|
||||
generic map (
|
||||
CURRENT_MODE => "0b1",
|
||||
RGB0_CURRENT => "0b000001",
|
||||
RGB1_CURRENT => "0b000001",
|
||||
RGB2_CURRENT => "0b000001"
|
||||
)
|
||||
port map (
|
||||
CURREN => '1', -- I
|
||||
RGBLEDEN => '1', -- I
|
||||
RGB0PWM => con_pwm(1), -- I - green - pwm channel 1
|
||||
RGB1PWM => con_pwm(2), -- I - bluee - pwm channel 2
|
||||
RGB2PWM => con_pwm(0), -- I - red - pwm channel 0
|
||||
RGB2 => pwm_o(2), -- O - red
|
||||
RGB1 => pwm_o(1), -- O - blue
|
||||
RGB0 => pwm_o(0) -- O - green
|
||||
);
|
||||
|
||||
end architecture;
|
||||
@ -0,0 +1,163 @@
|
||||
-- #################################################################################################
|
||||
-- # << NEORV32 - Example setup for the tinyVision.ai Inc. "UPduino v3" (c) Board >> #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # BSD 3-Clause License #
|
||||
-- # #
|
||||
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
|
||||
-- # #
|
||||
-- # Redistribution and use in source and binary forms, with or without modification, are #
|
||||
-- # permitted provided that the following conditions are met: #
|
||||
-- # #
|
||||
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
|
||||
-- # conditions and the following disclaimer. #
|
||||
-- # #
|
||||
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
|
||||
-- # conditions and the following disclaimer in the documentation and/or other materials #
|
||||
-- # provided with the distribution. #
|
||||
-- # #
|
||||
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
|
||||
-- # endorse or promote products derived from this software without specific prior written #
|
||||
-- # permission. #
|
||||
-- # #
|
||||
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
|
||||
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
|
||||
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
|
||||
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
|
||||
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
|
||||
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
|
||||
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
|
||||
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
|
||||
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
|
||||
-- #################################################################################################
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library iCE40;
|
||||
use iCE40.components.all; -- for device primitives and macros
|
||||
|
||||
entity neorv32_iCEBreaker_BoardTop_MinimalBoot is
|
||||
port (
|
||||
-- UART (uart0) --
|
||||
uart_txd_o : out std_ulogic;
|
||||
uart_rxd_i : in std_ulogic;
|
||||
-- GPIO --
|
||||
gpio_o : out std_ulogic_vector(3 downto 0);
|
||||
-- PWM (to on-board RGB power LED) --
|
||||
pwm_o : out std_logic_vector(2 downto 0)
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture neorv32_iCEBreaker_BoardTop_MinimalBoot_rtl of neorv32_iCEBreaker_BoardTop_MinimalBoot is
|
||||
|
||||
-- configuration --
|
||||
constant f_clock_c : natural := 18000000; -- PLL output clock frequency in Hz
|
||||
|
||||
-- On-chip oscillator --
|
||||
signal hf_osc_clk : std_logic;
|
||||
|
||||
-- Globals
|
||||
signal pll_rstn : std_logic;
|
||||
signal pll_clk : std_logic;
|
||||
|
||||
-- internal IO connection --
|
||||
signal con_pwm : std_logic_vector(2 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
-- On-Chip HF Oscillator ------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
HSOSC_inst : SB_HFOSC
|
||||
generic map (
|
||||
CLKHF_DIV => "0b10" -- 12 MHz
|
||||
)
|
||||
port map (
|
||||
CLKHFPU => '1',
|
||||
CLKHFEN => '1',
|
||||
CLKHF => hf_osc_clk
|
||||
);
|
||||
|
||||
-- System PLL -----------------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
-- Settings generated by icepll -i 12 -o 18:
|
||||
-- F_PLLIN: 12.000 MHz (given)
|
||||
-- F_PLLOUT: 18.000 MHz (requested)
|
||||
-- F_PLLOUT: 18.000 MHz (achieved)
|
||||
-- FEEDBACK: SIMPLE
|
||||
-- F_PFD: 12.000 MHz
|
||||
-- F_VCO: 576.000 MHz
|
||||
-- DIVR: 0 (4'b0000)
|
||||
-- DIVF: 47 (7'b0101111)
|
||||
-- DIVQ: 5 (3'b101)
|
||||
-- FILTER_RANGE: 1 (3'b001)
|
||||
Pll_inst : SB_PLL40_CORE
|
||||
generic map (
|
||||
FEEDBACK_PATH => "SIMPLE",
|
||||
DIVR => x"0",
|
||||
DIVF => 7x"2F",
|
||||
DIVQ => 3x"5",
|
||||
FILTER_RANGE => 3x"1"
|
||||
)
|
||||
port map (
|
||||
REFERENCECLK => hf_osc_clk,
|
||||
PLLOUTCORE => open,
|
||||
PLLOUTGLOBAL => pll_clk,
|
||||
EXTFEEDBACK => '0',
|
||||
DYNAMICDELAY => x"00",
|
||||
LOCK => pll_rstn,
|
||||
BYPASS => '0',
|
||||
RESETB => '1',
|
||||
LATCHINPUTVALUE => '0',
|
||||
SDO => open,
|
||||
SDI => '0',
|
||||
SCLK => '0'
|
||||
);
|
||||
|
||||
-- The core of the problem ----------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot
|
||||
generic map (
|
||||
CLOCK_FREQUENCY => f_clock_c -- clock frequency of clk_i in Hz
|
||||
)
|
||||
port map (
|
||||
-- Global control --
|
||||
clk_i => std_ulogic(pll_clk),
|
||||
rstn_i => std_ulogic(pll_rstn),
|
||||
|
||||
-- GPIO --
|
||||
gpio_o => gpio_o,
|
||||
|
||||
-- primary UART --
|
||||
uart_txd_o => uart_txd_o, -- UART0 send data
|
||||
uart_rxd_i => uart_rxd_i, -- UART0 receive data
|
||||
uart_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
|
||||
uart_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional
|
||||
|
||||
-- PWM (to on-board RGB LED) --
|
||||
pwm_o => con_pwm
|
||||
);
|
||||
|
||||
-- IO Connection --------------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
RGB_inst: SB_RGBA_DRV
|
||||
generic map (
|
||||
CURRENT_MODE => "0b1",
|
||||
RGB0_CURRENT => "0b000011",
|
||||
RGB1_CURRENT => "0b000011",
|
||||
RGB2_CURRENT => "0b000011"
|
||||
)
|
||||
port map (
|
||||
CURREN => '1', -- I
|
||||
RGBLEDEN => '1', -- I
|
||||
RGB0PWM => con_pwm(1), -- I - green - pwm channel 1
|
||||
RGB1PWM => con_pwm(2), -- I - blue - pwm channel 2
|
||||
RGB2PWM => con_pwm(0), -- I - red - pwm channel 0
|
||||
RGB2 => pwm_o(2), -- O - red
|
||||
RGB1 => pwm_o(1), -- O - blue
|
||||
RGB0 => pwm_o(0) -- O - green
|
||||
);
|
||||
|
||||
end architecture;
|
||||
@ -0,0 +1,205 @@
|
||||
-- #################################################################################################
|
||||
-- # << NEORV32 - Example setup for the tinyVision.ai Inc. "UPduino v3" (c) Board >> #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # BSD 3-Clause License #
|
||||
-- # #
|
||||
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
|
||||
-- # #
|
||||
-- # Redistribution and use in source and binary forms, with or without modification, are #
|
||||
-- # permitted provided that the following conditions are met: #
|
||||
-- # #
|
||||
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
|
||||
-- # conditions and the following disclaimer. #
|
||||
-- # #
|
||||
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
|
||||
-- # conditions and the following disclaimer in the documentation and/or other materials #
|
||||
-- # provided with the distribution. #
|
||||
-- # #
|
||||
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
|
||||
-- # endorse or promote products derived from this software without specific prior written #
|
||||
-- # permission. #
|
||||
-- # #
|
||||
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
|
||||
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
|
||||
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
|
||||
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
|
||||
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
|
||||
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
|
||||
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
|
||||
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
|
||||
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
|
||||
-- #################################################################################################
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library iCE40;
|
||||
use iCE40.components.all; -- for device primitives and macros
|
||||
|
||||
entity neorv32_iCEBreaker_BoardTop_UP5KDemo is
|
||||
port (
|
||||
user_reset_btn : in std_ulogic;
|
||||
-- UART (uart0) --
|
||||
uart_txd_o : out std_ulogic;
|
||||
uart_rxd_i : in std_ulogic;
|
||||
-- SPI to on-board flash --
|
||||
flash_sck_o : out std_ulogic;
|
||||
flash_sdo_o : out std_ulogic;
|
||||
flash_sdi_i : in std_ulogic;
|
||||
flash_csn_o : out std_ulogic; -- NEORV32.SPI_CS(0)
|
||||
-- SPI to IO pins --
|
||||
spi_sck_o : out std_ulogic;
|
||||
spi_sdo_o : out std_ulogic;
|
||||
spi_sdi_i : in std_ulogic;
|
||||
spi_csn_o : out std_ulogic; -- NEORV32.SPI_CS(1)
|
||||
-- TWI --
|
||||
twi_sda_io : inout std_logic;
|
||||
twi_scl_io : inout std_logic;
|
||||
-- GPIO --
|
||||
gpio_i : in std_ulogic_vector(3 downto 0);
|
||||
gpio_o : out std_ulogic_vector(3 downto 0);
|
||||
-- PWM (to on-board RGB power LED) --
|
||||
pwm_o : out std_ulogic_vector(2 downto 0)
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture neorv32_iCEBreaker_BoardTop_UP5KDemo_rtl of neorv32_iCEBreaker_BoardTop_UP5KDemo is
|
||||
|
||||
-- configuration --
|
||||
constant f_clock_c : natural := 18000000; -- PLL output clock frequency in Hz
|
||||
|
||||
-- On-chip oscillator --
|
||||
signal hf_osc_clk : std_logic;
|
||||
|
||||
-- Globals
|
||||
signal pll_rstn : std_logic;
|
||||
signal pll_clk : std_logic;
|
||||
|
||||
-- internal IO connection --
|
||||
signal con_pwm : std_ulogic_vector(2 downto 0);
|
||||
signal con_spi_sdi : std_ulogic;
|
||||
signal con_spi_csn : std_ulogic;
|
||||
|
||||
begin
|
||||
|
||||
-- On-Chip HF Oscillator ------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
HSOSC_inst : SB_HFOSC
|
||||
generic map (
|
||||
CLKHF_DIV => "0b10" -- 12 MHz
|
||||
)
|
||||
port map (
|
||||
CLKHFPU => '1',
|
||||
CLKHFEN => '1',
|
||||
CLKHF => hf_osc_clk
|
||||
);
|
||||
|
||||
|
||||
-- System PLL -----------------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
-- Settings generated by icepll -i 12 -o 18:
|
||||
-- F_PLLIN: 12.000 MHz (given)
|
||||
-- F_PLLOUT: 18.000 MHz (requested)
|
||||
-- F_PLLOUT: 18.000 MHz (achieved)
|
||||
-- FEEDBACK: SIMPLE
|
||||
-- F_PFD: 12.000 MHz
|
||||
-- F_VCO: 576.000 MHz
|
||||
-- DIVR: 0 (4'b0000)
|
||||
-- DIVF: 47 (7'b0101111)
|
||||
-- DIVQ: 5 (3'b101)
|
||||
-- FILTER_RANGE: 1 (3'b001)
|
||||
Pll_inst : SB_PLL40_CORE
|
||||
generic map (
|
||||
FEEDBACK_PATH => "SIMPLE",
|
||||
DIVR => x"0",
|
||||
DIVF => 7x"2F",
|
||||
DIVQ => 3x"5",
|
||||
FILTER_RANGE => 3x"1"
|
||||
)
|
||||
port map (
|
||||
REFERENCECLK => hf_osc_clk,
|
||||
PLLOUTCORE => open,
|
||||
PLLOUTGLOBAL => pll_clk,
|
||||
EXTFEEDBACK => '0',
|
||||
DYNAMICDELAY => x"00",
|
||||
LOCK => pll_rstn,
|
||||
BYPASS => '0',
|
||||
RESETB => user_reset_btn,
|
||||
LATCHINPUTVALUE => '0',
|
||||
SDO => open,
|
||||
SDI => '0',
|
||||
SCLK => '0'
|
||||
);
|
||||
|
||||
-- The core of the problem ----------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
|
||||
neorv32_inst: entity work.neorv32_ProcessorTop_UP5KDemo
|
||||
generic map (
|
||||
CLOCK_FREQUENCY => f_clock_c -- clock frequency of clk_i in Hz
|
||||
)
|
||||
port map (
|
||||
-- Global control --
|
||||
clk_i => std_ulogic(pll_clk),
|
||||
rstn_i => std_ulogic(pll_rstn),
|
||||
|
||||
-- primary UART --
|
||||
uart_txd_o => uart_txd_o,
|
||||
uart_rxd_i => uart_rxd_i,
|
||||
uart_rts_o => open,
|
||||
uart_cts_i => '0',
|
||||
|
||||
-- SPI to on-board flash --
|
||||
flash_sck_o => flash_sck_o,
|
||||
flash_sdo_o => flash_sdo_o,
|
||||
flash_sdi_i => flash_sdi_i,
|
||||
flash_csn_o => flash_csn_o,
|
||||
|
||||
-- SPI to IO pins --
|
||||
spi_sck_o => spi_sck_o,
|
||||
spi_sdo_o => spi_sdo_o,
|
||||
spi_sdi_i => con_spi_sdi,
|
||||
spi_csn_o => con_spi_csn,
|
||||
|
||||
-- TWI --
|
||||
twi_sda_io => twi_sda_io,
|
||||
twi_scl_io => twi_scl_io,
|
||||
|
||||
-- GPIO --
|
||||
gpio_i => gpio_i,
|
||||
gpio_o => gpio_o,
|
||||
|
||||
-- PWM (to on-board RGB power LED) --
|
||||
pwm_o => con_pwm
|
||||
);
|
||||
|
||||
-- IO Connection --------------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
|
||||
-- SPI sdi read-back --
|
||||
spi_csn_o <= con_spi_csn;
|
||||
con_spi_sdi <= flash_sdi_i when (con_spi_csn = '0') else spi_sdi_i;
|
||||
|
||||
-- RGB --
|
||||
RGB_inst: SB_RGBA_DRV
|
||||
generic map (
|
||||
CURRENT_MODE => "0b1",
|
||||
RGB0_CURRENT => "0b000001",
|
||||
RGB1_CURRENT => "0b000001",
|
||||
RGB2_CURRENT => "0b000001"
|
||||
)
|
||||
port map (
|
||||
CURREN => '1', -- I
|
||||
RGBLEDEN => '1', -- I
|
||||
RGB0PWM => con_pwm(1), -- I - green - pwm channel 1
|
||||
RGB1PWM => con_pwm(2), -- I - bluee - pwm channel 2
|
||||
RGB2PWM => con_pwm(0), -- I - red - pwm channel 0
|
||||
RGB2 => pwm_o(2), -- O - red
|
||||
RGB1 => pwm_o(1), -- O - blue
|
||||
RGB0 => pwm_o(0) -- O - green
|
||||
);
|
||||
|
||||
end architecture;
|
||||
@ -0,0 +1,172 @@
|
||||
-- #################################################################################################
|
||||
-- # << NEORV32 - Example setup with an external clock, for the iCESugar (c) Board >> #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # BSD 3-Clause License #
|
||||
-- # #
|
||||
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
|
||||
-- # #
|
||||
-- # Redistribution and use in source and binary forms, with or without modification, are #
|
||||
-- # permitted provided that the following conditions are met: #
|
||||
-- # #
|
||||
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
|
||||
-- # conditions and the following disclaimer. #
|
||||
-- # #
|
||||
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
|
||||
-- # conditions and the following disclaimer in the documentation and/or other materials #
|
||||
-- # provided with the distribution. #
|
||||
-- # #
|
||||
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
|
||||
-- # endorse or promote products derived from this software without specific prior written #
|
||||
-- # permission. #
|
||||
-- # #
|
||||
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
|
||||
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
|
||||
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
|
||||
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
|
||||
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
|
||||
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
|
||||
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
|
||||
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
|
||||
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
|
||||
-- #################################################################################################
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library iCE40;
|
||||
use iCE40.components.all; -- for device primitives and macros
|
||||
|
||||
entity neorv32_iCESugar_BoardTop_Minimal is
|
||||
port (
|
||||
-- 48MHz Clock input
|
||||
iCESugarv15_CLK : in std_logic;
|
||||
-- UART0
|
||||
iCESugarv15_RX : in std_logic;
|
||||
iCESugarv15_TX : out std_logic;
|
||||
-- LED outputs
|
||||
iCESugarv15_LED_R : out std_logic;
|
||||
iCESugarv15_LED_G : out std_logic;
|
||||
iCESugarv15_LED_B : out std_logic;
|
||||
-- USB Pins (which should be statically driven if not being used)
|
||||
iCESugarv15_USB_DP : out std_logic;
|
||||
iCESugarv15_USB_DN : out std_logic;
|
||||
iCESugarv15_USB_DP_PU : out std_logic
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture neorv32_iCESugar_BoardTop_Minimal_rtl of neorv32_iCESugar_BoardTop_Minimal is
|
||||
|
||||
-- configuration --
|
||||
constant f_clock_c : natural := 22000000; -- PLL output clock frequency in Hz
|
||||
|
||||
-- Globals
|
||||
signal pll_rstn : std_logic;
|
||||
signal pll_clk : std_logic;
|
||||
|
||||
-- internal IO connection --
|
||||
signal con_gpio_o : std_ulogic_vector(3 downto 0);
|
||||
signal con_pwm : std_logic_vector(2 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
-- Assign USB pins to "0" so as to disconnect iCESugar from
|
||||
-- the host system. Otherwise it would try to talk to
|
||||
-- us over USB, which wouldn't work since we have no stack.
|
||||
iCESugarv15_USB_DP <= '0';
|
||||
iCESugarv15_USB_DN <= '0';
|
||||
iCESugarv15_USB_DP_PU <= '0';
|
||||
|
||||
-- System PLL -----------------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
-- Settings generated by icepll -i 12 -o 22:
|
||||
-- F_PLLIN: 12.000 MHz (given)
|
||||
-- F_PLLOUT: 22.000 MHz (requested)
|
||||
-- F_PLLOUT: 22.000 MHz (achieved)
|
||||
-- FEEDBACK: SIMPLE
|
||||
-- F_PFD: 12.000 MHz
|
||||
-- F_VCO: 708.000 MHz
|
||||
-- DIVR: 0 (4'b0000)
|
||||
-- DIVF: 58 (7'b0111010)
|
||||
-- DIVQ: 5 (3'b101)
|
||||
-- FILTER_RANGE: 1 (3'b001)
|
||||
Pll_inst : SB_PLL40_PAD
|
||||
generic map (
|
||||
FEEDBACK_PATH => "SIMPLE",
|
||||
DIVR => x"0",
|
||||
DIVF => 7x"3A",
|
||||
DIVQ => 3x"5",
|
||||
FILTER_RANGE => 3x"1"
|
||||
)
|
||||
port map (
|
||||
PACKAGEPIN => iCESugarv15_CLK,
|
||||
PLLOUTCORE => open,
|
||||
PLLOUTGLOBAL => pll_clk,
|
||||
EXTFEEDBACK => '0',
|
||||
DYNAMICDELAY => x"00",
|
||||
LOCK => pll_rstn,
|
||||
BYPASS => '0',
|
||||
RESETB => '1',
|
||||
LATCHINPUTVALUE => '0',
|
||||
SDO => open,
|
||||
SDI => '0',
|
||||
SCLK => '0'
|
||||
);
|
||||
|
||||
-- The core of the problem ----------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
|
||||
neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot
|
||||
generic map (
|
||||
CLOCK_FREQUENCY => f_clock_c, -- clock frequency of clk_i in Hz
|
||||
CPU_EXTENSION_RISCV_A => false,
|
||||
CPU_EXTENSION_RISCV_C => false,
|
||||
CPU_EXTENSION_RISCV_E => false,
|
||||
CPU_EXTENSION_RISCV_M => false,
|
||||
CPU_EXTENSION_RISCV_U => false,
|
||||
CPU_EXTENSION_RISCV_Zfinx => false,
|
||||
CPU_EXTENSION_RISCV_Zicsr => true,
|
||||
CPU_EXTENSION_RISCV_Zifencei => false
|
||||
)
|
||||
port map (
|
||||
-- Global control --
|
||||
clk_i => std_ulogic(pll_clk),
|
||||
rstn_i => std_ulogic(pll_rstn),
|
||||
|
||||
-- GPIO --
|
||||
gpio_o => con_gpio_o,
|
||||
|
||||
-- primary UART --
|
||||
uart_txd_o => iCESugarv15_TX, -- UART0 send data
|
||||
uart_rxd_i => iCESugarv15_RX, -- UART0 receive data
|
||||
uart_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
|
||||
uart_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional
|
||||
|
||||
-- PWM (to on-board RGB LED) --
|
||||
pwm_o => con_pwm
|
||||
);
|
||||
|
||||
-- IO Connection --------------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
|
||||
RGB_inst: SB_RGBA_DRV
|
||||
generic map (
|
||||
CURRENT_MODE => "0b1",
|
||||
RGB0_CURRENT => "0b000011",
|
||||
RGB1_CURRENT => "0b000011",
|
||||
RGB2_CURRENT => "0b000011"
|
||||
)
|
||||
port map (
|
||||
CURREN => '1', -- I
|
||||
RGBLEDEN => '1', -- I
|
||||
RGB2PWM => con_pwm(2), -- I - blue - pwm channel 2
|
||||
RGB1PWM => con_pwm(1) or con_gpio_o(0), -- I - red - pwm channel 1 || BOOT blink
|
||||
RGB0PWM => con_pwm(0), -- I - green - pwm channel 0
|
||||
RGB2 => iCESugarv15_LED_B, -- O - blue
|
||||
RGB1 => iCESugarv15_LED_R, -- O - red
|
||||
RGB0 => iCESugarv15_LED_G -- O - green
|
||||
);
|
||||
|
||||
end architecture;
|
||||
@ -0,0 +1,177 @@
|
||||
-- #################################################################################################
|
||||
-- # << NEORV32 - Example setup including the bootloader, for the iCESugar (c) Board >> #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # BSD 3-Clause License #
|
||||
-- # #
|
||||
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
|
||||
-- # #
|
||||
-- # Redistribution and use in source and binary forms, with or without modification, are #
|
||||
-- # permitted provided that the following conditions are met: #
|
||||
-- # #
|
||||
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
|
||||
-- # conditions and the following disclaimer. #
|
||||
-- # #
|
||||
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
|
||||
-- # conditions and the following disclaimer in the documentation and/or other materials #
|
||||
-- # provided with the distribution. #
|
||||
-- # #
|
||||
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
|
||||
-- # endorse or promote products derived from this software without specific prior written #
|
||||
-- # permission. #
|
||||
-- # #
|
||||
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
|
||||
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
|
||||
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
|
||||
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
|
||||
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
|
||||
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
|
||||
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
|
||||
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
|
||||
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
|
||||
-- #################################################################################################
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library iCE40;
|
||||
use iCE40.components.all; -- for device primitives and macros
|
||||
|
||||
entity neorv32_iCESugar_BoardTop_MinimalBoot is
|
||||
port (
|
||||
-- LED outputs
|
||||
iCESugarv15_LED_R : out std_logic;
|
||||
iCESugarv15_LED_G : out std_logic;
|
||||
iCESugarv15_LED_B : out std_logic;
|
||||
-- UART0
|
||||
iCESugarv15_RX : in std_logic;
|
||||
iCESugarv15_TX : out std_logic;
|
||||
-- USB Pins (which should be statically driven if not being used)
|
||||
iCESugarv15_USB_DP : out std_logic;
|
||||
iCESugarv15_USB_DN : out std_logic;
|
||||
iCESugarv15_USB_DP_PU : out std_logic
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture neorv32_iCESugar_BoardTop_MinimalBoot_rtl of neorv32_iCESugar_BoardTop_MinimalBoot is
|
||||
|
||||
-- configuration --
|
||||
constant f_clock_c : natural := 18000000; -- PLL output clock frequency in Hz
|
||||
|
||||
-- On-chip oscillator --
|
||||
signal hf_osc_clk : std_logic;
|
||||
|
||||
-- Globals
|
||||
signal pll_rstn : std_logic;
|
||||
signal pll_clk : std_logic;
|
||||
|
||||
-- internal IO connection --
|
||||
signal con_gpio_o : std_ulogic_vector(3 downto 0);
|
||||
signal con_pwm : std_logic_vector(2 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
-- Assign USB pins to "0" so as to disconnect iCESugar from
|
||||
-- the host system. Otherwise it would try to talk to
|
||||
-- us over USB, which wouldn't work since we have no stack.
|
||||
iCESugarv15_USB_DP <= '0';
|
||||
iCESugarv15_USB_DN <= '0';
|
||||
iCESugarv15_USB_DP_PU <= '0';
|
||||
|
||||
-- On-Chip HF Oscillator ------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
HSOSC_inst : SB_HFOSC
|
||||
generic map (
|
||||
CLKHF_DIV => "0b10" -- 12 MHz
|
||||
)
|
||||
port map (
|
||||
CLKHFPU => '1',
|
||||
CLKHFEN => '1',
|
||||
CLKHF => hf_osc_clk
|
||||
);
|
||||
|
||||
-- System PLL -----------------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
-- Settings generated by icepll -i 12 -o 18:
|
||||
-- F_PLLIN: 12.000 MHz (given)
|
||||
-- F_PLLOUT: 18.000 MHz (requested)
|
||||
-- F_PLLOUT: 18.000 MHz (achieved)
|
||||
-- FEEDBACK: SIMPLE
|
||||
-- F_PFD: 12.000 MHz
|
||||
-- F_VCO: 576.000 MHz
|
||||
-- DIVR: 0 (4'b0000)
|
||||
-- DIVF: 47 (7'b0101111)
|
||||
-- DIVQ: 5 (3'b101)
|
||||
-- FILTER_RANGE: 1 (3'b001)
|
||||
Pll_inst : SB_PLL40_CORE
|
||||
generic map (
|
||||
FEEDBACK_PATH => "SIMPLE",
|
||||
DIVR => x"0",
|
||||
DIVF => 7x"2F",
|
||||
DIVQ => 3x"5",
|
||||
FILTER_RANGE => 3x"1"
|
||||
)
|
||||
port map (
|
||||
REFERENCECLK => hf_osc_clk,
|
||||
PLLOUTCORE => open,
|
||||
PLLOUTGLOBAL => pll_clk,
|
||||
EXTFEEDBACK => '0',
|
||||
DYNAMICDELAY => x"00",
|
||||
LOCK => pll_rstn,
|
||||
BYPASS => '0',
|
||||
RESETB => '1',
|
||||
LATCHINPUTVALUE => '0',
|
||||
SDO => open,
|
||||
SDI => '0',
|
||||
SCLK => '0'
|
||||
);
|
||||
|
||||
-- The core of the problem ----------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
|
||||
neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot
|
||||
generic map (
|
||||
CLOCK_FREQUENCY => f_clock_c -- clock frequency of clk_i in Hz
|
||||
)
|
||||
port map (
|
||||
-- Global control --
|
||||
clk_i => std_ulogic(pll_clk),
|
||||
rstn_i => std_ulogic(pll_rstn),
|
||||
|
||||
-- GPIO --
|
||||
gpio_o => con_gpio_o,
|
||||
|
||||
-- primary UART --
|
||||
uart_txd_o => iCESugarv15_TX, -- UART0 send data
|
||||
uart_rxd_i => iCESugarv15_RX, -- UART0 receive data
|
||||
uart_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
|
||||
uart_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional
|
||||
|
||||
-- PWM (to on-board RGB LED) --
|
||||
pwm_o => con_pwm
|
||||
);
|
||||
|
||||
-- IO Connection --------------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
|
||||
RGB_inst: SB_RGBA_DRV
|
||||
generic map (
|
||||
CURRENT_MODE => "0b1",
|
||||
RGB0_CURRENT => "0b000011",
|
||||
RGB1_CURRENT => "0b000011",
|
||||
RGB2_CURRENT => "0b000011"
|
||||
)
|
||||
port map (
|
||||
CURREN => '1', -- I
|
||||
RGBLEDEN => '1', -- I
|
||||
RGB2PWM => con_pwm(2), -- I - blue - pwm channel 2
|
||||
RGB1PWM => con_pwm(1) or con_gpio_o(0), -- I - red - pwm channel 1 || BOOT blink
|
||||
RGB0PWM => con_pwm(0), -- I - green - pwm channel 0
|
||||
RGB2 => iCESugarv15_LED_B, -- O - blue
|
||||
RGB1 => iCESugarv15_LED_R, -- O - red
|
||||
RGB0 => iCESugarv15_LED_G -- O - green
|
||||
);
|
||||
|
||||
end architecture;
|
||||
4
Libs/RiscV/NEORV32/setups/osflow/boards/AlhambraII.mk
Normal file
4
Libs/RiscV/NEORV32/setups/osflow/boards/AlhambraII.mk
Normal file
@ -0,0 +1,4 @@
|
||||
.PHONY: all
|
||||
|
||||
all: bit
|
||||
echo "! Built $(IMPL) for $(BOARD)"
|
||||
16
Libs/RiscV/NEORV32/setups/osflow/boards/Fomu.mk
Normal file
16
Libs/RiscV/NEORV32/setups/osflow/boards/Fomu.mk
Normal file
@ -0,0 +1,16 @@
|
||||
.PHONY: all
|
||||
|
||||
# Default target: run all required targets to build the DFU image.
|
||||
all: $(IMPL).dfu
|
||||
echo "! Built $(IMPL) for $(BOARD) $(FOMU_REV)"
|
||||
|
||||
# Use dfu-suffix to generate the DFU image from the FPGA bitstream.
|
||||
${IMPL}.dfu: $(IMPL).bit
|
||||
$(COPY) $< $@
|
||||
dfu-suffix -v 1209 -p 70b1 -a $@
|
||||
|
||||
# Use df-util to load the DFU image onto the Fomu.
|
||||
load: $(IMPL).dfu
|
||||
dfu-util -D $<
|
||||
|
||||
.PHONY: load
|
||||
4
Libs/RiscV/NEORV32/setups/osflow/boards/OrangeCrab.mk
Normal file
4
Libs/RiscV/NEORV32/setups/osflow/boards/OrangeCrab.mk
Normal file
@ -0,0 +1,4 @@
|
||||
.PHONY: all
|
||||
|
||||
all: bit
|
||||
echo "! Built $(IMPL) for $(BOARD)"
|
||||
4
Libs/RiscV/NEORV32/setups/osflow/boards/ULX3S.mk
Normal file
4
Libs/RiscV/NEORV32/setups/osflow/boards/ULX3S.mk
Normal file
@ -0,0 +1,4 @@
|
||||
.PHONY: all
|
||||
|
||||
all: bit
|
||||
echo "! Built $(IMPL) for $(BOARD)"
|
||||
4
Libs/RiscV/NEORV32/setups/osflow/boards/UPduino.mk
Normal file
4
Libs/RiscV/NEORV32/setups/osflow/boards/UPduino.mk
Normal file
@ -0,0 +1,4 @@
|
||||
.PHONY: all
|
||||
|
||||
all: bit
|
||||
echo "! Built $(IMPL) for $(BOARD)"
|
||||
4
Libs/RiscV/NEORV32/setups/osflow/boards/iCEBreaker.mk
Normal file
4
Libs/RiscV/NEORV32/setups/osflow/boards/iCEBreaker.mk
Normal file
@ -0,0 +1,4 @@
|
||||
.PHONY: all
|
||||
|
||||
all: bit
|
||||
echo "! Built $(IMPL) for $(BOARD)"
|
||||
4
Libs/RiscV/NEORV32/setups/osflow/boards/iCESugar.mk
Normal file
4
Libs/RiscV/NEORV32/setups/osflow/boards/iCESugar.mk
Normal file
@ -0,0 +1,4 @@
|
||||
.PHONY: all
|
||||
|
||||
all: bit
|
||||
echo "! Built $(IMPL) for $(BOARD)"
|
||||
107
Libs/RiscV/NEORV32/setups/osflow/boards/index.mk
Normal file
107
Libs/RiscV/NEORV32/setups/osflow/boards/index.mk
Normal file
@ -0,0 +1,107 @@
|
||||
PCF_PATH ?= constraints
|
||||
|
||||
|
||||
ifeq ($(BOARD),Fomu)
|
||||
|
||||
$(info Setting constraints and implementation args for BOARD Fomu)
|
||||
|
||||
# Different Fomu hardware revisions are wired differently and thus
|
||||
# require different configurations for yosys and nextpnr.
|
||||
# Configuration is performed by setting the environment variable FOMU_REV accordingly.
|
||||
|
||||
FOMU_REV ?= pvt
|
||||
|
||||
ifeq ($(FOMU_REV),evt1)
|
||||
YOSYSFLAGS ?= -D EVT=1 -D EVT1=1 -D HAVE_PMOD=1
|
||||
PNRFLAGS ?= --up5k --package sg48
|
||||
CONSTRAINTS ?= $(PCF_PATH)/$(BOARD)-evt2.pcf
|
||||
else ifeq ($(FOMU_REV),evt2)
|
||||
YOSYSFLAGS ?= -D EVT=1 -D EVT2=1 -D HAVE_PMOD=1
|
||||
PNRFLAGS ?= --up5k --package sg48
|
||||
CONSTRAINTS ?= $(PCF_PATH)/$(BOARD)-$(FOMU_REV).pcf
|
||||
else ifeq ($(FOMU_REV),evt3)
|
||||
YOSYSFLAGS ?= -D EVT=1 -D EVT3=1 -D HAVE_PMOD=1
|
||||
PNRFLAGS ?= --up5k --package sg48
|
||||
CONSTRAINTS ?= $(PCF_PATH)/$(BOARD)-$(FOMU_REV).pcf
|
||||
else ifeq ($(FOMU_REV),hacker)
|
||||
YOSYSFLAGS ?= -D HACKER=1
|
||||
PNRFLAGS ?= --up5k --package uwg30
|
||||
CONSTRAINTS ?= $(PCF_PATH)/$(BOARD)-$(FOMU_REV).pcf
|
||||
else ifeq ($(FOMU_REV),pvt)
|
||||
YOSYSFLAGS ?= -D PVT=1
|
||||
PNRFLAGS ?= --up5k --package uwg30
|
||||
CONSTRAINTS ?= $(PCF_PATH)/$(BOARD)-$(FOMU_REV).pcf
|
||||
else
|
||||
$(error Unrecognized FOMU_REV value. must be "evt1", "evt2", "evt3", "pvt", or "hacker")
|
||||
endif
|
||||
|
||||
IMPL := neorv32_Fomu_$(FOMU_REV)_$(ID)
|
||||
|
||||
endif
|
||||
|
||||
|
||||
ifeq ($(BOARD),iCESugar)
|
||||
$(info Setting constraints and implementation args for BOARD iCESugar)
|
||||
|
||||
CONSTRAINTS ?= $(PCF_PATH)/$(BOARD).pcf
|
||||
PNRFLAGS ?= --up5k --package sg48 --ignore-loops --timing-allow-fail
|
||||
IMPL ?= neorv32_$(BOARD)_$(ID)
|
||||
|
||||
endif
|
||||
|
||||
|
||||
ifeq ($(BOARD),UPduino)
|
||||
$(info Setting constraints and implementation args for BOARD UPduino)
|
||||
|
||||
UPduino_REV ?= v3
|
||||
|
||||
CONSTRAINTS ?= $(PCF_PATH)/$(BOARD)_v3.pcf
|
||||
PNRFLAGS ?= --up5k --package sg48 --ignore-loops --timing-allow-fail
|
||||
IMPL ?= neorv32_$(BOARD)_$(UPduino_REV)_$(ID)
|
||||
|
||||
endif
|
||||
|
||||
ifeq ($(BOARD),iCEBreaker)
|
||||
$(info Setting constraints and implementation args for BOARD iCEBreaker)
|
||||
|
||||
CONSTRAINTS ?= $(PCF_PATH)/$(BOARD).pcf
|
||||
PNRFLAGS ?= --up5k --package sg48 --ignore-loops --timing-allow-fail
|
||||
IMPL ?= neorv32_$(BOARD)_$(ID)
|
||||
|
||||
endif
|
||||
|
||||
|
||||
|
||||
ifeq ($(BOARD),OrangeCrab)
|
||||
$(info Setting constraints and implementation args for BOARD OrangeCrab)
|
||||
|
||||
DEVICE_SERIES = ecp5
|
||||
|
||||
OrangeCrab_REV ?= r02-25F
|
||||
|
||||
CONSTRAINTS ?= $(PCF_PATH)/$(BOARD).lpf
|
||||
PNRFLAGS ?= --25k --package CSFBGA285 --ignore-loops --timing-allow-fail
|
||||
IMPL ?= neorv32_$(BOARD)_$(OrangeCrab_REV)_$(ID)
|
||||
|
||||
endif
|
||||
|
||||
ifeq ($(BOARD),AlhambraII)
|
||||
$(info Setting constraints and implementation args for BOARD AlhambraII)
|
||||
|
||||
CONSTRAINTS ?= $(PCF_PATH)/$(BOARD).pcf
|
||||
PNRFLAGS ?= --hx8k --package tq144:4k --ignore-loops --timing-allow-fail
|
||||
IMPL ?= neorv32_$(BOARD)_$(ID)
|
||||
|
||||
endif
|
||||
|
||||
|
||||
ifeq ($(BOARD),ULX3S)
|
||||
$(info Setting constraints and implementation args for BOARD ULX3S)
|
||||
|
||||
DEVICE_SERIES = ecp5
|
||||
|
||||
CONSTRAINTS ?= $(PCF_PATH)/$(BOARD).lpf
|
||||
PNRFLAGS ?= --85k --freq 25 --package CABGA381 --ignore-loops --timing-allow-fail
|
||||
IMPL ?= neorv32_$(BOARD)_$(ID)
|
||||
|
||||
endif
|
||||
39
Libs/RiscV/NEORV32/setups/osflow/common.mk
Normal file
39
Libs/RiscV/NEORV32/setups/osflow/common.mk
Normal file
@ -0,0 +1,39 @@
|
||||
ID ?= impl_1
|
||||
|
||||
include boards/index.mk
|
||||
|
||||
ifndef TOP
|
||||
$(error TOP needs to be specified!)
|
||||
endif
|
||||
|
||||
include filesets.mk
|
||||
|
||||
ifndef DESIGN_SRC
|
||||
ifndef BOARD_SRC
|
||||
$(error Neither DESIGN_SRC nor BOARD_SRC were set!)
|
||||
endif
|
||||
endif
|
||||
|
||||
include tools.mk
|
||||
|
||||
ifdef GHDL_PLUGIN_MODULE
|
||||
YOSYSFLAGS += -m $(GHDL_PLUGIN_MODULE)
|
||||
endif
|
||||
|
||||
include synthesis.mk
|
||||
include PnR_Bit.mk
|
||||
|
||||
.PHONY: syn impl bit svf clean
|
||||
|
||||
syn: ${IMPL}.json
|
||||
impl: ${IMPL}.${PNR2BIT_EXT}
|
||||
bit: ${IMPL}.bit
|
||||
|
||||
ifeq ($(DEVICE_SERIES),ecp5)
|
||||
svf: ${IMPL}.svf
|
||||
endif
|
||||
|
||||
clean:
|
||||
rm -rf *.{${PNR2BIT_EXT},bit,cf,dfu,history,json,o,svf} *-report.txt
|
||||
|
||||
include boards/$(BOARD).mk
|
||||
24
Libs/RiscV/NEORV32/setups/osflow/constraints/AlhambraII.pcf
Normal file
24
Libs/RiscV/NEORV32/setups/osflow/constraints/AlhambraII.pcf
Normal file
@ -0,0 +1,24 @@
|
||||
# -----------------------------------------------------------------------------
|
||||
#- Alhambra II constraint file (.pcf)
|
||||
#- By Carlos Dominguez
|
||||
#- May - 2021
|
||||
#- GPL license
|
||||
#- Repo: https://github.com/zipotron/neorv32
|
||||
# -----------------------------------------------------------------------------
|
||||
|
||||
# UART port (on-board FTDI)
|
||||
set_io AlhambraII_TX 61 # output (ser-tx)
|
||||
set_io AlhambraII_RX 62 # input (ser-rx)
|
||||
|
||||
#> External clock (12 MHz)
|
||||
set_io AlhambraII_CLK 49
|
||||
|
||||
#> On-Board LEDs
|
||||
set_io AlhambraII_LED0 45
|
||||
set_io AlhambraII_LED1 44
|
||||
set_io AlhambraII_LED2 43
|
||||
set_io AlhambraII_LED3 42
|
||||
set_io AlhambraII_LED4 41
|
||||
set_io AlhambraII_LED5 39
|
||||
set_io AlhambraII_LED6 38
|
||||
set_io AlhambraII_LED7 37
|
||||
34
Libs/RiscV/NEORV32/setups/osflow/constraints/Fomu-evt2.pcf
Normal file
34
Libs/RiscV/NEORV32/setups/osflow/constraints/Fomu-evt2.pcf
Normal file
@ -0,0 +1,34 @@
|
||||
# Configuration for the Fomu 'evt2' board
|
||||
set_io clki 44
|
||||
set_io clki_alt 20
|
||||
set_io rgb[0] 39
|
||||
set_io rgb[1] 40
|
||||
set_io rgb[2] 41
|
||||
set_io pmod[0] 25
|
||||
set_io pmod[1] 26
|
||||
set_io pmod[2] 27
|
||||
set_io pmod[3] 28
|
||||
set_io user[0] 48
|
||||
set_io user[1] 47
|
||||
set_io user[2] 46
|
||||
set_io user[3] 45
|
||||
set_io user[4] 42
|
||||
set_io user[5] 38
|
||||
set_io spi_mosi 14
|
||||
set_io spi_miso 17
|
||||
set_io spi_clk 15
|
||||
set_io spi_cs 16
|
||||
set_io spi_io2 18
|
||||
set_io spi_io3 19
|
||||
set_io uart_tx 21
|
||||
set_io uart_rx 13
|
||||
set_io usb_dn 37
|
||||
set_io usb_dp 34
|
||||
set_io usb_dp_pu 35
|
||||
set_io usb_dn_pu 36
|
||||
set_io dbg[0] 20
|
||||
set_io dbg[1] 12
|
||||
set_io dbg[2] 11
|
||||
set_io dbg[3] 23
|
||||
set_io dbg[4] 10
|
||||
set_io dbg[5] 9
|
||||
34
Libs/RiscV/NEORV32/setups/osflow/constraints/Fomu-evt3.pcf
Normal file
34
Libs/RiscV/NEORV32/setups/osflow/constraints/Fomu-evt3.pcf
Normal file
@ -0,0 +1,34 @@
|
||||
# Configuration for the Fomu 'evt3' board
|
||||
set_io rgb[0] 39
|
||||
set_io rgb[1] 40
|
||||
set_io rgb[2] 41
|
||||
set_io pmod[0] 28
|
||||
set_io pmod[1] 27
|
||||
set_io pmod[2] 26
|
||||
set_io pmod[3] 23
|
||||
set_io clki_alt 20
|
||||
set_io clki 44
|
||||
set_io user[0] 48
|
||||
set_io user[1] 47
|
||||
set_io user[2] 46
|
||||
set_io user[3] 45
|
||||
set_io user[4] 42
|
||||
set_io user[5] 38
|
||||
set_io spi_mosi 14
|
||||
set_io spi_miso 17
|
||||
set_io spi_clk 15
|
||||
set_io spi_io2 18
|
||||
set_io spi_io3 19
|
||||
set_io spi_cs 16
|
||||
set_io uart_tx 21
|
||||
set_io uart_rx 13
|
||||
set_io usb_dn 37
|
||||
set_io usb_dp 34
|
||||
set_io usb_dp_pu 35
|
||||
set_io usb_dn_pu 36
|
||||
set_io dbg[0] 20
|
||||
set_io dbg[1] 12
|
||||
set_io dbg[2] 11
|
||||
set_io dbg[3] 25
|
||||
set_io dbg[4] 10
|
||||
set_io dbg[5] 9
|
||||
16
Libs/RiscV/NEORV32/setups/osflow/constraints/Fomu-hacker.pcf
Normal file
16
Libs/RiscV/NEORV32/setups/osflow/constraints/Fomu-hacker.pcf
Normal file
@ -0,0 +1,16 @@
|
||||
# Configuration for the Fomu 'hacker' board
|
||||
set_io clki F5 # Clock input from 48MHz Oscillator
|
||||
set_io rgb[0] A5 # Blue LED
|
||||
set_io rgb[1] B5 # Green LED
|
||||
set_io rgb[2] C5 # Red LED
|
||||
set_io user[0] F4 # User touch pad 1
|
||||
set_io user[1] E5 # User touch pad 2
|
||||
set_io user[2] E4 # User touch pad 3
|
||||
set_io user[3] F2 # User touch pad 4
|
||||
set_io spi_mosi F1 # SPI Master Out, Slave In Pin
|
||||
set_io spi_miso E1 # SPI Master In, Slave Out Pin
|
||||
set_io spi_clk D1 # SPI Master Clock Output Pin
|
||||
set_io spi_cs C1 # SPI Chip Select
|
||||
set_io usb_dn A2 # USB D- pad
|
||||
set_io usb_dp A4 # USB D+ pad
|
||||
set_io usb_dp_pu D5 # USB D+ pull up (indicates device connected)
|
||||
18
Libs/RiscV/NEORV32/setups/osflow/constraints/Fomu-pvt.pcf
Normal file
18
Libs/RiscV/NEORV32/setups/osflow/constraints/Fomu-pvt.pcf
Normal file
@ -0,0 +1,18 @@
|
||||
# Configuration for the Fomu 'pvt' board
|
||||
set_io clki F4 # Clock input from 48MHz Oscillator
|
||||
set_io rgb[0] A5 # Blue LED
|
||||
set_io rgb[1] B5 # Green LED
|
||||
set_io rgb[2] C5 # Red LED
|
||||
set_io user[0] E4 # User touch pad 1
|
||||
set_io user[1] D5 # User touch pad 2
|
||||
set_io user[2] E5 # User touch pad 3
|
||||
set_io user[3] F5 # User touch pad 4
|
||||
set_io spi_mosi F1 # SPI Master Out, Slave In Pin
|
||||
set_io spi_miso E1 # SPI Master In, Slave Out Pin
|
||||
set_io spi_clk D1 # SPI Master Clock Output Pin
|
||||
set_io spi_cs C1 # SPI Chip Select
|
||||
set_io spi_io2 F2
|
||||
set_io spi_io3 B1
|
||||
set_io usb_dn A2 # USB D- pad
|
||||
set_io usb_dp A1 # USB D+ pad
|
||||
set_io usb_dp_pu A4 # USB D+ pull up (indicates device connected)
|
||||
278
Libs/RiscV/NEORV32/setups/osflow/constraints/OrangeCrab.lpf
Normal file
278
Libs/RiscV/NEORV32/setups/osflow/constraints/OrangeCrab.lpf
Normal file
@ -0,0 +1,278 @@
|
||||
#| OrangeCrab-r02-25F
|
||||
|
||||
|
||||
LOCATE COMP "OrangeCrab_CLK" SITE "A9";
|
||||
IOBUF PORT "OrangeCrab_CLK" IO_TYPE=LVCMOS33;
|
||||
FREQUENCY PORT "OrangeCrab_CLK" 48.0 MHz;
|
||||
|
||||
LOCATE COMP "OrangeCrab_RST_N" SITE "V17";
|
||||
IOBUF PORT "OrangeCrab_RST_N" IO_TYPE=LVCMOS33;
|
||||
|
||||
LOCATE COMP "OrangeCrab_LED_RGB_R" SITE "K4";
|
||||
IOBUF PORT "OrangeCrab_LED_RGB_R" IO_TYPE=LVCMOS33;
|
||||
LOCATE COMP "OrangeCrab_LED_RGB_G" SITE "M3";
|
||||
IOBUF PORT "OrangeCrab_LED_RGB_G" IO_TYPE=LVCMOS33;
|
||||
LOCATE COMP "OrangeCrab_LED_RGB_B" SITE "J3";
|
||||
IOBUF PORT "OrangeCrab_LED_RGB_B" IO_TYPE=LVCMOS33;
|
||||
|
||||
LOCATE COMP "OrangeCrab_USR_BTN" SITE "J17";
|
||||
IOBUF PORT "OrangeCrab_USR_BTN" IO_TYPE=SSTL135_I;
|
||||
|
||||
LOCATE COMP "OrangeCrab_USB_D_P" SITE "N1";
|
||||
IOBUF PORT "OrangeCrab_USB_D_P" IO_TYPE=LVCMOS33;
|
||||
LOCATE COMP "OrangeCrab_USB_D_N" SITE "M2";
|
||||
IOBUF PORT "OrangeCrab_USB_D_N" IO_TYPE=LVCMOS33;
|
||||
LOCATE COMP "OrangeCrab_USB_DP_PU" SITE "N2";
|
||||
IOBUF PORT "OrangeCrab_USB_DP_PU" IO_TYPE=LVCMOS33;
|
||||
|
||||
LOCATE COMP "OrangeCrab_GPIO_0" SITE "N17";
|
||||
IOBUF PORT "OrangeCrab_GPIO_0" IO_TYPE=LVCMOS33;
|
||||
IOBUF PORT "OrangeCrab_GPIO_0" PULLMODE=DOWN;
|
||||
LOCATE COMP "OrangeCrab_GPIO_1" SITE "M18";
|
||||
IOBUF PORT "OrangeCrab_GPIO_1" IO_TYPE=LVCMOS33;
|
||||
IOBUF PORT "OrangeCrab_GPIO_1" PULLMODE=DOWN;
|
||||
LOCATE COMP "OrangeCrab_GPIO_5" SITE "B10";
|
||||
IOBUF PORT "OrangeCrab_GPIO_5" IO_TYPE=LVCMOS33;
|
||||
IOBUF PORT "OrangeCrab_GPIO_5" PULLMODE=DOWN;
|
||||
LOCATE COMP "OrangeCrab_GPIO_6" SITE "B9";
|
||||
IOBUF PORT "OrangeCrab_GPIO_6" IO_TYPE=LVCMOS33;
|
||||
IOBUF PORT "OrangeCrab_GPIO_6" PULLMODE=DOWN;
|
||||
LOCATE COMP "OrangeCrab_GPIO_9" SITE "C8";
|
||||
IOBUF PORT "OrangeCrab_GPIO_9" IO_TYPE=LVCMOS33;
|
||||
IOBUF PORT "OrangeCrab_GPIO_9" PULLMODE=DOWN;
|
||||
LOCATE COMP "OrangeCrab_GPIO_10" SITE "B8";
|
||||
IOBUF PORT "OrangeCrab_GPIO_10" IO_TYPE=LVCMOS33;
|
||||
IOBUF PORT "OrangeCrab_GPIO_10" PULLMODE=DOWN;
|
||||
LOCATE COMP "OrangeCrab_GPIO_11" SITE "A8";
|
||||
IOBUF PORT "OrangeCrab_GPIO_11" IO_TYPE=LVCMOS33;
|
||||
IOBUF PORT "OrangeCrab_GPIO_11" PULLMODE=DOWN;
|
||||
LOCATE COMP "OrangeCrab_GPIO_12" SITE "H2";
|
||||
IOBUF PORT "OrangeCrab_GPIO_12" IO_TYPE=LVCMOS33;
|
||||
IOBUF PORT "OrangeCrab_GPIO_12" PULLMODE=DOWN;
|
||||
LOCATE COMP "OrangeCrab_GPIO_13" SITE "J2";
|
||||
IOBUF PORT "OrangeCrab_GPIO_13" IO_TYPE=LVCMOS33;
|
||||
IOBUF PORT "OrangeCrab_GPIO_13" PULLMODE=DOWN;
|
||||
LOCATE COMP "OrangeCrab_GPIO_A0" SITE "L4";
|
||||
IOBUF PORT "OrangeCrab_GPIO_A0" IO_TYPE=LVCMOS33;
|
||||
IOBUF PORT "OrangeCrab_GPIO_A0" PULLMODE=DOWN;
|
||||
LOCATE COMP "OrangeCrab_GPIO_A1" SITE "N3";
|
||||
IOBUF PORT "OrangeCrab_GPIO_A1" IO_TYPE=LVCMOS33;
|
||||
IOBUF PORT "OrangeCrab_GPIO_A1" PULLMODE=DOWN;
|
||||
LOCATE COMP "OrangeCrab_GPIO_A2" SITE "N4";
|
||||
IOBUF PORT "OrangeCrab_GPIO_A2" IO_TYPE=LVCMOS33;
|
||||
IOBUF PORT "OrangeCrab_GPIO_A2" PULLMODE=DOWN;
|
||||
LOCATE COMP "OrangeCrab_GPIO_A3" SITE "H4";
|
||||
IOBUF PORT "OrangeCrab_GPIO_A3" IO_TYPE=LVCMOS33;
|
||||
IOBUF PORT "OrangeCrab_GPIO_A3" PULLMODE=DOWN;
|
||||
|
||||
LOCATE COMP "OrangeCrab_DDRAM_A[0]" SITE "C4";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_A[0]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_A[0]" IO_TYPE=SSTL135_I;
|
||||
LOCATE COMP "OrangeCrab_DDRAM_A[1]" SITE "D2";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_A[1]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_A[1]" IO_TYPE=SSTL135_I;
|
||||
LOCATE COMP "OrangeCrab_DDRAM_A[2]" SITE "D3";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_A[2]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_A[2]" IO_TYPE=SSTL135_I;
|
||||
LOCATE COMP "OrangeCrab_DDRAM_A[3]" SITE "A3";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_A[3]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_A[3]" IO_TYPE=SSTL135_I;
|
||||
LOCATE COMP "OrangeCrab_DDRAM_A[4]" SITE "A4";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_A[4]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_A[4]" IO_TYPE=SSTL135_I;
|
||||
LOCATE COMP "OrangeCrab_DDRAM_A[5]" SITE "D4";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_A[5]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_A[5]" IO_TYPE=SSTL135_I;
|
||||
LOCATE COMP "OrangeCrab_DDRAM_A[6]" SITE "C3";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_A[6]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_A[6]" IO_TYPE=SSTL135_I;
|
||||
LOCATE COMP "OrangeCrab_DDRAM_A[7]" SITE "B2";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_A[7]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_A[7]" IO_TYPE=SSTL135_I;
|
||||
LOCATE COMP "OrangeCrab_DDRAM_A[8]" SITE "B1";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_A[8]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_A[8]" IO_TYPE=SSTL135_I;
|
||||
LOCATE COMP "OrangeCrab_DDRAM_A[9]" SITE "D1";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_A[9]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_A[9]" IO_TYPE=SSTL135_I;
|
||||
LOCATE COMP "OrangeCrab_DDRAM_A[10]" SITE "A7";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_A[10]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_A[10]" IO_TYPE=SSTL135_I;
|
||||
LOCATE COMP "OrangeCrab_DDRAM_A[11]" SITE "C2";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_A[11]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_A[11]" IO_TYPE=SSTL135_I;
|
||||
LOCATE COMP "OrangeCrab_DDRAM_A[12]" SITE "B6";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_A[12]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_A[12]" IO_TYPE=SSTL135_I;
|
||||
LOCATE COMP "OrangeCrab_DDRAM_A[13]" SITE "C1";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_A[13]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_A[13]" IO_TYPE=SSTL135_I;
|
||||
LOCATE COMP "OrangeCrab_DDRAM_A[14]" SITE "A2";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_A[14]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_A[14]" IO_TYPE=SSTL135_I;
|
||||
LOCATE COMP "OrangeCrab_DDRAM_A[15]" SITE "C7";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_A[15]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_A[15]" IO_TYPE=SSTL135_I;
|
||||
|
||||
LOCATE COMP "OrangeCrab_DDRAM_BA[0]" SITE "D6";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_BA[0]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_BA[0]" IO_TYPE=SSTL135_I;
|
||||
LOCATE COMP "OrangeCrab_DDRAM_BA[1]" SITE "B7";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_BA[1]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_BA[1]" IO_TYPE=SSTL135_I;
|
||||
LOCATE COMP "OrangeCrab_DDRAM_BA[2]" SITE "A6";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_BA[2]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_BA[2]" IO_TYPE=SSTL135_I;
|
||||
|
||||
LOCATE COMP "OrangeCrab_DDRAM_RAS_N" SITE "C12";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_RAS_N" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_RAS_N" IO_TYPE=SSTL135_I;
|
||||
|
||||
LOCATE COMP "OrangeCrab_DDRAM_CAS_N" SITE "D13";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_CAS_N" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_CAS_N" IO_TYPE=SSTL135_I;
|
||||
|
||||
LOCATE COMP "OrangeCrab_DDRAM_WE_N" SITE "B12";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_WE_N" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_WE_N" IO_TYPE=SSTL135_I;
|
||||
|
||||
LOCATE COMP "OrangeCrab_DDRAM_CS_N" SITE "A12";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_CS_N" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_CS_N" IO_TYPE=SSTL135_I;
|
||||
|
||||
LOCATE COMP "OrangeCrab_DDRAM_DM[0]" SITE "D16";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DM[0]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DM[0]" IO_TYPE=SSTL135_I;
|
||||
LOCATE COMP "OrangeCrab_DDRAM_DM[1]" SITE "G16";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DM[1]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DM[1]" IO_TYPE=SSTL135_I;
|
||||
|
||||
LOCATE COMP "OrangeCrab_DDRAM_DQ[0]" SITE "C17";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[0]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[0]" IO_TYPE=SSTL135_I;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[0]" TERMINATION=OFF;
|
||||
LOCATE COMP "OrangeCrab_DDRAM_DQ[1]" SITE "D15";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[1]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[1]" IO_TYPE=SSTL135_I;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[1]" TERMINATION=OFF;
|
||||
LOCATE COMP "OrangeCrab_DDRAM_DQ[2]" SITE "B17";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[2]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[2]" IO_TYPE=SSTL135_I;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[2]" TERMINATION=OFF;
|
||||
LOCATE COMP "OrangeCrab_DDRAM_DQ[3]" SITE "C16";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[3]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[3]" IO_TYPE=SSTL135_I;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[3]" TERMINATION=OFF;
|
||||
LOCATE COMP "OrangeCrab_DDRAM_DQ[4]" SITE "A15";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[4]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[4]" IO_TYPE=SSTL135_I;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[4]" TERMINATION=OFF;
|
||||
LOCATE COMP "OrangeCrab_DDRAM_DQ[5]" SITE "B13";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[5]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[5]" IO_TYPE=SSTL135_I;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[5]" TERMINATION=OFF;
|
||||
LOCATE COMP "OrangeCrab_DDRAM_DQ[6]" SITE "A17";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[6]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[6]" IO_TYPE=SSTL135_I;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[6]" TERMINATION=OFF;
|
||||
LOCATE COMP "OrangeCrab_DDRAM_DQ[7]" SITE "A13";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[7]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[7]" IO_TYPE=SSTL135_I;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[7]" TERMINATION=OFF;
|
||||
LOCATE COMP "OrangeCrab_DDRAM_DQ[8]" SITE "F17";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[8]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[8]" IO_TYPE=SSTL135_I;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[8]" TERMINATION=OFF;
|
||||
LOCATE COMP "OrangeCrab_DDRAM_DQ[9]" SITE "F16";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[9]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[9]" IO_TYPE=SSTL135_I;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[9]" TERMINATION=OFF;
|
||||
LOCATE COMP "OrangeCrab_DDRAM_DQ[10]" SITE "G15";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[10]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[10]" IO_TYPE=SSTL135_I;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[10]" TERMINATION=OFF;
|
||||
LOCATE COMP "OrangeCrab_DDRAM_DQ[11]" SITE "F15";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[11]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[11]" IO_TYPE=SSTL135_I;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[11]" TERMINATION=OFF;
|
||||
LOCATE COMP "OrangeCrab_DDRAM_DQ[12]" SITE "J16";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[12]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[12]" IO_TYPE=SSTL135_I;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[12]" TERMINATION=OFF;
|
||||
LOCATE COMP "OrangeCrab_DDRAM_DQ[13]" SITE "C18";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[13]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[13]" IO_TYPE=SSTL135_I;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[13]" TERMINATION=OFF;
|
||||
LOCATE COMP "OrangeCrab_DDRAM_DQ[14]" SITE "H16";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[14]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[14]" IO_TYPE=SSTL135_I;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[14]" TERMINATION=OFF;
|
||||
LOCATE COMP "OrangeCrab_DDRAM_DQ[15]" SITE "F18";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[15]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[15]" IO_TYPE=SSTL135_I;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQ[15]" TERMINATION=OFF;
|
||||
|
||||
LOCATE COMP "OrangeCrab_DDRAM_DQS_P[0]" SITE "B15";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQS_P[0]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQS_P[0]" IO_TYPE=SSTL135D_I;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQS_P[0]" TERMINATION=OFF;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQS_P[0]" DIFFRESISTOR=100;
|
||||
LOCATE COMP "OrangeCrab_DDRAM_DQS_P[1]" SITE "G18";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQS_P[1]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQS_P[1]" IO_TYPE=SSTL135D_I;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQS_P[1]" TERMINATION=OFF;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_DQS_P[1]" DIFFRESISTOR=100;
|
||||
|
||||
LOCATE COMP "OrangeCrab_DDRAM_CLK_P" SITE "J18";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_CLK_P" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_CLK_P" IO_TYPE=SSTL135D_I;
|
||||
|
||||
LOCATE COMP "OrangeCrab_DDRAM_CKE" SITE "D18";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_CKE" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_CKE" IO_TYPE=SSTL135_I;
|
||||
|
||||
LOCATE COMP "OrangeCrab_DDRAM_ODT" SITE "C13";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_ODT" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_ODT" IO_TYPE=SSTL135_I;
|
||||
|
||||
LOCATE COMP "OrangeCrab_DDRAM_RESET_N" SITE "L18";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_RESET_N" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_RESET_N" IO_TYPE=SSTL135_I;
|
||||
|
||||
LOCATE COMP "OrangeCrab_DDRAM_VCCIO[0]" SITE "K16";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_VCCIO[0]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_VCCIO[0]" IO_TYPE=SSTL135_II;
|
||||
LOCATE COMP "OrangeCrab_DDRAM_VCCIO[1]" SITE "D17";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_VCCIO[1]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_VCCIO[1]" IO_TYPE=SSTL135_II;
|
||||
LOCATE COMP "OrangeCrab_DDRAM_VCCIO[2]" SITE "K15";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_VCCIO[2]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_VCCIO[2]" IO_TYPE=SSTL135_II;
|
||||
LOCATE COMP "OrangeCrab_DDRAM_VCCIO[3]" SITE "K17";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_VCCIO[3]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_VCCIO[3]" IO_TYPE=SSTL135_II;
|
||||
LOCATE COMP "OrangeCrab_DDRAM_VCCIO[4]" SITE "B18";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_VCCIO[4]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_VCCIO[4]" IO_TYPE=SSTL135_II;
|
||||
LOCATE COMP "OrangeCrab_DDRAM_VCCIO[5]" SITE "C6";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_VCCIO[5]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_VCCIO[5]" IO_TYPE=SSTL135_II;
|
||||
|
||||
LOCATE COMP "OrangeCrab_DDRAM_GND[0]" SITE "L15";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_GND[0]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_GND[0]" IO_TYPE=SSTL135_II;
|
||||
LOCATE COMP "OrangeCrab_DDRAM_GND[1]" SITE "L16";
|
||||
IOBUF PORT "OrangeCrab_DDRAM_GND[1]" SLEWRATE=FAST;
|
||||
IOBUF PORT "OrangeCrab_DDRAM_GND[1]" IO_TYPE=SSTL135_II;
|
||||
|
||||
LOCATE COMP "OrangeCrab_SPIFLASH_CS_N" SITE "U17";
|
||||
IOBUF PORT "OrangeCrab_SPIFLASH_CS_N" IO_TYPE=LVCMOS33;
|
||||
|
||||
LOCATE COMP "OrangeCrab_SPIFLASH_DQ[0]" SITE "U18";
|
||||
IOBUF PORT "OrangeCrab_SPIFLASH_DQ[0]" IO_TYPE=LVCMOS33;
|
||||
LOCATE COMP "OrangeCrab_SPIFLASH_DQ[1]" SITE "T18";
|
||||
IOBUF PORT "OrangeCrab_SPIFLASH_DQ[1]" IO_TYPE=LVCMOS33;
|
||||
LOCATE COMP "OrangeCrab_SPIFLASH_DQ[2]" SITE "R18";
|
||||
IOBUF PORT "OrangeCrab_SPIFLASH_DQ[2]" IO_TYPE=LVCMOS33;
|
||||
LOCATE COMP "OrangeCrab_SPIFLASH_DQ[3]" SITE "N18";
|
||||
IOBUF PORT "OrangeCrab_SPIFLASH_DQ[3]" IO_TYPE=LVCMOS33;
|
||||
598
Libs/RiscV/NEORV32/setups/osflow/constraints/ULX3S.lpf
Normal file
598
Libs/RiscV/NEORV32/setups/osflow/constraints/ULX3S.lpf
Normal file
@ -0,0 +1,598 @@
|
||||
BLOCK RESETPATHS;
|
||||
BLOCK ASYNCPATHS;
|
||||
## ULX3S v2.x.x and v3.0.x
|
||||
|
||||
# The clock "usb" and "gpdi" sheet
|
||||
LOCATE COMP "ULX3S_CLK" SITE "G2";
|
||||
IOBUF PORT "ULX3S_CLK" PULLMODE=NONE IO_TYPE=LVCMOS33;
|
||||
FREQUENCY PORT "ULX3S_CLK" 25 MHZ;
|
||||
|
||||
# JTAG and SPI FLASH voltage 3.3V and options to boot from SPI flash
|
||||
# write to FLASH possible any time from JTAG:
|
||||
SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=ENABLE SLAVE_PARALLEL_PORT=DISABLE;
|
||||
# write to FLASH possible from user bitstream:
|
||||
# SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE;
|
||||
|
||||
## USBSERIAL FTDI-FPGA serial port "usb" sheet
|
||||
LOCATE COMP "ULX3S_TX" SITE "L4"; # FPGA transmits to ftdi
|
||||
LOCATE COMP "ULX3S_RX" SITE "M1"; # FPGA receives from ftdi
|
||||
LOCATE COMP "ftdi_nrts" SITE "M3"; # FPGA receives
|
||||
LOCATE COMP "ftdi_ndtr" SITE "N1"; # FPGA receives
|
||||
LOCATE COMP "ftdi_txden" SITE "L3"; # FPGA receives
|
||||
IOBUF PORT "ULX3S_TX" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "ULX3S_RX" PULLMODE=UP IO_TYPE=LVCMOS33;
|
||||
IOBUF PORT "ftdi_nrts" PULLMODE=UP IO_TYPE=LVCMOS33;
|
||||
IOBUF PORT "ftdi_ndtr" PULLMODE=UP IO_TYPE=LVCMOS33;
|
||||
IOBUF PORT "ftdi_txden" PULLMODE=UP IO_TYPE=LVCMOS33;
|
||||
|
||||
## LED indicators "blinkey" and "gpio" sheet
|
||||
LOCATE COMP "ULX3S_LED7" SITE "H3";
|
||||
LOCATE COMP "ULX3S_LED6" SITE "E1";
|
||||
LOCATE COMP "ULX3S_LED5" SITE "E2";
|
||||
LOCATE COMP "ULX3S_LED4" SITE "D1";
|
||||
LOCATE COMP "ULX3S_LED3" SITE "D2";
|
||||
LOCATE COMP "ULX3S_LED2" SITE "C1";
|
||||
LOCATE COMP "ULX3S_LED1" SITE "C2";
|
||||
LOCATE COMP "ULX3S_LED0" SITE "B2";
|
||||
IOBUF PORT "ULX3S_LED0" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "ULX3S_LED1" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "ULX3S_LED2" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "ULX3S_LED3" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "ULX3S_LED4" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "ULX3S_LED5" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "ULX3S_LED6" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "ULX3S_LED7" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
|
||||
## Pushbuttons "blinkey", "flash", "power", "gpdi" sheet
|
||||
LOCATE COMP "ULX3S_RST_N" SITE "D6"; # BTN_PWRn (inverted logic)
|
||||
LOCATE COMP "btn[1]" SITE "R1"; # FIRE1
|
||||
LOCATE COMP "btn[2]" SITE "T1"; # FIRE2
|
||||
LOCATE COMP "btn[3]" SITE "R18"; # UP W1->R18
|
||||
LOCATE COMP "btn[4]" SITE "V1"; # DOWN
|
||||
LOCATE COMP "btn[5]" SITE "U1"; # LEFT
|
||||
LOCATE COMP "btn[6]" SITE "H16"; # RIGHT Y2->H16
|
||||
IOBUF PORT "ULX3S_RST_N" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "btn[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "btn[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "btn[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "btn[4]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "btn[5]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "btn[6]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
|
||||
## DIP switch "blinkey", "gpio" sheet
|
||||
LOCATE COMP "sw[0]" SITE "E8"; # SW1
|
||||
LOCATE COMP "sw[1]" SITE "D8"; # SW2
|
||||
LOCATE COMP "sw[2]" SITE "D7"; # SW3
|
||||
LOCATE COMP "sw[3]" SITE "E7"; # SW4
|
||||
IOBUF PORT "sw[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sw[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sw[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sw[3]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
|
||||
## SPI OLED DISPLAY SSD1331 (Color) or SSD1306 (B/W) "blinkey", "usb" sheet
|
||||
LOCATE COMP "oled_clk" SITE "P4";
|
||||
LOCATE COMP "oled_mosi" SITE "P3";
|
||||
LOCATE COMP "oled_dc" SITE "P1";
|
||||
LOCATE COMP "oled_resn" SITE "P2";
|
||||
LOCATE COMP "oled_csn" SITE "N2";
|
||||
IOBUF PORT "oled_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "oled_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "oled_dc" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "oled_resn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "oled_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
|
||||
## SPI Flash chip "flash" sheet
|
||||
LOCATE COMP "flash_csn" SITE "R2";
|
||||
LOCATE COMP "flash_clk" SITE "U3";
|
||||
LOCATE COMP "flash_mosi" SITE "W2";
|
||||
LOCATE COMP "flash_miso" SITE "V2";
|
||||
LOCATE COMP "flash_holdn" SITE "W1";
|
||||
LOCATE COMP "flash_wpn" SITE "Y2";
|
||||
#LOCATE COMP "flash_csspin" SITE "AJ3";
|
||||
#LOCATE COMP "flash_initn" SITE "AG4";
|
||||
#LOCATE COMP "flash_done" SITE "AJ4";
|
||||
#LOCATE COMP "flash_programn" SITE "AH4";
|
||||
#LOCATE COMP "flash_cfg_select[0]" SITE "AM4";
|
||||
#LOCATE COMP "flash_cfg_select[1]" SITE "AL4";
|
||||
#LOCATE COMP "flash_cfg_select[2]" SITE "AK4";
|
||||
IOBUF PORT "flash_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "flash_clk" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "flash_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "flash_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "flash_holdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "flash_wpn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
#IOBUF PORT "flash_csspin" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
#IOBUF PORT "flash_initn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
#IOBUF PORT "flash_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
#IOBUF PORT "flash_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
#IOBUF PORT "flash_cfg_select[0]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
#IOBUF PORT "flash_cfg_select[1]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
#IOBUF PORT "flash_cfg_select[2]" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
|
||||
## SD card "sdcard", "usb" sheet
|
||||
# wifi_gpio2,4,12,13,14,15 are shared with SD card.
|
||||
# If any of wifi_gpio2,4,12,13 is used in toplevel, don't use sd_d[].
|
||||
# If SD is used in 1-bit SPI mode, wifi_gpio4,12 = sd_d[1,2] are free,
|
||||
LOCATE COMP "sd_clk" SITE "H2"; # sd_clk WiFi_GPIO14
|
||||
LOCATE COMP "sd_cmd" SITE "J1"; # sd_cmd_di (MOSI) WiFi GPIO15
|
||||
LOCATE COMP "sd_d[0]" SITE "J3"; # sd_d0_do (MISO) WiFi GPIO2
|
||||
LOCATE COMP "sd_d[1]" SITE "H1"; # sd_d1_irq WiFi GPIO4
|
||||
LOCATE COMP "sd_d[2]" SITE "K1"; # sd_d2 WiFi_GPIO12
|
||||
LOCATE COMP "sd_d[3]" SITE "K2"; # sd_d3_csn WiFi_GPIO13
|
||||
LOCATE COMP "sd_wp" SITE "P5"; # not connected
|
||||
LOCATE COMP "sd_cdn" SITE "N5"; # not connected
|
||||
IOBUF PORT "sd_clk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sd_cmd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sd_d[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sd_d[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sd_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4; # WiFi GPIO12 pulldown bootstrapping without 3.3V efuse
|
||||
IOBUF PORT "sd_d[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sd_wp" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sd_cdn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
|
||||
## ADC SPI (MAX11123) "analog", "ram" sheet
|
||||
# input lines shared with GP,GN14-17
|
||||
LOCATE COMP "adc_csn" SITE "R17";
|
||||
LOCATE COMP "adc_mosi" SITE "R16";
|
||||
LOCATE COMP "adc_miso" SITE "U16";
|
||||
LOCATE COMP "adc_sclk" SITE "P17";
|
||||
IOBUF PORT "adc_csn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "adc_mosi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "adc_miso" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "adc_sclk" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
|
||||
## Audio 4-bit DAC "analog", "gpio" sheet
|
||||
# output impedance: 75 ohm
|
||||
# Stereo 16 ohm earphones, analog audio,
|
||||
# SPDIF digital audio and composite video.
|
||||
LOCATE COMP "audio_l[3]" SITE "B3"; # JACK TIP (left audio)
|
||||
LOCATE COMP "audio_l[2]" SITE "C3";
|
||||
LOCATE COMP "audio_l[1]" SITE "D3";
|
||||
LOCATE COMP "audio_l[0]" SITE "E4";
|
||||
LOCATE COMP "audio_r[3]" SITE "C5"; # JACK RING1 (right audio)
|
||||
LOCATE COMP "audio_r[2]" SITE "D5";
|
||||
LOCATE COMP "audio_r[1]" SITE "B5";
|
||||
LOCATE COMP "audio_r[0]" SITE "A3";
|
||||
LOCATE COMP "audio_v[3]" SITE "E5"; # JACK RING2 (video or digital audio)
|
||||
LOCATE COMP "audio_v[2]" SITE "F5";
|
||||
LOCATE COMP "audio_v[1]" SITE "F2";
|
||||
LOCATE COMP "audio_v[0]" SITE "H5";
|
||||
IOBUF PORT "audio_l[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
|
||||
IOBUF PORT "audio_l[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
|
||||
IOBUF PORT "audio_l[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
|
||||
IOBUF PORT "audio_l[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
|
||||
IOBUF PORT "audio_r[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
|
||||
IOBUF PORT "audio_r[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
|
||||
IOBUF PORT "audio_r[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
|
||||
IOBUF PORT "audio_r[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
|
||||
IOBUF PORT "audio_v[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
|
||||
IOBUF PORT "audio_v[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
|
||||
IOBUF PORT "audio_v[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
|
||||
IOBUF PORT "audio_v[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
|
||||
|
||||
## WiFi ESP-32 "wifi", "usb", "flash" sheet
|
||||
# wifi_gpio2,4,12,13,14,15 are shared with SD card.
|
||||
# If any of wifi_gpio2,4,12,13 is used in toplevel, don't use sd_d[].
|
||||
# If SD is used in 1-bit SPI mode, wifi_gpio4,12 = sd_d[1,2] are free,
|
||||
# other pins are shared with GP/GN, and JTAG
|
||||
LOCATE COMP "wifi_en" SITE "F1"; # enable/reset WiFi
|
||||
LOCATE COMP "wifi_rxd" SITE "K3"; # FPGA transmits to WiFi
|
||||
LOCATE COMP "wifi_txd" SITE "K4"; # FPGA receives from WiFi
|
||||
LOCATE COMP "wifi_gpio0" SITE "L2";
|
||||
LOCATE COMP "wifi_gpio5" SITE "N4"; # WIFI LED
|
||||
LOCATE COMP "wifi_gpio16" SITE "L1"; # Serial1 RX
|
||||
LOCATE COMP "wifi_gpio17" SITE "N3"; # Serial1 TX
|
||||
# LOCATE COMP "prog_done" SITE "Y3"; # not GPIO, always active
|
||||
# wifi lines shared with SD card
|
||||
LOCATE COMP "wifi_gpio2" SITE "J3"; # sd_d0_do (MISO) WiFi GPIO2
|
||||
LOCATE COMP "wifi_gpio4" SITE "H1"; # sd_d1_irq WiFi GPIO4
|
||||
LOCATE COMP "wifi_gpio12" SITE "K1"; # sd_d2 WiFi_GPIO12
|
||||
LOCATE COMP "wifi_gpio13" SITE "K2"; # sd_d3_csn WiFi_GPIO13
|
||||
LOCATE COMP "wifi_gpio14" SITE "H2"; # sd_clk WiFi_GPIO14
|
||||
LOCATE COMP "wifi_gpio15" SITE "J1"; # sd_cmd_di (MOSI) WiFi GPIO15
|
||||
# wifi lines shared with JTAG
|
||||
# LOCATE COMP "wifi_gpio21" SITE "U5"; # JTAG TMS
|
||||
# LOCATE COMP "wifi_gpio18" SITE "T5"; # JTAG TCK
|
||||
# LOCATE COMP "wifi_gpio23" SITE "R5"; # JTAG TDI
|
||||
# LOCATE COMP "wifi_gpio19" SITE "V4"; # JTAG TDO
|
||||
IOBUF PORT "wifi_en" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "wifi_rxd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "wifi_txd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "wifi_gpio0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "wifi_gpio5" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4; # pull down or drive 0 for esp32 programming
|
||||
IOBUF PORT "wifi_gpio16" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "wifi_gpio17" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
# IOBUF PORT "prog_done" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
|
||||
## PCB antenna 433 MHz (may be also used for FM) "usb" sheet
|
||||
LOCATE COMP "ant_433mhz" SITE "G1";
|
||||
IOBUF PORT "ant_433mhz" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
|
||||
## Second USB port "US2" going directly into FPGA "usb", "ram" sheet
|
||||
LOCATE COMP "ULX3S_USB_D_P" SITE "E16"; # single ended or differential input only
|
||||
LOCATE COMP "ULX3S_USB_D_N" SITE "F16";
|
||||
IOBUF PORT "ULX3S_USB_D_P" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=16;
|
||||
IOBUF PORT "ULX3S_USB_D_N" PULLMODE=NONE IO_TYPE=LVCMOS33D DRIVE=16;
|
||||
LOCATE COMP "usb_fpga_bd_dp" SITE "D15"; # single-ended bidirectional
|
||||
LOCATE COMP "usb_fpga_bd_dn" SITE "E15";
|
||||
IOBUF PORT "usb_fpga_bd_dp" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "usb_fpga_bd_dn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
LOCATE COMP "ULX3S_USB_DP_PU" SITE "B12"; # pull up/down control
|
||||
LOCATE COMP "ULX3S_USB_DN_PU" SITE "C12";
|
||||
IOBUF PORT "ULX3S_USB_DP_PU" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
|
||||
IOBUF PORT "ULX3S_USB_DN_PU" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=16;
|
||||
|
||||
## JTAG ESP-32 "usb" sheet
|
||||
# connected to FT231X and ESP-32
|
||||
# commented out because those are dedicated pins, not directly useable as GPIO
|
||||
# but could be used by some vendor-specific JTAG bridging (boundary scan) module
|
||||
#LOCATE COMP "jtag_tdi" SITE "R5"; # FTDI_nRI FPGA receives
|
||||
#LOCATE COMP "jtag_tdo" SITE "V4"; # FTDI_nCTS FPGA transmits
|
||||
#LOCATE COMP "jtag_tck" SITE "T5"; # FTDI_nDSR FPGA receives
|
||||
#LOCATE COMP "jtag_tms" SITE "U5"; # FTDI_nDCD FPGA receives
|
||||
#IOBUF PORT "jtag_tdi" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
#IOBUF PORT "jtag_tdo" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
#IOBUF PORT "jtag_tck" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
#IOBUF PORT "jtag_tms" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
|
||||
## SDRAM "ram" sheet
|
||||
LOCATE COMP "sdram_clk" SITE "F19";
|
||||
LOCATE COMP "sdram_cke" SITE "F20";
|
||||
LOCATE COMP "sdram_csn" SITE "P20";
|
||||
LOCATE COMP "sdram_wen" SITE "T20";
|
||||
LOCATE COMP "sdram_rasn" SITE "R20";
|
||||
LOCATE COMP "sdram_casn" SITE "T19";
|
||||
LOCATE COMP "sdram_a[0]" SITE "M20";
|
||||
LOCATE COMP "sdram_a[1]" SITE "M19";
|
||||
LOCATE COMP "sdram_a[2]" SITE "L20";
|
||||
LOCATE COMP "sdram_a[3]" SITE "L19";
|
||||
LOCATE COMP "sdram_a[4]" SITE "K20";
|
||||
LOCATE COMP "sdram_a[5]" SITE "K19";
|
||||
LOCATE COMP "sdram_a[6]" SITE "K18";
|
||||
LOCATE COMP "sdram_a[7]" SITE "J20";
|
||||
LOCATE COMP "sdram_a[8]" SITE "J19";
|
||||
LOCATE COMP "sdram_a[9]" SITE "H20";
|
||||
LOCATE COMP "sdram_a[10]" SITE "N19";
|
||||
LOCATE COMP "sdram_a[11]" SITE "G20";
|
||||
LOCATE COMP "sdram_a[12]" SITE "G19";
|
||||
LOCATE COMP "sdram_ba[0]" SITE "P19";
|
||||
LOCATE COMP "sdram_ba[1]" SITE "N20";
|
||||
LOCATE COMP "sdram_dqm[0]" SITE "U19";
|
||||
LOCATE COMP "sdram_dqm[1]" SITE "E20";
|
||||
LOCATE COMP "sdram_d[0]" SITE "J16";
|
||||
LOCATE COMP "sdram_d[1]" SITE "L18";
|
||||
LOCATE COMP "sdram_d[2]" SITE "M18";
|
||||
LOCATE COMP "sdram_d[3]" SITE "N18";
|
||||
LOCATE COMP "sdram_d[4]" SITE "P18";
|
||||
LOCATE COMP "sdram_d[5]" SITE "T18";
|
||||
LOCATE COMP "sdram_d[6]" SITE "T17";
|
||||
LOCATE COMP "sdram_d[7]" SITE "U20";
|
||||
LOCATE COMP "sdram_d[8]" SITE "E19";
|
||||
LOCATE COMP "sdram_d[9]" SITE "D20";
|
||||
LOCATE COMP "sdram_d[10]" SITE "D19";
|
||||
LOCATE COMP "sdram_d[11]" SITE "C20";
|
||||
LOCATE COMP "sdram_d[12]" SITE "E18";
|
||||
LOCATE COMP "sdram_d[13]" SITE "F18";
|
||||
LOCATE COMP "sdram_d[14]" SITE "J18";
|
||||
LOCATE COMP "sdram_d[15]" SITE "J17";
|
||||
IOBUF PORT "sdram_clk" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_cke" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_csn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_wen" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_rasn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_casn" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_a[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_a[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_a[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_a[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_a[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_a[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_a[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_a[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_a[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_a[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_a[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_a[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_a[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_ba[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_ba[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_dqm[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_dqm[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_d[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_d[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_d[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_d[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_d[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_d[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_d[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_d[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_d[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_d[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_d[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_d[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_d[12]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_d[13]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_d[14]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "sdram_d[15]" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
|
||||
# GPDI differential interface (Video) "gpdi" sheet
|
||||
LOCATE COMP "gpdi_dp[0]" SITE "A16"; # Blue +
|
||||
LOCATE COMP "gpdi_dn[0]" SITE "B16"; # Blue -
|
||||
LOCATE COMP "gpdi_dp[1]" SITE "A14"; # Green +
|
||||
LOCATE COMP "gpdi_dn[1]" SITE "C14"; # Green -
|
||||
LOCATE COMP "gpdi_dp[2]" SITE "A12"; # Red +
|
||||
LOCATE COMP "gpdi_dn[2]" SITE "A13"; # Red -
|
||||
LOCATE COMP "gpdi_dp[3]" SITE "A17"; # Clock +
|
||||
LOCATE COMP "gpdi_dn[3]" SITE "B18"; # Clock -
|
||||
LOCATE COMP "gpdi_util" SITE "A19"; # add 10k parallel to C
|
||||
LOCATE COMP "gpdi_hpd" SITE "B20"; # add 549ohm parallel to C
|
||||
LOCATE COMP "gpdi_cec" SITE "A18";
|
||||
LOCATE COMP "gpdi_sda" SITE "B19"; # I2C shared with RTC
|
||||
LOCATE COMP "gpdi_scl" SITE "E12"; # I2C shared with RTC C12->E12
|
||||
IOBUF PORT "gpdi_dp[0]" IO_TYPE=LVCMOS33D DRIVE=4;
|
||||
IOBUF PORT "gpdi_dn[0]" IO_TYPE=LVCMOS33D DRIVE=4;
|
||||
IOBUF PORT "gpdi_dp[1]" IO_TYPE=LVCMOS33D DRIVE=4;
|
||||
IOBUF PORT "gpdi_dn[1]" IO_TYPE=LVCMOS33D DRIVE=4;
|
||||
IOBUF PORT "gpdi_dp[2]" IO_TYPE=LVCMOS33D DRIVE=4;
|
||||
IOBUF PORT "gpdi_dn[2]" IO_TYPE=LVCMOS33D DRIVE=4;
|
||||
IOBUF PORT "gpdi_dp[3]" IO_TYPE=LVCMOS33D DRIVE=4;
|
||||
IOBUF PORT "gpdi_dn[3]" IO_TYPE=LVCMOS33D DRIVE=4;
|
||||
IOBUF PORT "gpdi_util" IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gpdi_hpd" IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gpdi_cec" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gpdi_sda" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gpdi_scl" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
|
||||
# GPIO (default single-ended) "gpio", "ram", "gpdi" sheet
|
||||
# Pins enumerated gp[0-27], gn[0-27].
|
||||
# With differential mode enabled on Lattice,
|
||||
# gp[] (+) are used, gn[] (-) are ignored from design
|
||||
# as they handle inverted signal by default.
|
||||
# To enable differential, rename LVCMOS33->LVCMOS33D
|
||||
# FEMALE ANGLED (90 deg PMOD) on TOP or
|
||||
# MALE VERTICAL ( 0 deg pins) on BOTTOM and flat cable
|
||||
LOCATE COMP "gp[0]" SITE "B11"; # PCLK
|
||||
LOCATE COMP "gn[0]" SITE "C11"; # PCLK
|
||||
LOCATE COMP "gp[1]" SITE "A10"; # PCLK
|
||||
LOCATE COMP "gn[1]" SITE "A11"; # PCLK
|
||||
LOCATE COMP "gp[2]" SITE "A9"; # GR_PCLK
|
||||
LOCATE COMP "gn[2]" SITE "B10"; # GR_PCLK
|
||||
LOCATE COMP "gp[3]" SITE "B9";
|
||||
LOCATE COMP "gn[3]" SITE "C10";
|
||||
LOCATE COMP "gp[4]" SITE "A7";
|
||||
LOCATE COMP "gn[4]" SITE "A8";
|
||||
LOCATE COMP "gp[5]" SITE "C8";
|
||||
LOCATE COMP "gn[5]" SITE "B8";
|
||||
LOCATE COMP "gp[6]" SITE "C6";
|
||||
LOCATE COMP "gn[6]" SITE "C7";
|
||||
IOBUF PORT "gp[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
LOCATE COMP "gp[7]" SITE "A6";
|
||||
LOCATE COMP "gn[7]" SITE "B6";
|
||||
LOCATE COMP "gp[8]" SITE "A4"; # DIFF
|
||||
LOCATE COMP "gn[8]" SITE "A5"; # DIFF
|
||||
LOCATE COMP "gp[9]" SITE "A2"; # DIFF
|
||||
LOCATE COMP "gn[9]" SITE "B1"; # DIFF
|
||||
LOCATE COMP "gp[10]" SITE "C4"; # DIFF
|
||||
LOCATE COMP "gn[10]" SITE "B4"; # DIFF
|
||||
LOCATE COMP "gp[11]" SITE "F4"; # DIFF wifi_gpio26
|
||||
LOCATE COMP "gn[11]" SITE "E3"; # DIFF wifi_gpio25
|
||||
LOCATE COMP "gp[12]" SITE "G3"; # DIFF wifi_gpio33 PCLK
|
||||
LOCATE COMP "gn[12]" SITE "F3"; # DIFF wifi_gpio32 PCLK
|
||||
LOCATE COMP "gp[13]" SITE "H4"; # DIFF wifi_gpio35
|
||||
LOCATE COMP "gn[13]" SITE "G5"; # DIFF wifi_gpio34
|
||||
IOBUF PORT "gp[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[8]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[9]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[10]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[11]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[12]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[12]" PULLMODE=NONE IO_TYPE=LVCMOS33;
|
||||
FREQUENCY PORT "gn[12]" 50 MHZ;
|
||||
IOBUF PORT "gp[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[13]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
LOCATE COMP "gp[14]" SITE "U18"; # DIFF ADC AIN1
|
||||
LOCATE COMP "gn[14]" SITE "U17"; # DIFF ADC AIN0
|
||||
LOCATE COMP "gp[15]" SITE "N17"; # DIFF ADC AIN3
|
||||
LOCATE COMP "gn[15]" SITE "P16"; # DIFF ADC AIN2
|
||||
LOCATE COMP "gp[16]" SITE "N16"; # DIFF ADC AIN5
|
||||
LOCATE COMP "gn[16]" SITE "M17"; # DIFF ADC AIN4
|
||||
LOCATE COMP "gp[17]" SITE "L16"; # DIFF ADC AIN7 GR_PCLK
|
||||
LOCATE COMP "gn[17]" SITE "L17"; # DIFF ADC AIN6
|
||||
LOCATE COMP "gp[18]" SITE "H18"; # DIFF
|
||||
LOCATE COMP "gn[18]" SITE "H17"; # DIFF
|
||||
LOCATE COMP "gp[19]" SITE "F17"; # DIFF
|
||||
LOCATE COMP "gn[19]" SITE "G18"; # DIFF
|
||||
LOCATE COMP "gp[20]" SITE "D18"; # DIFF
|
||||
LOCATE COMP "gn[20]" SITE "E17"; # DIFF
|
||||
IOBUF PORT "gp[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[14]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[15]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[16]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[17]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[18]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[19]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[20]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
LOCATE COMP "gp[21]" SITE "C18"; # DIFF
|
||||
LOCATE COMP "gn[21]" SITE "D17"; # DIFF
|
||||
LOCATE COMP "gp[22]" SITE "B15";
|
||||
LOCATE COMP "gn[22]" SITE "C15";
|
||||
LOCATE COMP "gp[23]" SITE "B17";
|
||||
LOCATE COMP "gn[23]" SITE "C17";
|
||||
LOCATE COMP "gp[24]" SITE "C16";
|
||||
LOCATE COMP "gn[24]" SITE "D16";
|
||||
LOCATE COMP "gp[25]" SITE "D14";
|
||||
LOCATE COMP "gn[25]" SITE "E14";
|
||||
LOCATE COMP "gp[26]" SITE "B13";
|
||||
LOCATE COMP "gn[26]" SITE "C13";
|
||||
LOCATE COMP "gp[27]" SITE "D13";
|
||||
LOCATE COMP "gn[27]" SITE "E13";
|
||||
IOBUF PORT "gp[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[21]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[22]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[23]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[24]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[25]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[26]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn[27]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
|
||||
## GPIO repeated as individual signals (non-vector)
|
||||
# Allows mixed input, output, bidirectional, clock, differential
|
||||
# If any of individual gp is used, then don't use gp[] vector.
|
||||
# Same for gn and gn[].
|
||||
# FEMALE ANGLED (90 deg PMOD) on TOP or
|
||||
# MALE VERTICAL ( 0 deg pins) on BOTTOM and flat cable
|
||||
LOCATE COMP "gp0" SITE "B11"; # PCLK
|
||||
LOCATE COMP "gn0" SITE "C11"; # PCLK
|
||||
LOCATE COMP "gp1" SITE "A10"; # PCLK
|
||||
LOCATE COMP "gn1" SITE "A11"; # PCLK
|
||||
LOCATE COMP "gp2" SITE "A9"; # GR_PCLK
|
||||
LOCATE COMP "gn2" SITE "B10"; # GR_PCLK
|
||||
LOCATE COMP "gp3" SITE "B9";
|
||||
LOCATE COMP "gn3" SITE "C10";
|
||||
LOCATE COMP "gp4" SITE "A7";
|
||||
LOCATE COMP "gn4" SITE "A8";
|
||||
LOCATE COMP "gp5" SITE "C8";
|
||||
LOCATE COMP "gn5" SITE "B8";
|
||||
LOCATE COMP "gp6" SITE "C6";
|
||||
LOCATE COMP "gn6" SITE "C7";
|
||||
IOBUF PORT "gp0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp1" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn1" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp2" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn2" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp3" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn3" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp4" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn4" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp5" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn5" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp6" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn6" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
LOCATE COMP "gp7" SITE "A6";
|
||||
LOCATE COMP "gn7" SITE "B6";
|
||||
LOCATE COMP "gp8" SITE "A4"; # DIFF
|
||||
LOCATE COMP "gn8" SITE "A5"; # DIFF
|
||||
LOCATE COMP "gp9" SITE "A2"; # DIFF
|
||||
LOCATE COMP "gn9" SITE "B1"; # DIFF
|
||||
LOCATE COMP "gp10" SITE "C4"; # DIFF
|
||||
LOCATE COMP "gn10" SITE "B4"; # DIFF
|
||||
LOCATE COMP "gp11" SITE "F4"; # DIFF wifi_gpio26
|
||||
LOCATE COMP "gn11" SITE "E3"; # DIFF wifi_gpio25
|
||||
LOCATE COMP "gp12" SITE "G3"; # DIFF wifi_gpio33 PCLK
|
||||
LOCATE COMP "gn12" SITE "F3"; # DIFF wifi_gpio32 PCLK
|
||||
LOCATE COMP "gp13" SITE "H4"; # DIFF wifi_gpio35
|
||||
LOCATE COMP "gn13" SITE "G5"; # DIFF wifi_gpio34
|
||||
# wifi sharing PCB v2.0.6-v3.0.8
|
||||
# prior to v2.0.6 see schematics
|
||||
IOBUF PORT "gp7" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn7" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp8" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn8" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp9" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn9" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp10" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn10" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp11" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn11" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp12" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn12" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
FREQUENCY PORT "gn12" 50 MHZ;
|
||||
IOBUF PORT "gp13" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn13" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
LOCATE COMP "gp14" SITE "U18"; # DIFF ADC AIN1
|
||||
LOCATE COMP "gn14" SITE "U17"; # DIFF ADC AIN0
|
||||
LOCATE COMP "gp15" SITE "N17"; # DIFF ADC AIN3
|
||||
LOCATE COMP "gn15" SITE "P16"; # DIFF ADC AIN2
|
||||
LOCATE COMP "gp16" SITE "N16"; # DIFF ADC AIN5
|
||||
LOCATE COMP "gn16" SITE "M17"; # DIFF ADC AIN4
|
||||
LOCATE COMP "gp17" SITE "L16"; # DIFF ADC AIN7 GR_PCLK
|
||||
LOCATE COMP "gn17" SITE "L17"; # DIFF ADC AIN6
|
||||
LOCATE COMP "gp18" SITE "H18"; # DIFF
|
||||
LOCATE COMP "gn18" SITE "H17"; # DIFF
|
||||
LOCATE COMP "gp19" SITE "F17"; # DIFF
|
||||
LOCATE COMP "gn19" SITE "G18"; # DIFF
|
||||
LOCATE COMP "gp20" SITE "D18"; # DIFF
|
||||
LOCATE COMP "gn20" SITE "E17"; # DIFF
|
||||
IOBUF PORT "gp14" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn14" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp15" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn15" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp16" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn16" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp17" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn17" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp18" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn18" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp19" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn19" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp20" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn20" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
LOCATE COMP "gp21" SITE "C18"; # DIFF
|
||||
LOCATE COMP "gn21" SITE "D17"; # DIFF
|
||||
LOCATE COMP "gp22" SITE "B15";
|
||||
LOCATE COMP "gn22" SITE "C15";
|
||||
LOCATE COMP "gp23" SITE "B17";
|
||||
LOCATE COMP "gn23" SITE "C17";
|
||||
LOCATE COMP "gp24" SITE "C16";
|
||||
LOCATE COMP "gn24" SITE "D16";
|
||||
LOCATE COMP "gp25" SITE "D14";
|
||||
LOCATE COMP "gn25" SITE "E14";
|
||||
LOCATE COMP "gp26" SITE "B13";
|
||||
LOCATE COMP "gn26" SITE "C13";
|
||||
LOCATE COMP "gp27" SITE "D13";
|
||||
LOCATE COMP "gn27" SITE "E13";
|
||||
IOBUF PORT "gp21" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn21" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp22" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn22" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp23" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn23" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp24" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn24" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp25" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn25" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp26" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn26" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gp27" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
IOBUF PORT "gn27" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
|
||||
## PROGRAMN (reload bitstream from FLASH, exit from bootloader)
|
||||
# PCB v2.0.5 and higher
|
||||
LOCATE COMP "user_programn" SITE "M4";
|
||||
IOBUF PORT "user_programn" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
|
||||
## SHUTDOWN "power", "ram" sheet (connected from PCB v1.7.5)
|
||||
# on PCB v1.7 shutdown is not connected to FPGA
|
||||
LOCATE COMP "shutdown" SITE "G16"; # FPGA receives
|
||||
IOBUF PORT "shutdown" PULLMODE=DOWN IO_TYPE=LVCMOS33 DRIVE=4;
|
||||
36
Libs/RiscV/NEORV32/setups/osflow/constraints/UPduino_v3.pcf
Normal file
36
Libs/RiscV/NEORV32/setups/osflow/constraints/UPduino_v3.pcf
Normal file
@ -0,0 +1,36 @@
|
||||
## UART (uart0)
|
||||
set_io uart_txd_o 38
|
||||
set_io uart_rxd_i 28
|
||||
|
||||
## SPI - on-board flash
|
||||
set_io flash_sdo_o 14
|
||||
set_io flash_sck_o 15
|
||||
set_io flash_csn_o 16
|
||||
set_io flash_sdi_i 17
|
||||
|
||||
## SPI - user port
|
||||
set_io spi_sdo_o 34
|
||||
set_io spi_sck_o 43
|
||||
set_io spi_csn_o 36
|
||||
set_io spi_sdi_i 42
|
||||
|
||||
## TWI
|
||||
set_io twi_sda_io 31
|
||||
set_io twi_scl_io 37
|
||||
|
||||
## GPIO - input
|
||||
set_io gpio_i[0] 44
|
||||
set_io gpio_i[1] 4
|
||||
set_io gpio_i[2] 3
|
||||
set_io gpio_i[3] 48
|
||||
|
||||
## GPIO - output
|
||||
set_io gpio_o[0] 45
|
||||
set_io gpio_o[1] 47
|
||||
set_io gpio_o[2] 46
|
||||
set_io gpio_o[3] 2
|
||||
|
||||
## RGB power LED
|
||||
set_io pwm_o[0] 39
|
||||
set_io pwm_o[1] 40
|
||||
set_io pwm_o[2] 41
|
||||
39
Libs/RiscV/NEORV32/setups/osflow/constraints/iCEBreaker.pcf
Normal file
39
Libs/RiscV/NEORV32/setups/osflow/constraints/iCEBreaker.pcf
Normal file
@ -0,0 +1,39 @@
|
||||
## UART (uart0)
|
||||
set_io uart_txd_o 9
|
||||
set_io uart_rxd_i 6
|
||||
|
||||
## SPI - on-board flash
|
||||
set_io flash_sdo_o 14
|
||||
set_io flash_sck_o 15
|
||||
set_io flash_csn_o 16
|
||||
set_io flash_sdi_i 17
|
||||
|
||||
## SPI - user port
|
||||
set_io spi_sdo_o 43
|
||||
set_io spi_sck_o 38
|
||||
set_io spi_csn_o 34
|
||||
set_io spi_sdi_i 31
|
||||
|
||||
## TWI
|
||||
set_io twi_sda_io 2
|
||||
set_io twi_scl_io 4
|
||||
|
||||
## GPIO - input
|
||||
set_io gpio_i[0] 18
|
||||
set_io gpio_i[1] 19
|
||||
set_io gpio_i[2] 20
|
||||
set_io gpio_i[3] 28
|
||||
|
||||
## GPIO - output
|
||||
set_io gpio_o[0] 25
|
||||
set_io gpio_o[1] 26
|
||||
set_io gpio_o[2] 27
|
||||
set_io gpio_o[3] 23
|
||||
|
||||
## RGB power LED
|
||||
set_io pwm_o[0] 39
|
||||
set_io pwm_o[1] 40
|
||||
set_io pwm_o[2] 41
|
||||
|
||||
#User Reset Btn
|
||||
set_io user_reset_btn 10
|
||||
69
Libs/RiscV/NEORV32/setups/osflow/constraints/iCESugar.pcf
Normal file
69
Libs/RiscV/NEORV32/setups/osflow/constraints/iCESugar.pcf
Normal file
@ -0,0 +1,69 @@
|
||||
#| iCESugar-v1.5
|
||||
|
||||
|
||||
#> Clock (12 MHz)
|
||||
set_io --warn-no-port iCESugarv15_CLK 35
|
||||
|
||||
|
||||
#> Tri-colour LED
|
||||
set_io --warn-no-port iCESugarv15_LED_G 41
|
||||
set_io --warn-no-port iCESugarv15_LED_R 40
|
||||
set_io --warn-no-port iCESugarv15_LED_B 39
|
||||
|
||||
|
||||
#> UART
|
||||
set_io --warn-no-port iCESugarv15_RX 4
|
||||
set_io --warn-no-port iCESugarv15_TX 6
|
||||
|
||||
|
||||
#> USB
|
||||
set_io --warn-no-port iCESugarv15_USB_DN 9
|
||||
set_io --warn-no-port iCESugarv15_USB_DP 10
|
||||
set_io --warn-no-port iCESugarv15_USB_DP_PU 11
|
||||
|
||||
|
||||
#> PMOD 1
|
||||
set_io --warn-no-port iCESugarv15_PMOD1A_0 10
|
||||
set_io --warn-no-port iCESugarv15_PMOD1A_1 6
|
||||
set_io --warn-no-port iCESugarv15_PMOD1A_2 3
|
||||
set_io --warn-no-port iCESugarv15_PMOD1A_3 48
|
||||
set_io --warn-no-port iCESugarv15_PMOD1B_0 47
|
||||
set_io --warn-no-port iCESugarv15_PMOD1B_1 2
|
||||
set_io --warn-no-port iCESugarv15_PMOD1B_2 4
|
||||
set_io --warn-no-port iCESugarv15_PMOD1B_3 9
|
||||
|
||||
|
||||
#> PMOD 2
|
||||
set_io --warn-no-port iCESugarv15_PMOD2A_0 46
|
||||
set_io --warn-no-port iCESugarv15_PMOD2A_1 44
|
||||
set_io --warn-no-port iCESugarv15_PMOD2A_2 42
|
||||
set_io --warn-no-port iCESugarv15_PMOD2A_3 37
|
||||
set_io --warn-no-port iCESugarv15_PMOD2B_0 36
|
||||
set_io --warn-no-port iCESugarv15_PMOD2B_1 38
|
||||
set_io --warn-no-port iCESugarv15_PMOD2B_2 43
|
||||
set_io --warn-no-port iCESugarv15_PMOD2B_3 45
|
||||
|
||||
|
||||
#> PMOD 3
|
||||
set_io --warn-no-port iCESugarv15_PMOD3A_0 34
|
||||
set_io --warn-no-port iCESugarv15_PMOD3A_1 31
|
||||
set_io --warn-no-port iCESugarv15_PMOD3A_2 27
|
||||
set_io --warn-no-port iCESugarv15_PMOD3A_3 25
|
||||
set_io --warn-no-port iCESugarv15_PMOD3B_0 23
|
||||
set_io --warn-no-port iCESugarv15_PMOD3B_1 26
|
||||
set_io --warn-no-port iCESugarv15_PMOD3B_2 28
|
||||
set_io --warn-no-port iCESugarv15_PMOD3B_3 32
|
||||
|
||||
|
||||
#> PMOD 4 | Switches
|
||||
set_io --warn-no-port iCESugarv15_PMOD4_0 21
|
||||
set_io --warn-no-port iCESugarv15_PMOD4_1 20
|
||||
set_io --warn-no-port iCESugarv15_PMOD4_2 19
|
||||
set_io --warn-no-port iCESugarv15_PMOD4_3 18
|
||||
|
||||
|
||||
#> SPI
|
||||
set_io --warn-no-port iCESugarv15_SPI_SS 16
|
||||
set_io --warn-no-port iCESugarv15_SPI_SCK 15
|
||||
set_io --warn-no-port iCESugarv15_SPI_MOSI 17
|
||||
set_io --warn-no-port iCESugarv15_SPI_MISO 14
|
||||
@ -0,0 +1,75 @@
|
||||
library ieee ;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
package components is
|
||||
|
||||
-- Yosys wrapper components
|
||||
|
||||
component EHXPLLL
|
||||
generic
|
||||
(
|
||||
CLKI_DIV : integer := 1;
|
||||
CLKFB_DIV : integer := 1;
|
||||
CLKOP_DIV : integer := 8;
|
||||
CLKOS_DIV : integer := 8;
|
||||
CLKOS2_DIV : integer := 8;
|
||||
CLKOS3_DIV : integer := 8;
|
||||
CLKOP_ENABLE : string := "ENABLED";
|
||||
CLKOS_ENABLE : string := "DISABLED";
|
||||
CLKOS2_ENABLE : string := "DISABLED";
|
||||
CLKOS3_ENABLE : string := "DISABLED";
|
||||
CLKOP_CPHASE : integer := 0;
|
||||
CLKOS_CPHASE : integer := 0;
|
||||
CLKOS2_CPHASE : integer := 0;
|
||||
CLKOS3_CPHASE : integer := 0;
|
||||
CLKOP_FPHASE : integer := 0;
|
||||
CLKOS_FPHASE : integer := 0;
|
||||
CLKOS2_FPHASE : integer := 0;
|
||||
CLKOS3_FPHASE : integer := 0;
|
||||
FEEDBK_PATH : string := "CLKOP";
|
||||
CLKOP_TRIM_POL : string := "RISING";
|
||||
CLKOP_TRIM_DELAY : integer := 0;
|
||||
CLKOS_TRIM_POL : string := "RISING";
|
||||
CLKOS_TRIM_DELAY : integer := 0;
|
||||
OUTDIVIDER_MUXA : string := "DIVA";
|
||||
OUTDIVIDER_MUXB : string := "DIVB";
|
||||
OUTDIVIDER_MUXC : string := "DIVC";
|
||||
OUTDIVIDER_MUXD : string := "DIVD";
|
||||
PLL_LOCK_MODE : integer := 0;
|
||||
PLL_LOCK_DELAY : integer := 200;
|
||||
STDBY_ENABLE : string := "DISABLED";
|
||||
REFIN_RESET : string := "DISABLED";
|
||||
SYNC_ENABLE : string := "DISABLED";
|
||||
INT_LOCK_STICKY : string := "ENABLED";
|
||||
DPHASE_SOURCE : string := "DISABLED";
|
||||
PLLRST_ENA : string := "DISABLED";
|
||||
INTFB_WAKE : string := "DISABLED"
|
||||
);
|
||||
port
|
||||
(
|
||||
CLKI : IN std_logic := 'X';
|
||||
CLKFB : IN std_logic := 'X';
|
||||
RST : IN std_logic := 'X';
|
||||
STDBY : IN std_logic := 'X';
|
||||
PLLWAKESYNC : IN std_logic := 'X';
|
||||
PHASESEL1 : IN std_logic := 'X';
|
||||
PHASESEL0 : IN std_logic := 'X';
|
||||
PHASEDIR : IN std_logic := 'X';
|
||||
PHASESTEP : IN std_logic := 'X';
|
||||
PHASELOADREG : IN std_logic := 'X';
|
||||
ENCLKOP : IN std_logic := 'X';
|
||||
ENCLKOS : IN std_logic := 'X';
|
||||
ENCLKOS2 : IN std_logic := 'X';
|
||||
ENCLKOS3 : IN std_logic := 'X';
|
||||
CLKOP : OUT std_logic := 'X';
|
||||
CLKOS : OUT std_logic := 'X';
|
||||
CLKOS2 : OUT std_logic := 'X';
|
||||
CLKOS3 : OUT std_logic := 'X';
|
||||
LOCK : OUT std_logic := 'X';
|
||||
INTLOCK : OUT std_logic := 'X';
|
||||
REFCLK : OUT std_logic := 'X';
|
||||
CLKINTFB : OUT std_logic := 'X'
|
||||
);
|
||||
end component;
|
||||
|
||||
end package;
|
||||
@ -0,0 +1,145 @@
|
||||
-- #################################################################################################
|
||||
-- # << NEORV32 - Processor-Internal DMEM for Lattice iCE40 UltraPlus >> #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # Memory has a physical size of 64kb (2 x SPRAMs). #
|
||||
-- # Logical size DMEM_SIZE must be less or equal. #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # BSD 3-Clause License #
|
||||
-- # #
|
||||
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
|
||||
-- # #
|
||||
-- # Redistribution and use in source and binary forms, with or without modification, are #
|
||||
-- # permitted provided that the following conditions are met: #
|
||||
-- # #
|
||||
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
|
||||
-- # conditions and the following disclaimer. #
|
||||
-- # #
|
||||
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
|
||||
-- # conditions and the following disclaimer in the documentation and/or other materials #
|
||||
-- # provided with the distribution. #
|
||||
-- # #
|
||||
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
|
||||
-- # endorse or promote products derived from this software without specific prior written #
|
||||
-- # permission. #
|
||||
-- # #
|
||||
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
|
||||
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
|
||||
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
|
||||
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
|
||||
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
|
||||
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
|
||||
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
|
||||
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
|
||||
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
|
||||
-- #################################################################################################
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library neorv32;
|
||||
use neorv32.neorv32_package.all;
|
||||
|
||||
library iCE40;
|
||||
use iCE40.components.all;
|
||||
|
||||
architecture neorv32_dmem_rtl of neorv32_dmem is
|
||||
|
||||
-- advanced configuration --------------------------------------------------------------------------------
|
||||
constant spram_sleep_mode_en_c : boolean := false; -- put DMEM into sleep mode when idle (for low power)
|
||||
-- -------------------------------------------------------------------------------------------------------
|
||||
|
||||
-- IO space: module base address --
|
||||
constant hi_abb_c : natural := 31; -- high address boundary bit
|
||||
constant lo_abb_c : natural := index_size_f(64*1024); -- low address boundary bit
|
||||
|
||||
-- local signals --
|
||||
signal acc_en : std_ulogic;
|
||||
signal mem_cs : std_ulogic;
|
||||
signal rdata : std_ulogic_vector(31 downto 0);
|
||||
signal rden : std_ulogic;
|
||||
|
||||
-- SPRAM signals --
|
||||
signal spram_clk : std_logic;
|
||||
signal spram_addr : std_logic_vector(13 downto 0);
|
||||
signal spram_di_lo : std_logic_vector(15 downto 0);
|
||||
signal spram_di_hi : std_logic_vector(15 downto 0);
|
||||
signal spram_do_lo : std_logic_vector(15 downto 0);
|
||||
signal spram_do_hi : std_logic_vector(15 downto 0);
|
||||
signal spram_be_lo : std_logic_vector(03 downto 0);
|
||||
signal spram_be_hi : std_logic_vector(03 downto 0);
|
||||
signal spram_we : std_logic;
|
||||
signal spram_pwr_n : std_logic;
|
||||
signal spram_cs : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
-- Sanity Checks --------------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
assert false report "NEORV32 PROCESSOR CONFIG NOTE: Using iCE40up SPRAM-based DMEM." severity note;
|
||||
assert not (DMEM_SIZE > 64*1024) report "NEORV32 PROCESSOR CONFIG ERROR: DMEM has a fixed physical size of 64kB. Logical size must be less or equal." severity error;
|
||||
|
||||
|
||||
-- Access Control -------------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = DMEM_BASE(hi_abb_c downto lo_abb_c)) else '0';
|
||||
mem_cs <= acc_en and (rden_i or wren_i);
|
||||
|
||||
|
||||
-- Memory Access --------------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
imem_spram_lo_inst : SB_SPRAM256KA
|
||||
port map (
|
||||
ADDRESS => spram_addr, -- I
|
||||
DATAIN => spram_di_lo, -- I
|
||||
MASKWREN => spram_be_lo, -- I
|
||||
WREN => spram_we, -- I
|
||||
CHIPSELECT => spram_cs, -- I
|
||||
CLOCK => spram_clk, -- I
|
||||
STANDBY => '0', -- I
|
||||
SLEEP => spram_pwr_n, -- I
|
||||
POWEROFF => '1', -- I
|
||||
DATAOUT => spram_do_lo -- O
|
||||
);
|
||||
|
||||
imem_spram_hi_inst : SB_SPRAM256KA
|
||||
port map (
|
||||
ADDRESS => spram_addr, -- I
|
||||
DATAIN => spram_di_hi, -- I
|
||||
MASKWREN => spram_be_hi, -- I
|
||||
WREN => spram_we, -- I
|
||||
CHIPSELECT => spram_cs, -- I
|
||||
CLOCK => spram_clk, -- I
|
||||
STANDBY => '0', -- I
|
||||
SLEEP => spram_pwr_n, -- I
|
||||
POWEROFF => '1', -- I
|
||||
DATAOUT => spram_do_hi -- O
|
||||
);
|
||||
|
||||
-- access logic and signal type conversion --
|
||||
spram_clk <= std_logic(clk_i);
|
||||
spram_addr <= std_logic_vector(addr_i(13+2 downto 0+2));
|
||||
spram_di_lo <= std_logic_vector(data_i(15 downto 00));
|
||||
spram_di_hi <= std_logic_vector(data_i(31 downto 16));
|
||||
spram_we <= '1' when ((acc_en and wren_i) = '1') else '0'; -- global write enable
|
||||
spram_cs <= std_logic(mem_cs);
|
||||
spram_be_lo <= std_logic(ben_i(1)) & std_logic(ben_i(1)) & std_logic(ben_i(0)) & std_logic(ben_i(0)); -- low byte write enable
|
||||
spram_be_hi <= std_logic(ben_i(3)) & std_logic(ben_i(3)) & std_logic(ben_i(2)) & std_logic(ben_i(2)); -- high byte write enable
|
||||
spram_pwr_n <= '0' when ((spram_sleep_mode_en_c = false) or (mem_cs = '1')) else '1'; -- LP mode disabled or IMEM selected
|
||||
rdata <= std_ulogic_vector(spram_do_hi) & std_ulogic_vector(spram_do_lo);
|
||||
|
||||
buffer_ff: process(clk_i)
|
||||
begin
|
||||
if rising_edge(clk_i) then
|
||||
ack_o <= mem_cs;
|
||||
rden <= acc_en and rden_i;
|
||||
end if;
|
||||
end process buffer_ff;
|
||||
|
||||
-- output gate --
|
||||
data_o <= rdata when (rden = '1') else (others => '0');
|
||||
|
||||
|
||||
end neorv32_dmem_rtl;
|
||||
@ -0,0 +1,146 @@
|
||||
-- #################################################################################################
|
||||
-- # << NEORV32 - Processor-Internal IMEM for Lattice iCE40 UltraPlus >> #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # Memory has a physical size of 64kb (2 x SPRAMs). #
|
||||
-- # Logical size IMEM_SIZE must be less or equal. #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # BSD 3-Clause License #
|
||||
-- # #
|
||||
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
|
||||
-- # #
|
||||
-- # Redistribution and use in source and binary forms, with or without modification, are #
|
||||
-- # permitted provided that the following conditions are met: #
|
||||
-- # #
|
||||
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
|
||||
-- # conditions and the following disclaimer. #
|
||||
-- # #
|
||||
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
|
||||
-- # conditions and the following disclaimer in the documentation and/or other materials #
|
||||
-- # provided with the distribution. #
|
||||
-- # #
|
||||
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
|
||||
-- # endorse or promote products derived from this software without specific prior written #
|
||||
-- # permission. #
|
||||
-- # #
|
||||
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
|
||||
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
|
||||
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
|
||||
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
|
||||
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
|
||||
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
|
||||
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
|
||||
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
|
||||
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
|
||||
-- #################################################################################################
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library neorv32;
|
||||
use neorv32.neorv32_package.all;
|
||||
|
||||
library iCE40;
|
||||
use iCE40.components.all;
|
||||
|
||||
architecture neorv32_imem_rtl of neorv32_imem is
|
||||
|
||||
-- advanced configuration --------------------------------------------------------------------------------
|
||||
constant spram_sleep_mode_en_c : boolean := false; -- put IMEM into sleep mode when idle (for low power)
|
||||
-- -------------------------------------------------------------------------------------------------------
|
||||
|
||||
-- IO space: module base address --
|
||||
constant hi_abb_c : natural := 31; -- high address boundary bit
|
||||
constant lo_abb_c : natural := index_size_f(64*1024); -- low address boundary bit
|
||||
|
||||
-- local signals --
|
||||
signal acc_en : std_ulogic;
|
||||
signal mem_cs : std_ulogic;
|
||||
signal rdata : std_ulogic_vector(31 downto 0);
|
||||
signal rden : std_ulogic;
|
||||
|
||||
-- SPRAM signals --
|
||||
signal spram_clk : std_logic;
|
||||
signal spram_addr : std_logic_vector(13 downto 0);
|
||||
signal spram_di_lo : std_logic_vector(15 downto 0);
|
||||
signal spram_di_hi : std_logic_vector(15 downto 0);
|
||||
signal spram_do_lo : std_logic_vector(15 downto 0);
|
||||
signal spram_do_hi : std_logic_vector(15 downto 0);
|
||||
signal spram_be_lo : std_logic_vector(03 downto 0);
|
||||
signal spram_be_hi : std_logic_vector(03 downto 0);
|
||||
signal spram_we : std_logic;
|
||||
signal spram_pwr_n : std_logic;
|
||||
signal spram_cs : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
-- Sanity Checks --------------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
assert false report "NEORV32 PROCESSOR CONFIG NOTE: Using iCE40up SPRAM-based IMEM." severity note;
|
||||
assert not (IMEM_AS_IROM = true) report "NEORV32 PROCESSOR CONFIG ERROR: ICE40 Ultra Plus SPRAM cannot be initialized by bitstream!" severity failure;
|
||||
assert not (IMEM_SIZE > 64*1024) report "NEORV32 PROCESSOR CONFIG ERROR: IMEM has a fixed physical size of 64kB. Logical size must be less or equal." severity error;
|
||||
|
||||
|
||||
-- Access Control -------------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = IMEM_BASE(hi_abb_c downto lo_abb_c)) else '0';
|
||||
mem_cs <= acc_en and (rden_i or wren_i);
|
||||
|
||||
|
||||
-- Memory Access --------------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
imem_spram_lo_inst : SB_SPRAM256KA
|
||||
port map (
|
||||
ADDRESS => spram_addr, -- I
|
||||
DATAIN => spram_di_lo, -- I
|
||||
MASKWREN => spram_be_lo, -- I
|
||||
WREN => spram_we, -- I
|
||||
CHIPSELECT => spram_cs, -- I
|
||||
CLOCK => spram_clk, -- I
|
||||
STANDBY => '0', -- I
|
||||
SLEEP => spram_pwr_n, -- I
|
||||
POWEROFF => '1', -- I
|
||||
DATAOUT => spram_do_lo -- O
|
||||
);
|
||||
|
||||
imem_spram_hi_inst : SB_SPRAM256KA
|
||||
port map (
|
||||
ADDRESS => spram_addr, -- I
|
||||
DATAIN => spram_di_hi, -- I
|
||||
MASKWREN => spram_be_hi, -- I
|
||||
WREN => spram_we, -- I
|
||||
CHIPSELECT => spram_cs, -- I
|
||||
CLOCK => spram_clk, -- I
|
||||
STANDBY => '0', -- I
|
||||
SLEEP => spram_pwr_n, -- I
|
||||
POWEROFF => '1', -- I
|
||||
DATAOUT => spram_do_hi -- O
|
||||
);
|
||||
|
||||
-- access logic and signal type conversion --
|
||||
spram_clk <= std_logic(clk_i);
|
||||
spram_addr <= std_logic_vector(addr_i(13+2 downto 0+2));
|
||||
spram_di_lo <= std_logic_vector(data_i(15 downto 00));
|
||||
spram_di_hi <= std_logic_vector(data_i(31 downto 16));
|
||||
spram_we <= '1' when ((acc_en and wren_i) = '1') else '0'; -- global write enable
|
||||
spram_cs <= std_logic(mem_cs);
|
||||
spram_be_lo <= std_logic(ben_i(1)) & std_logic(ben_i(1)) & std_logic(ben_i(0)) & std_logic(ben_i(0)); -- low byte write enable
|
||||
spram_be_hi <= std_logic(ben_i(3)) & std_logic(ben_i(3)) & std_logic(ben_i(2)) & std_logic(ben_i(2)); -- high byte write enable
|
||||
spram_pwr_n <= '0' when ((spram_sleep_mode_en_c = false) or (mem_cs = '1')) else '1'; -- LP mode disabled or IMEM selected
|
||||
rdata <= std_ulogic_vector(spram_do_hi) & std_ulogic_vector(spram_do_lo);
|
||||
|
||||
buffer_ff: process(clk_i)
|
||||
begin
|
||||
if rising_edge(clk_i) then
|
||||
ack_o <= mem_cs;
|
||||
rden <= acc_en and rden_i;
|
||||
end if;
|
||||
end process buffer_ff;
|
||||
|
||||
-- output gate --
|
||||
data_o <= rdata when (rden = '1') else (others => '0');
|
||||
|
||||
|
||||
end neorv32_imem_rtl;
|
||||
@ -0,0 +1,126 @@
|
||||
library ieee ;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
package components is
|
||||
|
||||
-- Yosys / IceCube wrapper components
|
||||
|
||||
component SB_GB
|
||||
port(
|
||||
GLOBAL_BUFFER_OUTPUT : out std_logic;
|
||||
USER_SIGNAL_TO_GLOBAL_BUFFER : in std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component SB_HFOSC
|
||||
generic (
|
||||
CLKHF_DIV : string
|
||||
);
|
||||
port (
|
||||
CLKHFPU : in std_logic;
|
||||
CLKHFEN : in std_logic;
|
||||
CLKHF : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component SB_PLL40_CORE is
|
||||
generic (
|
||||
FEEDBACK_PATH : string := "SIMPLE";
|
||||
DELAY_ADJUSTMENT_MODE_FEEDBACK : string := "FIXED";
|
||||
DELAY_ADJUSTMENT_MODE_RELATIVE : string := "FIXED";
|
||||
SHIFTREG_DIV_MODE : std_logic := '0';
|
||||
FDA_FEEDBACK : std_logic_vector(3 downto 0) := x"0";
|
||||
FDA_RELATIVE : std_logic_vector(3 downto 0) := x"0";
|
||||
PLLOUT_SELECT : string := "GENCLK";
|
||||
DIVR : std_logic_vector(3 downto 0) := x"0";
|
||||
DIVF : std_logic_vector(6 downto 0) := "0000000";
|
||||
DIVQ : std_logic_vector(2 downto 0) := "000";
|
||||
FILTER_RANGE : std_logic_vector(2 downto 0) := "000";
|
||||
ENABLE_ICEGATE : bit := '0';
|
||||
TEST_MODE : bit := '0';
|
||||
EXTERNAL_DIVIDE_FACTOR : integer := 1
|
||||
);
|
||||
port (
|
||||
REFERENCECLK : in std_logic;
|
||||
PLLOUTCORE : out std_logic;
|
||||
PLLOUTGLOBAL : out std_logic;
|
||||
EXTFEEDBACK : in std_logic;
|
||||
DYNAMICDELAY : in std_logic_vector(7 downto 0);
|
||||
LOCK : out std_logic;
|
||||
BYPASS : in std_logic;
|
||||
RESETB : in std_logic;
|
||||
LATCHINPUTVALUE : in std_logic;
|
||||
SDO : out std_logic;
|
||||
SDI : in std_logic;
|
||||
SCLK : in std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component SB_PLL40_PAD
|
||||
generic (
|
||||
FEEDBACK_PATH : string := "SIMPLE";
|
||||
DELAY_ADJUSTMENT_MODE_FEEDBACK : string := "FIXED";
|
||||
DELAY_ADJUSTMENT_MODE_RELATIVE : string := "FIXED";
|
||||
SHIFTREG_DIV_MODE : bit_vector(1 downto 0) := "00";
|
||||
FDA_FEEDBACK : bit_vector(3 downto 0) := "0000";
|
||||
FDA_RELATIVE : bit_vector(3 downto 0) := "0000";
|
||||
PLLOUT_SELECT : string := "GENCLK";
|
||||
DIVR : bit_vector(3 downto 0) := x"0";
|
||||
DIVF : bit_vector(6 downto 0) := "0000000";
|
||||
DIVQ : bit_vector(2 downto 0) := "000";
|
||||
FILTER_RANGE : bit_vector(2 downto 0) := "000";
|
||||
ENABLE_ICEGATE : bit := '0';
|
||||
TEST_MODE : bit := '0';
|
||||
EXTERNAL_DIVIDE_FACTOR : integer := 1
|
||||
);
|
||||
port (
|
||||
PACKAGEPIN : in std_logic;
|
||||
PLLOUTCORE : out std_logic;
|
||||
PLLOUTGLOBAL : out std_logic;
|
||||
EXTFEEDBACK : in std_logic;
|
||||
DYNAMICDELAY : in std_logic_vector(7 downto 0);
|
||||
LOCK : out std_logic;
|
||||
BYPASS : in std_logic;
|
||||
RESETB : in std_logic;
|
||||
LATCHINPUTVALUE : in std_logic;
|
||||
SDO : out std_logic;
|
||||
SDI : in std_logic;
|
||||
SCLK : in std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component SB_RGBA_DRV
|
||||
generic (
|
||||
CURRENT_MODE : string := "0b0";
|
||||
RGB0_CURRENT : string := "0b000000";
|
||||
RGB1_CURRENT : string := "0b000000";
|
||||
RGB2_CURRENT : string := "0b000000"
|
||||
);
|
||||
port (
|
||||
RGB0PWM : in std_logic;
|
||||
RGB1PWM : in std_logic;
|
||||
RGB2PWM : in std_logic;
|
||||
CURREN : in std_logic;
|
||||
RGBLEDEN : in std_logic;
|
||||
RGB0 : out std_logic;
|
||||
RGB1 : out std_logic;
|
||||
RGB2 : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component SB_SPRAM256KA
|
||||
port (
|
||||
ADDRESS : in std_logic_vector(13 downto 0);
|
||||
DATAIN : in std_logic_vector(15 downto 0);
|
||||
MASKWREN : in std_logic_vector(3 downto 0);
|
||||
WREN : in std_logic;
|
||||
CHIPSELECT : in std_logic;
|
||||
CLOCK : in std_logic;
|
||||
STANDBY : in std_logic;
|
||||
SLEEP : in std_logic;
|
||||
POWEROFF : in std_logic;
|
||||
DATAOUT : out std_logic_vector(15 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
end package;
|
||||
66
Libs/RiscV/NEORV32/setups/osflow/filesets.mk
Normal file
66
Libs/RiscV/NEORV32/setups/osflow/filesets.mk
Normal file
@ -0,0 +1,66 @@
|
||||
RTL_CORE_SRC := ../../rtl/core
|
||||
|
||||
NEORV32_PKG := $(RTL_CORE_SRC)/neorv32_package.vhd
|
||||
|
||||
NEORV32_APP_SRC := \
|
||||
$(RTL_CORE_SRC)/neorv32_application_image.vhd \
|
||||
|
||||
NEORV32_MEM_ENTITIES := \
|
||||
$(RTL_CORE_SRC)/neorv32_dmem.entity.vhd \
|
||||
$(RTL_CORE_SRC)/neorv32_imem.entity.vhd
|
||||
|
||||
NEORV32_CORE_SRC := \
|
||||
$(RTL_CORE_SRC)/neorv32_bootloader_image.vhd \
|
||||
$(RTL_CORE_SRC)/neorv32_boot_rom.vhd \
|
||||
$(RTL_CORE_SRC)/neorv32_bus_keeper.vhd \
|
||||
$(RTL_CORE_SRC)/neorv32_busswitch.vhd \
|
||||
$(RTL_CORE_SRC)/neorv32_cfs.vhd \
|
||||
$(RTL_CORE_SRC)/neorv32_cpu.vhd \
|
||||
$(RTL_CORE_SRC)/neorv32_cpu_alu.vhd \
|
||||
$(RTL_CORE_SRC)/neorv32_cpu_bus.vhd \
|
||||
$(RTL_CORE_SRC)/neorv32_cpu_control.vhd \
|
||||
$(RTL_CORE_SRC)/neorv32_cpu_cp_bitmanip.vhd \
|
||||
$(RTL_CORE_SRC)/neorv32_cpu_cp_fpu.vhd \
|
||||
$(RTL_CORE_SRC)/neorv32_cpu_cp_muldiv.vhd \
|
||||
$(RTL_CORE_SRC)/neorv32_cpu_cp_shifter.vhd \
|
||||
$(RTL_CORE_SRC)/neorv32_cpu_decompressor.vhd \
|
||||
$(RTL_CORE_SRC)/neorv32_cpu_regfile.vhd \
|
||||
$(RTL_CORE_SRC)/neorv32_debug_dm.vhd \
|
||||
$(RTL_CORE_SRC)/neorv32_debug_dtm.vhd \
|
||||
$(RTL_CORE_SRC)/neorv32_fifo.vhd \
|
||||
$(RTL_CORE_SRC)/neorv32_gpio.vhd \
|
||||
$(RTL_CORE_SRC)/neorv32_gptmr.vhd \
|
||||
$(RTL_CORE_SRC)/neorv32_icache.vhd \
|
||||
$(RTL_CORE_SRC)/neorv32_mtime.vhd \
|
||||
$(RTL_CORE_SRC)/neorv32_neoled.vhd \
|
||||
$(RTL_CORE_SRC)/neorv32_pwm.vhd \
|
||||
$(RTL_CORE_SRC)/neorv32_slink.vhd \
|
||||
$(RTL_CORE_SRC)/neorv32_spi.vhd \
|
||||
$(RTL_CORE_SRC)/neorv32_sysinfo.vhd \
|
||||
$(RTL_CORE_SRC)/neorv32_top.vhd \
|
||||
$(RTL_CORE_SRC)/neorv32_trng.vhd \
|
||||
$(RTL_CORE_SRC)/neorv32_twi.vhd \
|
||||
$(RTL_CORE_SRC)/neorv32_uart.vhd \
|
||||
$(RTL_CORE_SRC)/neorv32_wdt.vhd \
|
||||
$(RTL_CORE_SRC)/neorv32_wishbone.vhd \
|
||||
$(RTL_CORE_SRC)/neorv32_xirq.vhd
|
||||
|
||||
# Before including this partial makefile, NEORV32_MEM_SRC needs to be set
|
||||
# (containing two VHDL sources: one for IMEM and one for DMEM)
|
||||
|
||||
NEORV32_SRC := ${NEORV32_PKG} ${NEORV32_APP_SRC} ${NEORV32_MEM_ENTITIES} ${NEORV32_MEM_SRC} ${NEORV32_MEM_SRC_EXTRA} ${NEORV32_CORE_SRC} ${NEORV32_CORE_SRC_EXTRA}
|
||||
NEORV32_VERILOG_ALL := ${NEORV32_VERILOG_SRC} ${NEORV32_VERILOG_SRC_EXTRA}
|
||||
|
||||
ICE40_SRC := \
|
||||
devices/ice40/sb_ice40_components.vhd
|
||||
|
||||
ECP5_SRC := \
|
||||
devices/ecp5/ecp5_components.vhd
|
||||
|
||||
ifeq ($(DEVICE_SERIES),ecp5)
|
||||
DEVICE_SRC := ${ECP5_SRC}
|
||||
else
|
||||
DEVICE_SRC := ${ICE40_SRC}
|
||||
endif
|
||||
|
||||
# Optionally NEORV32_VERILOG_SRC can be set to a list of Verilog sources
|
||||
16
Libs/RiscV/NEORV32/setups/osflow/synthesis.mk
Normal file
16
Libs/RiscV/NEORV32/setups/osflow/synthesis.mk
Normal file
@ -0,0 +1,16 @@
|
||||
${DEVICE_LIB}-obj08.cf: ${DEVICE_SRC}
|
||||
ghdl -a $(GHDL_FLAGS) --work=${DEVICE_LIB} ${DEVICE_SRC}
|
||||
|
||||
neorv32-obj08.cf: ${DEVICE_LIB}-obj08.cf ${NEORV32_SRC}
|
||||
ghdl -a $(GHDL_FLAGS) --work=neorv32 ${NEORV32_SRC}
|
||||
|
||||
work-obj08.cf: neorv32-obj08.cf ${DESIGN_SRC} ${BOARD_SRC}
|
||||
ghdl -a $(GHDL_FLAGS) --work=work ${DESIGN_SRC} ${BOARD_SRC}
|
||||
|
||||
${IMPL}.json: work-obj08.cf $(NEORV32_VERILOG_ALL)
|
||||
$(YOSYS) $(YOSYSFLAGS) \
|
||||
-p \
|
||||
"$(GHDLSYNTH) $(GHDL_FLAGS) --no-formal $(TOP); \
|
||||
synth_${YOSYSSYNTH} \
|
||||
-top $(TOP) $(YOSYSPIPE) \
|
||||
-json $@" $(NEORV32_VERILOG_ALL) 2>&1 | tee yosys-report.txt
|
||||
28
Libs/RiscV/NEORV32/setups/osflow/tools.mk
Normal file
28
Libs/RiscV/NEORV32/setups/osflow/tools.mk
Normal file
@ -0,0 +1,28 @@
|
||||
GHDL_FLAGS += --std=08
|
||||
GHDL ?= ghdl
|
||||
GHDLSYNTH ?= ghdl
|
||||
YOSYS ?= yosys
|
||||
ICEPACK ?= icepack
|
||||
ECPPACK ?= ecppack
|
||||
OPENOCD ?= openocd
|
||||
COPY ?= cp -a
|
||||
|
||||
DEVICE_SERIES ?= ice40
|
||||
DEVICE_LIB ?= $(DEVICE_SERIES)
|
||||
YOSYSSYNTH ?= $(DEVICE_SERIES)
|
||||
NEXTPNR ?= nextpnr-$(DEVICE_SERIES)
|
||||
|
||||
ifeq ($(DEVICE_SERIES),ice40)
|
||||
YOSYSPIPE ?= -dsp
|
||||
CONSTRAINTS_FORMAT ?= pcf
|
||||
NEXTPNR_OUT ?= asc
|
||||
PNR2BIT_EXT ?= asc
|
||||
PACKTOOL ?= $(ICEPACK)
|
||||
PACKARGS ?=
|
||||
else
|
||||
CONSTRAINTS_FORMAT ?= lpf
|
||||
NEXTPNR_OUT ?= textcfg
|
||||
PNR2BIT_EXT ?= cfg
|
||||
PACKTOOL ?= $(ECPPACK)
|
||||
PACKARGS ?= --compress
|
||||
endif
|
||||
5
Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/.gitignore
vendored
Normal file
5
Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-avalonmm-wrapper/.gitignore
vendored
Normal file
@ -0,0 +1,5 @@
|
||||
db
|
||||
incremental_db
|
||||
output_files
|
||||
greybox_tmp
|
||||
*.qws
|
||||
@ -0,0 +1,60 @@
|
||||
# NEORV32 Test Setup using the NEORV32 with AvalonMM Master Interface wrapper
|
||||
|
||||
This setup provides a very simple "demo setup" that uses the NEORV32 with a AvalonMM
|
||||
Interface wrapper. This makes if possible to connect you own modules using a simple
|
||||
version of the AvalonMM Master interface.
|
||||
|
||||
Note that the AvalonMM Master is a very simple version providing only basic features:
|
||||
|
||||
* Single read and write access
|
||||
* Flow control (variable wait-states)
|
||||
* 8/16/32 bit data access
|
||||
* Aligned and unaligned access supported
|
||||
|
||||
The AvalonMM Master does **not** support:
|
||||
* Burst access
|
||||
* Pipeline transfer
|
||||
* Pending reads
|
||||
|
||||
The design is based on the de0-nano-test-setup, but added a AvalonMM Master wrapper.
|
||||
The wrapper file can be found here [`AvalonMM wrapper`](../../../rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd).
|
||||
|
||||
As a test an "external" DMEM is conneced to the NEORV32 over the AvalonMM Master Interface.
|
||||
|
||||
It uses the simplified and simple example top entity that provides a minimalistic interface (clock, reset, UART and 8 LEDs).
|
||||
|
||||
* FPGA Board: :books: [Terasic DE0-Nano FPGA Board](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593)
|
||||
* FPGA: Intel Cyclone-IV `EP4CE22F17C6N`
|
||||
* Toolchain: Intel Quartus Prime (tested with Quartus Prime 18.1.1 - Lite Edition)
|
||||
|
||||
|
||||
### NEORV32 Configuration
|
||||
|
||||
For NEORV32 configuration the default values of the neorv32_top in version 1.6.0 are used
|
||||
with a few exceptions:
|
||||
|
||||
* Memory: 16kB instruction memory (internal IMEM), 8kB data memory (external DMEM), No bootloader
|
||||
* Tested with version [`1.6.0`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md)
|
||||
* Clock: 50MHz from on-board oscillator
|
||||
* Reset: via on-board button "KEY0"
|
||||
* GPIO output port `gpio_o` (8-bit) connected to the 8 green user LEDs ("LED7" - "LED0")
|
||||
* UART0 signals `uart0_txd_o` and `uart0_rxd_i` are connected to the 40-pin **GPIO_0** header
|
||||
* `uart0_txd_o:` output, connected to FPGA pin `C3` - header pin `GPIO_01` (pin number "4")
|
||||
* `uart0_rxd_i:` input, connected to FPGA pin `A3` - header pin `GPIO_03` (pin number "6")
|
||||
|
||||
### FPGA Utilization
|
||||
|
||||
```
|
||||
Total logic elements 3,439 / 22,320 ( 15 % )
|
||||
Total registers 1674
|
||||
Total pins 12 / 154 ( 8 % )
|
||||
Total virtual pins 0
|
||||
Total memory bits 197,632 / 608,256 ( 32 % )
|
||||
Embedded Multiplier 9-bit elements 0 / 132 ( 0 % )
|
||||
Total PLLs 0 / 4 ( 0 % )
|
||||
```
|
||||
|
||||
|
||||
## How To Run
|
||||
|
||||
Open the Quartus project file, compile and upload to FPGA.
|
||||
@ -0,0 +1,31 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and any partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel FPGA IP License Agreement, or other applicable license
|
||||
# agreement, including, without limitation, that your use is for
|
||||
# the sole purpose of programming logic devices manufactured by
|
||||
# Intel and sold by Intel or its authorized distributors. Please
|
||||
# refer to the applicable agreement for further details, at
|
||||
# https://fpgasoftware.intel.com/eula.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
|
||||
# Date created = 20:23:30 September 13, 2021
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "18.1"
|
||||
DATE = "20:23:30 September 13, 2021"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "de0-nano-test-setup"
|
||||
@ -0,0 +1,108 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and any partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel FPGA IP License Agreement, or other applicable license
|
||||
# agreement, including, without limitation, that your use is for
|
||||
# the sole purpose of programming logic devices manufactured by
|
||||
# Intel and sold by Intel or its authorized distributors. Please
|
||||
# refer to the applicable agreement for further details, at
|
||||
# https://fpgasoftware.intel.com/eula.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
|
||||
# Date created = 20:23:30 September 13, 2021
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# de0-nano-test-setup_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus Prime software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
set_global_assignment -name FAMILY "Cyclone IV E"
|
||||
set_global_assignment -name DEVICE EP4CE22F17C6
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY neorv32_test_setup_avalonmm
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:40:53 APRIL 10, 2021"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.1 Lite Edition"
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_application_image.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_bootloader_image.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_boot_rom.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_busswitch.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_bus_keeper.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cfs.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_alu.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_bus.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_control.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_cp_bitmanip.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_cp_fpu.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_cp_muldiv.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_cp_shifter.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_decompressor.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_regfile.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_debug_dm.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_debug_dtm.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_fifo.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_gpio.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_icache.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_mtime.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_neoled.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_package.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_pwm.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_slink.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_spi.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_sysinfo.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_top.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_trng.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_twi.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_uart.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_wdt.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_wishbone.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_xirq.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_dmem.entity.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_imem.entity.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/mem/neorv32_dmem.default.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/mem/neorv32_imem.default.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE neorv32_test_setup_avalonmm.vhd
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_location_assignment PIN_R8 -to clk_i
|
||||
set_location_assignment PIN_L3 -to gpio_o[7]
|
||||
set_location_assignment PIN_B1 -to gpio_o[6]
|
||||
set_location_assignment PIN_F3 -to gpio_o[5]
|
||||
set_location_assignment PIN_D1 -to gpio_o[4]
|
||||
set_location_assignment PIN_A11 -to gpio_o[3]
|
||||
set_location_assignment PIN_B13 -to gpio_o[2]
|
||||
set_location_assignment PIN_A13 -to gpio_o[1]
|
||||
set_location_assignment PIN_A15 -to gpio_o[0]
|
||||
set_location_assignment PIN_J15 -to rstn_i
|
||||
set_location_assignment PIN_C3 -to uart0_txd_o
|
||||
set_location_assignment PIN_A3 -to uart0_rxd_i
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
@ -0,0 +1,4 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
|
||||
set_global_assignment -name IP_TOOL_VERSION "18.1"
|
||||
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "dmem_ram.vhd"]
|
||||
@ -0,0 +1,163 @@
|
||||
-- megafunction wizard: %RAM: 1-PORT%
|
||||
-- GENERATION: STANDARD
|
||||
-- VERSION: WM1.0
|
||||
-- MODULE: altsyncram
|
||||
|
||||
-- ============================================================
|
||||
-- File Name: dmem_ram.vhd
|
||||
-- Megafunction Name(s):
|
||||
-- altsyncram
|
||||
--
|
||||
-- Simulation Library Files(s):
|
||||
-- altera_mf
|
||||
-- ============================================================
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 18.1.1 Build 646 04/11/2019 SJ Lite Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||
--Your use of Intel Corporation's design tools, logic functions
|
||||
--and other software and tools, and any partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Intel Program License
|
||||
--Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
--the Intel FPGA IP License Agreement, or other applicable license
|
||||
--agreement, including, without limitation, that your use is for
|
||||
--the sole purpose of programming logic devices manufactured by
|
||||
--Intel and sold by Intel or its authorized distributors. Please
|
||||
--refer to the applicable agreement for further details, at
|
||||
--https://fpgasoftware.intel.com/eula.
|
||||
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
LIBRARY altera_mf;
|
||||
USE altera_mf.altera_mf_components.all;
|
||||
|
||||
ENTITY dmem_ram IS
|
||||
PORT
|
||||
(
|
||||
address : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
|
||||
byteena : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
|
||||
clock : IN STD_LOGIC := '1';
|
||||
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
|
||||
wren : IN STD_LOGIC ;
|
||||
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
|
||||
);
|
||||
END dmem_ram;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF dmem_ram IS
|
||||
|
||||
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
|
||||
|
||||
BEGIN
|
||||
q <= sub_wire0(31 DOWNTO 0);
|
||||
|
||||
altsyncram_component : altsyncram
|
||||
GENERIC MAP (
|
||||
byte_size => 8,
|
||||
clock_enable_input_a => "BYPASS",
|
||||
clock_enable_output_a => "BYPASS",
|
||||
intended_device_family => "Cyclone IV E",
|
||||
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
|
||||
lpm_type => "altsyncram",
|
||||
numwords_a => 2048,
|
||||
operation_mode => "SINGLE_PORT",
|
||||
outdata_aclr_a => "NONE",
|
||||
outdata_reg_a => "CLOCK0",
|
||||
power_up_uninitialized => "FALSE",
|
||||
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
|
||||
widthad_a => 11,
|
||||
width_a => 32,
|
||||
width_byteena_a => 4
|
||||
)
|
||||
PORT MAP (
|
||||
address_a => address,
|
||||
byteena_a => byteena,
|
||||
clock0 => clock,
|
||||
data_a => data,
|
||||
wren_a => wren,
|
||||
q_a => sub_wire0
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
|
||||
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
|
||||
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
||||
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
|
||||
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: MIFfilename STRING ""
|
||||
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
|
||||
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
|
||||
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
|
||||
-- Retrieval info: PRIVATE: WidthData NUMERIC "32"
|
||||
-- Retrieval info: PRIVATE: rden NUMERIC "0"
|
||||
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
-- Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
|
||||
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
|
||||
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
|
||||
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
||||
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
|
||||
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
|
||||
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
|
||||
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
|
||||
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
|
||||
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
|
||||
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
|
||||
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
|
||||
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
|
||||
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4"
|
||||
-- Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
|
||||
-- Retrieval info: USED_PORT: byteena 0 0 4 0 INPUT VCC "byteena[3..0]"
|
||||
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
|
||||
-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
|
||||
-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
|
||||
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
|
||||
-- Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
|
||||
-- Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena 0 0 4 0
|
||||
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
|
||||
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
|
||||
-- Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL dmem_ram.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL dmem_ram.inc FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL dmem_ram.cmp FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL dmem_ram.bsf FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL dmem_ram_inst.vhd FALSE
|
||||
-- Retrieval info: LIB_FILE: altera_mf
|
||||
@ -0,0 +1,332 @@
|
||||
-- #################################################################################################
|
||||
-- # << NEORV32 - Test Setup using the AvalonMM Interface >> #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # (c) "AvalonMM", "NIOS-2", "Qsys", "MegaWizard" and "Platform Designer" #
|
||||
-- # are trademarks of Intel #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # BSD 3-Clause License #
|
||||
-- # #
|
||||
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
|
||||
-- # #
|
||||
-- # Redistribution and use in source and binary forms, with or without modification, are #
|
||||
-- # permitted provided that the following conditions are met: #
|
||||
-- # #
|
||||
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
|
||||
-- # conditions and the following disclaimer. #
|
||||
-- # #
|
||||
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
|
||||
-- # conditions and the following disclaimer in the documentation and/or other materials #
|
||||
-- # provided with the distribution. #
|
||||
-- # #
|
||||
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
|
||||
-- # endorse or promote products derived from this software without specific prior written #
|
||||
-- # permission. #
|
||||
-- # #
|
||||
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
|
||||
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
|
||||
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
|
||||
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
|
||||
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
|
||||
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
|
||||
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
|
||||
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
|
||||
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 #
|
||||
-- #################################################################################################
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee.std_logic_unsigned.ALL;
|
||||
|
||||
library neorv32;
|
||||
use neorv32.neorv32_package.all;
|
||||
|
||||
entity neorv32_test_setup_avalonmm is
|
||||
generic (
|
||||
-- adapt these for your setup --
|
||||
CLOCK_FREQUENCY : natural := 50000000; -- clock frequency of clk_i in Hz
|
||||
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
|
||||
MEM_INT_DMEM_SIZE : natural := 8*1024 -- size of processor-internal data memory in bytes
|
||||
);
|
||||
port (
|
||||
-- Global control --
|
||||
clk_i : in std_ulogic; -- global clock, rising edge
|
||||
rstn_i : in std_ulogic; -- global reset, low-active, async
|
||||
-- GPIO --
|
||||
gpio_o : out std_ulogic_vector(7 downto 0); -- parallel output
|
||||
-- UART0 --
|
||||
uart0_txd_o : out std_ulogic; -- UART0 send data
|
||||
uart0_rxd_i : in std_ulogic -- UART0 receive data
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture neorv32_test_setup_avalonmm_rtl of neorv32_test_setup_avalonmm is
|
||||
|
||||
component neorv32_top_avalonmm is
|
||||
generic (
|
||||
-- General --
|
||||
CLOCK_FREQUENCY : natural; -- clock frequency of clk_i in Hz
|
||||
HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit)
|
||||
INT_BOOTLOADER_EN : boolean := false; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
|
||||
|
||||
-- On-Chip Debugger (OCD) --
|
||||
ON_CHIP_DEBUGGER_EN : boolean := false; -- implement on-chip debugger
|
||||
|
||||
-- RISC-V CPU Extensions --
|
||||
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
|
||||
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit-manipulation extension?
|
||||
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
||||
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
||||
CPU_EXTENSION_RISCV_M : boolean := false; -- implement mul/div extension?
|
||||
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
||||
CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT regs!)
|
||||
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
||||
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
|
||||
CPU_EXTENSION_RISCV_Zmmul : boolean := false; -- implement multiply-only M sub-extension?
|
||||
|
||||
-- Extension Options --
|
||||
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
|
||||
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
|
||||
CPU_CNT_WIDTH : natural := 64; -- total width of CPU cycle and instret counters (0..64)
|
||||
CPU_IPB_ENTRIES : natural := 2; -- entries is instruction prefetch buffer, has to be a power of 2
|
||||
|
||||
-- Physical Memory Protection (PMP) --
|
||||
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
|
||||
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
|
||||
|
||||
-- Hardware Performance Monitors (HPM) --
|
||||
HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29)
|
||||
HPM_CNT_WIDTH : natural := 40; -- total size of HPM counters (0..64)
|
||||
|
||||
-- Internal Instruction memory (IMEM) --
|
||||
MEM_INT_IMEM_EN : boolean := false; -- implement processor-internal instruction memory
|
||||
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
|
||||
|
||||
-- Internal Data memory (DMEM) --
|
||||
MEM_INT_DMEM_EN : boolean := false; -- implement processor-internal data memory
|
||||
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes
|
||||
|
||||
-- Internal Cache memory (iCACHE) --
|
||||
ICACHE_EN : boolean := false; -- implement instruction cache
|
||||
ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2
|
||||
ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2
|
||||
ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
|
||||
|
||||
-- Stream link interface (SLINK) --
|
||||
SLINK_NUM_TX : natural := 0; -- number of TX links (0..8)
|
||||
SLINK_NUM_RX : natural := 0; -- number of TX links (0..8)
|
||||
SLINK_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two
|
||||
SLINK_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two
|
||||
|
||||
-- External Interrupts Controller (XIRQ) --
|
||||
XIRQ_NUM_CH : natural := 0; -- number of external IRQ channels (0..32)
|
||||
XIRQ_TRIGGER_TYPE : std_ulogic_vector(31 downto 0) := x"ffffffff"; -- trigger type: 0=level, 1=edge
|
||||
XIRQ_TRIGGER_POLARITY : std_ulogic_vector(31 downto 0) := x"ffffffff"; -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
|
||||
|
||||
-- Processor peripherals --
|
||||
IO_GPIO_EN : boolean := false; -- implement general purpose input/output port unit (GPIO)?
|
||||
IO_MTIME_EN : boolean := false; -- implement machine system timer (MTIME)?
|
||||
IO_UART0_EN : boolean := false; -- implement primary universal asynchronous receiver/transmitter (UART0)?
|
||||
IO_UART1_EN : boolean := false; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
|
||||
IO_SPI_EN : boolean := false; -- implement serial peripheral interface (SPI)?
|
||||
IO_TWI_EN : boolean := false; -- implement two-wire interface (TWI)?
|
||||
IO_PWM_NUM_CH : natural := 0; -- number of PWM channels to implement (0..60); 0 = disabled
|
||||
IO_WDT_EN : boolean := false; -- implement watch dog timer (WDT)?
|
||||
IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)?
|
||||
IO_CFS_EN : boolean := false; -- implement custom functions subsystem (CFS)?
|
||||
IO_CFS_CONFIG : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic
|
||||
IO_CFS_IN_SIZE : positive := 32; -- size of CFS input conduit in bits
|
||||
IO_CFS_OUT_SIZE : positive := 32; -- size of CFS output conduit in bits
|
||||
IO_NEOLED_EN : boolean := false; -- implement NeoPixel-compatible smart LED interface (NEOLED)?
|
||||
IO_NEOLED_TX_FIFO : natural := 1 -- NEOLED TX FIFO depth, 1..32k, has to be a power of two
|
||||
);
|
||||
port (
|
||||
-- Global control --
|
||||
clk_i : in std_ulogic; -- global clock, rising edge
|
||||
rstn_i : in std_ulogic; -- global reset, low-active, async
|
||||
|
||||
-- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) --
|
||||
jtag_trst_i : in std_ulogic := 'U'; -- low-active TAP reset (optional)
|
||||
jtag_tck_i : in std_ulogic := 'U'; -- serial clock
|
||||
jtag_tdi_i : in std_ulogic := 'U'; -- serial data input
|
||||
jtag_tdo_o : out std_ulogic; -- serial data output
|
||||
jtag_tms_i : in std_ulogic := 'U'; -- mode select
|
||||
|
||||
-- AvalonMM interface
|
||||
read_o : out std_logic;
|
||||
write_o : out std_logic;
|
||||
waitrequest_i : in std_logic := '0';
|
||||
byteenable_o : out std_logic_vector(3 downto 0);
|
||||
address_o : out std_logic_vector(31 downto 0);
|
||||
writedata_o : out std_logic_vector(31 downto 0);
|
||||
readdata_i : in std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
-- Advanced memory control signals (available if MEM_EXT_EN = true) --
|
||||
fence_o : out std_ulogic; -- indicates an executed FENCE operation
|
||||
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation
|
||||
|
||||
-- TX stream interfaces (available if SLINK_NUM_TX > 0) --
|
||||
slink_tx_dat_o : out sdata_8x32_t; -- output data
|
||||
slink_tx_val_o : out std_ulogic_vector(7 downto 0); -- valid output
|
||||
slink_tx_rdy_i : in std_ulogic_vector(7 downto 0) := (others => 'L'); -- ready to send
|
||||
|
||||
-- RX stream interfaces (available if SLINK_NUM_RX > 0) --
|
||||
slink_rx_dat_i : in sdata_8x32_t := (others => (others => 'U')); -- input data
|
||||
slink_rx_val_i : in std_ulogic_vector(7 downto 0) := (others => 'L'); -- valid input
|
||||
slink_rx_rdy_o : out std_ulogic_vector(7 downto 0); -- ready to receive
|
||||
|
||||
-- GPIO (available if IO_GPIO_EN = true) --
|
||||
gpio_o : out std_ulogic_vector(63 downto 0); -- parallel output
|
||||
gpio_i : in std_ulogic_vector(63 downto 0) := (others => 'U'); -- parallel input
|
||||
|
||||
-- primary UART0 (available if IO_UART0_EN = true) --
|
||||
uart0_txd_o : out std_ulogic; -- UART0 send data
|
||||
uart0_rxd_i : in std_ulogic := 'U'; -- UART0 receive data
|
||||
uart0_rts_o : out std_ulogic; -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
|
||||
uart0_cts_i : in std_ulogic := 'L'; -- hw flow control: UART0.TX allowed to transmit, low-active, optional
|
||||
|
||||
-- secondary UART1 (available if IO_UART1_EN = true) --
|
||||
uart1_txd_o : out std_ulogic; -- UART1 send data
|
||||
uart1_rxd_i : in std_ulogic := 'U'; -- UART1 receive data
|
||||
uart1_rts_o : out std_ulogic; -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional
|
||||
uart1_cts_i : in std_ulogic := 'L'; -- hw flow control: UART1.TX allowed to transmit, low-active, optional
|
||||
|
||||
-- SPI (available if IO_SPI_EN = true) --
|
||||
spi_sck_o : out std_ulogic; -- SPI serial clock
|
||||
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
|
||||
spi_sdi_i : in std_ulogic := 'U'; -- controller data in, peripheral data out
|
||||
spi_csn_o : out std_ulogic_vector(07 downto 0); -- chip-select
|
||||
|
||||
-- TWI (available if IO_TWI_EN = true) --
|
||||
twi_sda_io : inout std_logic := 'U'; -- twi serial data line
|
||||
twi_scl_io : inout std_logic := 'U'; -- twi serial clock line
|
||||
|
||||
-- PWM (available if IO_PWM_NUM_CH > 0) --
|
||||
pwm_o : out std_ulogic_vector(IO_PWM_NUM_CH-1 downto 0); -- pwm channels
|
||||
|
||||
-- Custom Functions Subsystem IO (available if IO_CFS_EN = true) --
|
||||
cfs_in_i : in std_ulogic_vector(IO_CFS_IN_SIZE-1 downto 0) := (others => 'U'); -- custom CFS inputs conduit
|
||||
cfs_out_o : out std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom CFS outputs conduit
|
||||
|
||||
-- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
|
||||
neoled_o : out std_ulogic; -- async serial data line
|
||||
|
||||
-- System time --
|
||||
mtime_i : in std_ulogic_vector(63 downto 0) := (others => 'U'); -- current system time from ext. MTIME (if IO_MTIME_EN = false)
|
||||
mtime_o : out std_ulogic_vector(63 downto 0); -- current system time from int. MTIME (if IO_MTIME_EN = true)
|
||||
|
||||
-- External platform interrupts (available if XIRQ_NUM_CH > 0) --
|
||||
xirq_i : in std_ulogic_vector(XIRQ_NUM_CH-1 downto 0) := (others => 'L'); -- IRQ channels
|
||||
|
||||
-- CPU interrupts --
|
||||
mtime_irq_i : in std_ulogic := 'L'; -- machine timer interrupt, available if IO_MTIME_EN = false
|
||||
msw_irq_i : in std_ulogic := 'L'; -- machine software interrupt
|
||||
mext_irq_i : in std_ulogic := 'L' -- machine external interrupt
|
||||
);
|
||||
end component neorv32_top_avalonmm;
|
||||
|
||||
-- Intel/Altera RAM module created by MegaWizard
|
||||
COMPONENT dmem_ram IS
|
||||
PORT
|
||||
(
|
||||
address : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
|
||||
byteena : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
|
||||
clock : IN STD_LOGIC := '1';
|
||||
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
|
||||
wren : IN STD_LOGIC ;
|
||||
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT dmem_ram;
|
||||
|
||||
signal con_gpio_o : std_ulogic_vector(63 downto 0);
|
||||
|
||||
signal read_o : std_logic;
|
||||
signal write_o : std_logic;
|
||||
signal waitrequest_i : std_logic;
|
||||
signal byteenable_o : std_logic_vector(3 downto 0);
|
||||
signal address_o : std_logic_vector(31 downto 0);
|
||||
signal writedata_o : std_logic_vector(31 downto 0);
|
||||
signal readdata_i : std_logic_vector(31 downto 0);
|
||||
|
||||
signal read_wait_cnt : std_logic_vector(1 downto 0);
|
||||
|
||||
|
||||
begin
|
||||
|
||||
-- The Core Of The Problem ----------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
neorv32_top_inst: neorv32_top_avalonmm
|
||||
generic map (
|
||||
-- General --
|
||||
CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz
|
||||
INT_BOOTLOADER_EN => false, -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
|
||||
-- RISC-V CPU Extensions --
|
||||
CPU_EXTENSION_RISCV_C => true, -- implement compressed extension?
|
||||
CPU_EXTENSION_RISCV_M => true, -- implement mul/div extension?
|
||||
CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system?
|
||||
-- Internal Instruction memory --
|
||||
MEM_INT_IMEM_EN => true, -- implement processor-internal instruction memory
|
||||
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes
|
||||
-- Internal Data memory --
|
||||
MEM_INT_DMEM_EN => false, -- implement processor-internal data memory
|
||||
MEM_INT_DMEM_SIZE => 0, -- size of processor-internal data memory in bytes
|
||||
-- Processor peripherals --
|
||||
IO_GPIO_EN => true, -- implement general purpose input/output port unit (GPIO)?
|
||||
IO_MTIME_EN => true, -- implement machine system timer (MTIME)?
|
||||
IO_UART0_EN => true -- implement primary universal asynchronous receiver/transmitter (UART0)?
|
||||
)
|
||||
port map (
|
||||
-- Global control --
|
||||
clk_i => clk_i, -- global clock, rising edge
|
||||
rstn_i => rstn_i, -- global reset, low-active, async
|
||||
-- GPIO (available if IO_GPIO_EN = true) --
|
||||
gpio_o => con_gpio_o, -- parallel output
|
||||
-- primary UART0 (available if IO_UART0_EN = true) --
|
||||
uart0_txd_o => uart0_txd_o, -- UART0 send data
|
||||
uart0_rxd_i => uart0_rxd_i, -- UART0 receive data
|
||||
-- AvalonMM Interface
|
||||
read_o => read_o,
|
||||
write_o => write_o,
|
||||
waitrequest_i => waitrequest_i,
|
||||
byteenable_o => byteenable_o,
|
||||
address_o => address_o,
|
||||
writedata_o => writedata_o,
|
||||
readdata_i => readdata_i
|
||||
);
|
||||
|
||||
-- Simple example hooking up RAM module to AvalonMM Interface
|
||||
-- and using this RAM as DMEM
|
||||
my_dmem_ram : dmem_ram
|
||||
port map(
|
||||
address => address_o(12 downto 2),
|
||||
byteena => byteenable_o,
|
||||
clock => clk_i,
|
||||
data => writedata_o,
|
||||
wren => write_o,
|
||||
q => readdata_i);
|
||||
|
||||
|
||||
-- Very simple AvalonMM control signals
|
||||
-- Write has 0 wait-states
|
||||
-- Read has 2 wait-states
|
||||
waitrequest_i <= '1' when (read_o = '1' and read_wait_cnt /= "10") else '0';
|
||||
process(clk_i, rstn_i)
|
||||
begin
|
||||
if rstn_i = '0' then
|
||||
read_wait_cnt <= "00";
|
||||
elsif rising_edge(clk_i) then
|
||||
if read_o = '0' then
|
||||
read_wait_cnt <= "00";
|
||||
else
|
||||
read_wait_cnt <= read_wait_cnt + '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- GPIO output --
|
||||
gpio_o <= con_gpio_o(7 downto 0);
|
||||
|
||||
|
||||
end architecture;
|
||||
8
Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-qsys/.gitignore
vendored
Normal file
8
Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup-qsys/.gitignore
vendored
Normal file
@ -0,0 +1,8 @@
|
||||
/.qsys_edit
|
||||
/db
|
||||
/neorv32_test_qsys
|
||||
/*.sopcinfo
|
||||
/*.rpt
|
||||
/output_files
|
||||
/incremental_db
|
||||
/*.qws
|
||||
@ -0,0 +1,51 @@
|
||||
# NEORV32 Test Setup using the NEORV32 as a Nios II drop-in replacement
|
||||
|
||||
This setup provides a very simple "demo setup" that uses the NEORV32 Qsys/Platform Designer component
|
||||
so that the NEORV32 can be used as a drop-in replacement of the Nios II soft CPU from Intel.
|
||||
The demo is running on the Terasic DE0-Nano FPGA Board.
|
||||
|
||||
The design is based on the de0-nano-test-setup, but the NEORV32 cpu is added as a QSys/Platform Designer
|
||||
component. As an example the DMEM is "external" and uses an Platform Designer SRAM block.
|
||||
|
||||
|
||||
|
||||
For details about the design and use of the NEORV32 as a Qsys/Platform Designer component please
|
||||
look at the Qsys component files and documentation here [`NEORV32 Qsys Component`](../neorv32_qsys_component)
|
||||
|
||||
It uses the simplified simple example top entity that provides a minimalistic interface (clock, reset, UART and 8 LEDs).
|
||||
|
||||
* FPGA Board: :books: [Terasic DE0-Nano FPGA Board](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593)
|
||||
* FPGA: Intel Cyclone-IV `EP4CE22F17C6N`
|
||||
* Toolchain: Intel Quartus Prime (tested with Quartus Prime 18.1.1 - Lite Edition)
|
||||
|
||||
|
||||
### NEORV32 Configuration
|
||||
|
||||
For NEORV32 configuration the default values of the neorv32_top in version 1.6.0 are used
|
||||
with a few exceptions:
|
||||
|
||||
* Memory: 16kB instruction memory (internal IMEM), 8kB data memory (external DMEM), No bootloader
|
||||
* Tested with version [`1.6.0`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md)
|
||||
* Clock: 50MHz from on-board oscillator
|
||||
* Reset: via on-board button "KEY0"
|
||||
* GPIO output port `gpio_o` (8-bit) connected to the 8 green user LEDs ("LED7" - "LED0")
|
||||
* UART0 signals `uart0_txd_o` and `uart0_rxd_i` are connected to the 40-pin **GPIO_0** header
|
||||
* `uart0_txd_o:` output, connected to FPGA pin `C3` - header pin `GPIO_01` (pin number "4")
|
||||
* `uart0_rxd_i:` input, connected to FPGA pin `A3` - header pin `GPIO_03` (pin number "6")
|
||||
|
||||
### FPGA Utilization
|
||||
|
||||
```
|
||||
Total logic elements 4,064 / 22,320 ( 18 % )
|
||||
Total registers 1932
|
||||
Total pins 12 / 154 ( 8 % )
|
||||
Total virtual pins 0
|
||||
Total memory bits 230,400 / 608,256 ( 38 % )
|
||||
Embedded Multiplier 9-bit elements 0 / 132 ( 0 % )
|
||||
Total PLLs 0 / 4 ( 0 % )
|
||||
```
|
||||
|
||||
|
||||
## How To Run
|
||||
|
||||
Open the Quartus project file, compile and upload to FPGA.
|
||||
@ -0,0 +1,3 @@
|
||||
<library>
|
||||
<path path="../neorv32_qsys_component/**/*" />
|
||||
</library>
|
||||
@ -0,0 +1,31 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and any partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel FPGA IP License Agreement, or other applicable license
|
||||
# agreement, including, without limitation, that your use is for
|
||||
# the sole purpose of programming logic devices manufactured by
|
||||
# Intel and sold by Intel or its authorized distributors. Please
|
||||
# refer to the applicable agreement for further details, at
|
||||
# https://fpgasoftware.intel.com/eula.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
|
||||
# Date created = 21:29:54 June 08, 2021
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "18.1"
|
||||
DATE = "21:29:54 June 08, 2021"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "de0-nano-test-setup"
|
||||
@ -0,0 +1,76 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and any partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel FPGA IP License Agreement, or other applicable license
|
||||
# agreement, including, without limitation, that your use is for
|
||||
# the sole purpose of programming logic devices manufactured by
|
||||
# Intel and sold by Intel or its authorized distributors. Please
|
||||
# refer to the applicable agreement for further details, at
|
||||
# https://fpgasoftware.intel.com/eula.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
|
||||
# Date created = 21:29:54 June 08, 2021
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# de0-nano-test-setup_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus Prime software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
set_global_assignment -name FAMILY "Cyclone IV E"
|
||||
set_global_assignment -name DEVICE EP4CE22F17C6
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY neorv32_ProcessorTop_Test
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:40:53 APRIL 10, 2021"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.1 Lite Edition"
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id neorv32_ProcessorTop_Test
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id neorv32_ProcessorTop_Test
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id neorv32_ProcessorTop_Test
|
||||
set_location_assignment PIN_R8 -to clk_i
|
||||
set_location_assignment PIN_J15 -to rstn_i
|
||||
set_location_assignment PIN_C3 -to uart0_txd_o
|
||||
set_location_assignment PIN_A3 -to uart0_rxd_i
|
||||
set_location_assignment PIN_L3 -to gpio_o[7]
|
||||
set_location_assignment PIN_B1 -to gpio_o[6]
|
||||
set_location_assignment PIN_F3 -to gpio_o[5]
|
||||
set_location_assignment PIN_D1 -to gpio_o[4]
|
||||
set_location_assignment PIN_A11 -to gpio_o[3]
|
||||
set_location_assignment PIN_B13 -to gpio_o[2]
|
||||
set_location_assignment PIN_A13 -to gpio_o[1]
|
||||
set_location_assignment PIN_A15 -to gpio_o[0]
|
||||
set_global_assignment -name QSYS_FILE neorv32_test_qsys.qsys
|
||||
set_global_assignment -name QIP_FILE ../neorv32_qsys_component/neorv32_qsys.qip
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/core/neorv32_application_image.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/core/neorv32_bootloader_image.vhd
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_dmem.entity.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_imem.entity.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/mem/neorv32_dmem.default.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/mem/neorv32_imem.default.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE neorv32_ProcessorTop_Test.vhd
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id neorv32_ProcessorTop_Test
|
||||
@ -0,0 +1,12 @@
|
||||
#**************************************************************
|
||||
# Time Information
|
||||
#**************************************************************
|
||||
|
||||
set_time_format -unit ns -decimal_places 3
|
||||
|
||||
#**************************************************************
|
||||
# Create Clock
|
||||
#**************************************************************
|
||||
|
||||
create_clock -name {altera_reserved_tck} -period 100.000 -waveform { 0.000 50.000 } [get_ports {altera_reserved_tck}]
|
||||
create_clock -name {clk_i} -period 20.0 -waveform { 0.0 10.0 } [get_ports {clk_i}]
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 52 KiB |
@ -0,0 +1,44 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
library work;
|
||||
|
||||
entity neorv32_ProcessorTop_Test is port (
|
||||
clk_i : in std_logic;
|
||||
rstn_i : in std_logic;
|
||||
gpio_o : out std_logic_vector(7 downto 0);
|
||||
uart0_txd_o : out std_logic;
|
||||
uart0_rxd_i : in std_logic);
|
||||
end neorv32_ProcessorTop_Test;
|
||||
|
||||
----------------------------------------------------------------------------------------------------
|
||||
architecture rtl of neorv32_ProcessorTop_Test is
|
||||
----------------------------------------------------------------------------------------------------
|
||||
|
||||
component neorv32_test_qsys is
|
||||
port (
|
||||
clk_clk : in std_logic;
|
||||
perf_uart0_uart0_txd_o : out std_logic;
|
||||
perf_uart0_uart0_rxd_i : in std_logic;
|
||||
perf_gpio_gpio_o : out std_logic_vector(31 downto 0);
|
||||
perf_gpio_gpio_i : in std_logic_vector(31 downto 0);
|
||||
reset_reset_n : in std_logic);
|
||||
end component;
|
||||
|
||||
signal perf_gpio_gpio_o : std_logic_vector(31 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
gpio_o <= perf_gpio_gpio_o(7 downto 0);
|
||||
|
||||
my_riscv_core : neorv32_test_qsys
|
||||
port map (
|
||||
clk_clk => clk_i,
|
||||
perf_gpio_gpio_o => perf_gpio_gpio_o,
|
||||
perf_gpio_gpio_i => (others => '0'),
|
||||
perf_uart0_uart0_txd_o => uart0_txd_o,
|
||||
perf_uart0_uart0_rxd_i => uart0_rxd_i,
|
||||
reset_reset_n => rstn_i);
|
||||
|
||||
end rtl;
|
||||
File diff suppressed because one or more lines are too long
7
Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup/.gitignore
vendored
Normal file
7
Libs/RiscV/NEORV32/setups/quartus/de0-nano-test-setup/.gitignore
vendored
Normal file
@ -0,0 +1,7 @@
|
||||
db
|
||||
incremental_db
|
||||
output_files
|
||||
*.qpf
|
||||
*.qsf
|
||||
*.qws
|
||||
*.vhd
|
||||
@ -0,0 +1,62 @@
|
||||
# NEORV32 Test Setup for the Terasic DE0-Nano FPGA Board
|
||||
|
||||
This setup provides a very simple script-based "demo setup" that allows to check out the NEORV32 processor on the Terasic DE0-Nano board.
|
||||
It uses the simplified [`neorv32_test_setup_bootloader.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) top entity, which is a wrapper for the actual processor
|
||||
top entity that provides a minimalistic interface (clock, reset, UART and 8 LEDs).
|
||||
|
||||
* FPGA Board: :books: [Terasic DE0-Nano FPGA Board](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593)
|
||||
* FPGA: Intel Cyclone-IV `EP4CE22F17C6N`
|
||||
* Toolchain: Intel Quartus Prime (tested with Quartus Prime 20.1.0 - Lite Edition)
|
||||
|
||||
|
||||
### NEORV32 Configuration
|
||||
|
||||
:information_source: See the top entity [`rtl/test_setups/neorv32_test_setup_bootloader.vhd` ](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) for
|
||||
configuration and entity details and `create_project.tcl` for the according FPGA pin mapping.
|
||||
|
||||
* CPU: `rv32imcu_Zicsr` + 4 `HPM` (hardware performance monitors, 40-bit wide)
|
||||
* Memory: 16kB instruction memory (internal IMEM), 8kB data memory (internal DMEM), bootloader ROM
|
||||
* Peripherals: `GPIO`, `MTIME`, `UART0`, `WDT`
|
||||
* Tested with version [`1.5.7.6`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md)
|
||||
* Clock: 50MHz from on-board oscillator
|
||||
* Reset: via on-board button "KEY0"
|
||||
* GPIO output port `gpio_o` (8-bit) connected to the 8 green user LEDs ("LED7" - "LED0")
|
||||
* UART0 signals `uart0_txd_o` and `uart0_rxd_i` are connected to the 40-pin **GPIO_0** header
|
||||
* `uart0_txd_o:` output, connected to FPGA pin `C3` - header pin `GPIO_01` (pin number "4")
|
||||
* `uart0_rxd_i:` input, connected to FPGA pin `A3` - header pin `GPIO_03` (pin number "6")
|
||||
|
||||
:warning: The default [`neorv32_test_setup_bootloader.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) top entity
|
||||
is configured for a 100MHz input clock. Since the on-board oscillator of the DE0-nano board generates a 50MHz clock, the test setup has to be modified.
|
||||
This is automatically done by the `create_project.tcl` TCL script, which makes a local copy of the original test setup VHDL file
|
||||
(in *this* folder) and uses `sed` to configure the `CLOCK_FREQUENCY` generic (in the local copy) for 50MHz. The local copy is then used as actual
|
||||
top entity.
|
||||
|
||||
### FPGA Utilization
|
||||
|
||||
```
|
||||
Total logic elements 4,009 / 22,320 ( 18 % )
|
||||
Total registers 1860
|
||||
Total pins 12 / 154 ( 8 % )
|
||||
Total virtual pins 0
|
||||
Total memory bits 230,400 / 608,256 ( 38 % )
|
||||
Embedded Multiplier 9-bit elements 0 / 132 ( 0 % )
|
||||
Total PLLs 0 / 4 ( 0 % )
|
||||
```
|
||||
|
||||
|
||||
## How To Run
|
||||
|
||||
The `create_project.tcl` TCL script in this directory can be used to create a complete Quartus project.
|
||||
If not already available, this script will create a `work` folder in this directory.
|
||||
|
||||
1. start Quartus (in GUI mode)
|
||||
2. in the menu line click "View/Utility Windows/Tcl console" to open the Tcl console
|
||||
3. use the console to naviagte to **this** folder: `cd .../neorv32/boards/de0-nano-test-setup`
|
||||
4. execute `source create_project.tcl` - this will create and open the actual Quartus project in this folder
|
||||
5. if a "select family" prompt appears select the "Cyclone IV E" family and click OK
|
||||
6. double click on "Compile Design" in the "Tasks" window. This will synthesize, map and place & route your design and will also generate the actual FPGA bitstream
|
||||
7. when the process is done open the programmer (for example via "Tools/Programmer") and click "Start" in the programmer window to upload the bitstream to your FPGA
|
||||
8. use a serial terminal (like :earth_asia: [Tera Term](https://ttssh2.osdn.jp/index.html.en)) to connect to the USB-UART interface using the following configuration:
|
||||
19200 Baud, 8 data bits, 1 stop bit, no parity bits, no transmission / flow control protocol (raw bytes only), newline on `\r\n` (carriage return & newline)
|
||||
9. now you can communicate with the bootloader console and upload a new program. Check out the [example programs](https://github.com/stnolting/neorv32/tree/master/sw/example)
|
||||
and see section "Let's Get It Started" of the :page_facing_up: [NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) for further resources.
|
||||
@ -0,0 +1,94 @@
|
||||
# make a local copy of original "./../../rtl/test_setups/neorv32_test_setup_bootloader.vhd " file
|
||||
# and modify the default clock frequency: set to 50MHz
|
||||
set shell_script "cp -f ./../../../rtl/test_setups/neorv32_test_setup_bootloader.vhd . && sed -i 's/100000000/50000000/g' neorv32_test_setup_bootloader.vhd "
|
||||
exec sh -c $shell_script
|
||||
|
||||
# Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and any partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel FPGA IP License Agreement, or other applicable license
|
||||
# agreement, including, without limitation, that your use is for
|
||||
# the sole purpose of programming logic devices manufactured by
|
||||
# Intel and sold by Intel or its authorized distributors. Please
|
||||
# refer to the applicable agreement for further details, at
|
||||
# https://fpgasoftware.intel.com/eula.
|
||||
|
||||
# Quartus Prime: Generate Tcl File for Project
|
||||
# File: de0_nano_test.tcl
|
||||
# Generated on: Sat Apr 10 16:57:48 2021
|
||||
|
||||
# Load Quartus Prime Tcl Project package
|
||||
package require ::quartus::project
|
||||
|
||||
set need_to_close_project 0
|
||||
set make_assignments 1
|
||||
|
||||
# Check that the right project is open
|
||||
if {[is_project_open]} {
|
||||
if {[string compare $quartus(project) "de0-nano-test-setup"]} {
|
||||
puts "Project de0-nano-test-setup is not open"
|
||||
set make_assignments 0
|
||||
}
|
||||
} else {
|
||||
# Only open if not already open
|
||||
if {[project_exists de0-nano-test-setup]} {
|
||||
project_open -revision de0-nano-test-setup de0-nano-test-setup
|
||||
} else {
|
||||
project_new -revision de0-nano-test-setup de0-nano-test-setup
|
||||
}
|
||||
set need_to_close_project 1
|
||||
}
|
||||
|
||||
# Make assignments
|
||||
if {$make_assignments} {
|
||||
set_global_assignment -name FAMILY "Cyclone IV E"
|
||||
set_global_assignment -name DEVICE EP4CE22F17C6
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY neorv32_test_setup_bootloader
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:40:53 APRIL 10, 2021"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.0 Lite Edition"
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
|
||||
|
||||
# core VHDL files
|
||||
set core_src_dir [glob ./../../../rtl/core/*.vhd]
|
||||
foreach core_src_file $core_src_dir {
|
||||
set_global_assignment -name VHDL_FILE $core_src_file -library neorv32
|
||||
}
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/mem/neorv32_dmem.default.vhd -library neorv32
|
||||
set_global_assignment -name VHDL_FILE ./../../../rtl/core/mem/neorv32_imem.default.vhd -library neorv32
|
||||
|
||||
# top entity: use local modified copy of the original test setup
|
||||
set_global_assignment -name VHDL_FILE "neorv32_test_setup_bootloader.vhd"
|
||||
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
|
||||
set_location_assignment PIN_R8 -to clk_i
|
||||
set_location_assignment PIN_L3 -to gpio_o[7]
|
||||
set_location_assignment PIN_B1 -to gpio_o[6]
|
||||
set_location_assignment PIN_F3 -to gpio_o[5]
|
||||
set_location_assignment PIN_D1 -to gpio_o[4]
|
||||
set_location_assignment PIN_A11 -to gpio_o[3]
|
||||
set_location_assignment PIN_B13 -to gpio_o[2]
|
||||
set_location_assignment PIN_A13 -to gpio_o[1]
|
||||
set_location_assignment PIN_A15 -to gpio_o[0]
|
||||
set_location_assignment PIN_J15 -to rstn_i
|
||||
set_location_assignment PIN_C3 -to uart0_txd_o
|
||||
set_location_assignment PIN_A3 -to uart0_rxd_i
|
||||
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
|
||||
# Commit assignments
|
||||
export_assignments
|
||||
}
|
||||
@ -0,0 +1,73 @@
|
||||
# NEORV32 Platform Designer Component
|
||||
|
||||
This folder contains a Qsys/Platform Designer wrapper for the NEORV32 together with
|
||||
an Wishbone to AvalonMM bridge. This makes the NEORV32 a drop-in replacement for the
|
||||
Altera/Intel Nios II soft CPU.
|
||||
|
||||
This is just a quick template showing a possible solution, and not a feature complete
|
||||
solution. All parameters in the Generic section could be added to the GUI.
|
||||
|
||||
Only some peripherals (UART0, UART1 and GPIO) are connected, but other peripheral
|
||||
could easily be connected.
|
||||
|
||||
## Solution overview
|
||||
|
||||
The solution is made up of 3 files. One VHDL file for the component implementation
|
||||
(neorv32_qsys.vhd), one file for the Qsys component (neorv32_qsys_hw.tcl) and one file
|
||||
listing files to include (neorv32_qsys.qip) to simplify the Quartus setup (.qsf) file.
|
||||
The figure below shows how the component is implemented.
|
||||
|
||||
|
||||
|
||||
## GUI Settings
|
||||
|
||||
The Qsys component is created so that some parameters can be set in the Platform Design
|
||||
GUI. More settings could be added as needed.
|
||||
|
||||
|
||||
|
||||
## Implementation notes
|
||||
|
||||
The Platform Designer has a bug (feature?) that makes boolean parameters from the Platform
|
||||
Designer GUI being port mapped to the VHDL component generic as 0/1 instead of true/false.
|
||||
This is a known bug/feature.
|
||||
|
||||
A workaround for this is made by making the generic (boolean) parameters in the VHDL
|
||||
as "integer", and then use a "integer2bool" function to make the parameter boolean
|
||||
again to fit the NEORV32 top.
|
||||
|
||||
## How to use
|
||||
|
||||
To use the Qsys component in your Platform Designer design, you will just need to
|
||||
make a "User_Components.ipx" file in your Qsys folder, and reference this (rtl/system_integration/neorv32_qsys_component) folder.
|
||||
|
||||
Example "User_Components.ipx" content:
|
||||
```
|
||||
<library>
|
||||
<path path="../neorv32_qsys_component/**/*" />
|
||||
</library>
|
||||
```
|
||||
|
||||
You will also need to add 3 lines in your Quartus project file (QSF-file) in order to
|
||||
get the correct source files.
|
||||
|
||||
Example QSF-file info:
|
||||
```
|
||||
......
|
||||
set_global_assignment -name QIP_FILE ../neorv32_qsys_component/neorv32_qsys.qip
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/core/neorv32_application_image.vhd
|
||||
set_global_assignment -name VHDL_FILE ../../../rtl/core/neorv32_bootloader_image.vhd
|
||||
......
|
||||
```
|
||||
|
||||
Having seperate links for the bootloader and application images makes it easy to include images
|
||||
from your own project folders.
|
||||
|
||||
# NEORV32 Platform Designer Component - Example Design
|
||||
|
||||
The branch contains an example design using the Qsys/Platform designer component
|
||||
and running on the DE0 Nano board.
|
||||
|
||||
The example design can be found here [setups/quartus/de0-nano-test-setup-qsys`](../de0-nano-test-setup-qsys)
|
||||
|
||||
The example design will run the software examples.
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 11 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 62 KiB |
@ -0,0 +1,33 @@
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_package.vhd"] -library neorv32
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_boot_rom.vhd"] -library neorv32
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_busswitch.vhd"] -library neorv32
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_bus_keeper.vhd"] -library neorv32
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_cfs.vhd"] -library neorv32
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_cpu.vhd"] -library neorv32
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_cpu_alu.vhd"] -library neorv32
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_cpu_bus.vhd"] -library neorv32
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_cpu_control.vhd"] -library neorv32
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_cpu_cp_fpu.vhd"] -library neorv32
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_cpu_cp_muldiv.vhd"] -library neorv32
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_cpu_decompressor.vhd"] -library neorv32
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_cpu_regfile.vhd"] -library neorv32
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_debug_dm.vhd"] -library neorv32
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_debug_dtm.vhd"] -library neorv32
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_gpio.vhd"] -library neorv32
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_icache.vhd"] -library neorv32
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_mtime.vhd"] -library neorv32
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_nco.vhd"] -library neorv32
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_neoled.vhd"] -library neorv32
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_package.vhd"] -library neorv32
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_pwm.vhd"] -library neorv32
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_spi.vhd"] -library neorv32
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_sysinfo.vhd"] -library neorv32
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_top.vhd"] -library neorv32
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_trng.vhd"] -library neorv32
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_twi.vhd"] -library neorv32
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_uart.vhd"] -library neorv32
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_wdt.vhd"] -library neorv32
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_wishbone.vhd"] -library neorv32
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_fifo.vhd"] -library neorv32
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_cpu_cp_shifter.vhd"] -library neorv32
|
||||
|
||||
@ -0,0 +1,279 @@
|
||||
-- #################################################################################################
|
||||
-- # << NEORV32 - Processor Top Qsys component with AvalonMM Compatible Master Interface >> #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # (c) "NIOS-2", "Qsys", "Platform Designer" and "AvalonMM" are trademarks of Intel. #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # BSD 3-Clause License #
|
||||
-- # #
|
||||
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
|
||||
-- # #
|
||||
-- # Redistribution and use in source and binary forms, with or without modification, are #
|
||||
-- # permitted provided that the following conditions are met: #
|
||||
-- # #
|
||||
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
|
||||
-- # conditions and the following disclaimer. #
|
||||
-- # #
|
||||
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
|
||||
-- # conditions and the following disclaimer in the documentation and/or other materials #
|
||||
-- # provided with the distribution. #
|
||||
-- # #
|
||||
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
|
||||
-- # endorse or promote products derived from this software without specific prior written #
|
||||
-- # permission. #
|
||||
-- # #
|
||||
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
|
||||
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
|
||||
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
|
||||
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
|
||||
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
|
||||
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
|
||||
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
|
||||
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
|
||||
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
|
||||
-- #################################################################################################
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library neorv32;
|
||||
use neorv32.neorv32_package.all;
|
||||
|
||||
entity neorv32_qsys is
|
||||
generic (
|
||||
GUI_CLOCK_FREQUENCY : integer := 100000000;
|
||||
GUI_EMABLE_INTERNAL_IMEM : integer := 1;
|
||||
GUI_IMEM_SIZE : integer := 16;
|
||||
GUI_EMABLE_INTERNAL_DMEM : integer := 1;
|
||||
GUI_DMEM_SIZE : integer := 8;
|
||||
GUI_ENABLE_BOOTLOADER : integer := 0;
|
||||
GUI_ENABLE_AVALONMM : integer := 1;
|
||||
GUI_ENABLE_UART0 : integer := 1;
|
||||
GUI_ENABLE_UART1 : integer := 0;
|
||||
GUI_ENABLE_GPIO : integer := 0
|
||||
);
|
||||
port (
|
||||
-- Global control --
|
||||
clk_i : in std_logic := '0'; -- global clock, rising edge
|
||||
rstn_i : in std_logic := '0'; -- global reset, low-active, async
|
||||
-- GPIO --
|
||||
gpio_o : out std_logic_vector(63 downto 0); -- parallel output
|
||||
gpio_i : in std_logic_vector(63 downto 0) := (others => '0'); -- parallel output
|
||||
-- UART0 --
|
||||
uart0_txd_o : out std_logic; -- UART0 send data
|
||||
uart0_rxd_i : in std_logic := '0'; -- UART0 receive data
|
||||
|
||||
-- UART1 --
|
||||
uart1_txd_o : out std_logic; -- UART0 send data
|
||||
uart1_rxd_i : in std_logic := '0'; -- UART0 receive data
|
||||
|
||||
-- AvalonMM interface
|
||||
read : out std_logic;
|
||||
write : out std_logic;
|
||||
waitrequest : in std_logic := '0';
|
||||
byteenable : out std_logic_vector(3 downto 0);
|
||||
address : out std_logic_vector(31 downto 0);
|
||||
writedata : out std_logic_vector(31 downto 0);
|
||||
readdata : in std_logic_vector(31 downto 0) := (others => '0')
|
||||
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture neorv32_qsys_rtl of neorv32_qsys is
|
||||
|
||||
signal gpio_i_ulogic : std_ulogic_vector(63 downto 0);
|
||||
signal gpio_o_ulogic : std_ulogic_vector(63 downto 0);
|
||||
|
||||
-- Wishbone bus interface (available if MEM_EXT_EN = true) --
|
||||
signal wb_tag_o : std_ulogic_vector(02 downto 0); -- request tag
|
||||
signal wb_adr_o : std_ulogic_vector(31 downto 0); -- address
|
||||
signal wb_dat_i : std_ulogic_vector(31 downto 0); -- read data
|
||||
signal wb_dat_o : std_ulogic_vector(31 downto 0); -- write data
|
||||
signal wb_we_o : std_ulogic; -- read/write
|
||||
signal wb_sel_o : std_ulogic_vector(03 downto 0); -- byte enable
|
||||
signal wb_stb_o : std_ulogic; -- strobe
|
||||
signal wb_cyc_o : std_ulogic; -- valid cycle
|
||||
signal wb_lock_o : std_ulogic; -- exclusive access request
|
||||
signal wb_ack_i : std_ulogic; -- transfer acknowledge
|
||||
signal wb_err_i : std_ulogic; -- transfer error
|
||||
|
||||
signal reset : std_logic;
|
||||
|
||||
function integer2bool(integer_value : integer := 0) return boolean is
|
||||
begin
|
||||
if integer_value = 0 then
|
||||
return false;
|
||||
else
|
||||
return true;
|
||||
end if;
|
||||
end function;
|
||||
|
||||
begin
|
||||
|
||||
-- The Core Of The Problem ----------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
neorv32_top_inst: neorv32_top
|
||||
generic map (
|
||||
-- General --
|
||||
CLOCK_FREQUENCY => GUI_CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz
|
||||
INT_BOOTLOADER_EN => integer2bool(GUI_ENABLE_BOOTLOADER), -- implement processor-internal bootloader?
|
||||
HW_THREAD_ID => 0, -- hardware thread id (hartid)
|
||||
-- On-Chip Debugger (OCD) --
|
||||
ON_CHIP_DEBUGGER_EN => false, -- implement on-chip debugger
|
||||
-- RISC-V CPU Extensions --
|
||||
CPU_EXTENSION_RISCV_A => false, -- implement atomic extension?
|
||||
CPU_EXTENSION_RISCV_C => true, -- implement compressed extension?
|
||||
CPU_EXTENSION_RISCV_E => false, -- implement embedded RF extension?
|
||||
CPU_EXTENSION_RISCV_M => true, -- implement muld/div extension?
|
||||
CPU_EXTENSION_RISCV_U => true, -- implement user mode extension?
|
||||
CPU_EXTENSION_RISCV_Zfinx => false, -- implement 32-bit floating-point extension (using INT reg!)
|
||||
CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system?
|
||||
CPU_EXTENSION_RISCV_Zifencei => false, -- implement instruction stream sync.?
|
||||
CPU_EXTENSION_RISCV_Zmmul => false, -- implement multiply-only M sub-extension?
|
||||
-- Extension Options --
|
||||
FAST_MUL_EN => false, -- use DSPs for M extension's multiplier
|
||||
FAST_SHIFT_EN => false, -- use barrel shifter for shift operations
|
||||
CPU_CNT_WIDTH => 64, -- total width of CPU cycle and instret counters (0..64)
|
||||
CPU_IPB_ENTRIES => 2, -- entries is instruction prefetch buffer, has to be a power of 2
|
||||
-- Physical Memory Protection (PMP) --
|
||||
PMP_NUM_REGIONS => 0, -- number of regions (0..64)
|
||||
PMP_MIN_GRANULARITY => 64*1024, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
|
||||
-- Hardware Performance Monitors (HPM) --
|
||||
HPM_NUM_CNTS => 4, -- number of implemented HPM counters (0..29)
|
||||
HPM_CNT_WIDTH => 40, -- total size of HPM counters (0..64)
|
||||
-- Internal Instruction memory --
|
||||
MEM_INT_IMEM_EN => integer2bool(GUI_EMABLE_INTERNAL_IMEM), -- implement processor-internal instruction memory
|
||||
MEM_INT_IMEM_SIZE => GUI_IMEM_SIZE*1024, -- size of processor-internal instruction memory in bytes
|
||||
-- Internal Data memory --
|
||||
MEM_INT_DMEM_EN => integer2bool(GUI_EMABLE_INTERNAL_DMEM), -- implement processor-internal data memory
|
||||
MEM_INT_DMEM_SIZE => GUI_DMEM_SIZE*1024, -- size of processor-internal data memory in bytes
|
||||
-- Internal Cache memory --
|
||||
ICACHE_EN => false, -- implement instruction cache
|
||||
ICACHE_NUM_BLOCKS => 4, -- i-cache: number of blocks (min 1), has to be a power of 2
|
||||
ICACHE_BLOCK_SIZE => 64, -- i-cache: block size in bytes (min 4), has to be a power of 2
|
||||
ICACHE_ASSOCIATIVITY => 1, -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
|
||||
-- External memory interface --
|
||||
MEM_EXT_EN => integer2bool(GUI_ENABLE_AVALONMM), -- implement external memory bus interface?
|
||||
MEM_EXT_TIMEOUT => 0, -- cycles after a pending bus access auto-terminates (0 = disabled)
|
||||
MEM_EXT_PIPE_MODE => false, -- protocol: false=classic/standard wishbone mode, true=pipelined wishbone mode
|
||||
MEM_EXT_BIG_ENDIAN => false, -- byte order: true=big-endian, false=little-endian
|
||||
MEM_EXT_ASYNC_RX => false, -- use register buffer for RX data when false
|
||||
-- Stream link interface (SLINK) --
|
||||
SLINK_NUM_TX => 0, -- number of TX links (0..8)
|
||||
SLINK_NUM_RX => 0, -- number of TX links (0..8)
|
||||
SLINK_TX_FIFO => 1, -- TX fifo depth, has to be a power of two
|
||||
SLINK_RX_FIFO => 1, -- RX fifo depth, has to be a power of two
|
||||
-- External Interrupts Controller (XIRQ) --
|
||||
XIRQ_NUM_CH => 0, -- number of external IRQ channels (0..32)
|
||||
XIRQ_TRIGGER_TYPE => (x"FFFFFFFF"), -- trigger type: 0=level, 1=edge
|
||||
XIRQ_TRIGGER_POLARITY => (x"FFFFFFFF"), -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
|
||||
-- Processor peripherals --
|
||||
IO_GPIO_EN => integer2bool(GUI_ENABLE_GPIO), -- implement general purpose input/output port unit (GPIO)?
|
||||
IO_MTIME_EN => true, -- implement machine system timer (MTIME)?
|
||||
IO_UART0_EN => integer2bool(GUI_ENABLE_UART0), -- implement primary universal asynchronous receiver/transmitter (UART0)?
|
||||
IO_UART1_EN => integer2bool(GUI_ENABLE_UART1), -- implement secondary universal asynchronous receiver/transmitter (UART1)?
|
||||
IO_SPI_EN => false, -- implement serial peripheral interface (SPI)?
|
||||
IO_TWI_EN => false, -- implement two-wire interface (TWI)?
|
||||
IO_PWM_NUM_CH => 0, -- number of PWM channels to implement (0..60); 0 = disabled
|
||||
IO_WDT_EN => true, -- implement watch dog timer (WDT)?
|
||||
IO_TRNG_EN => false, -- implement true random number generator (TRNG)?
|
||||
IO_CFS_EN => false, -- implement custom functions subsystem (CFS)?
|
||||
IO_CFS_CONFIG => x"00000000", -- custom CFS configuration generic
|
||||
IO_CFS_IN_SIZE => 32, -- size of CFS input conduit in bits
|
||||
IO_CFS_OUT_SIZE => 32, -- size of CFS output conduit in bits
|
||||
IO_NEOLED_EN => false, -- implement NeoPixel-compatible smart LED interface (NEOLED)?
|
||||
IO_NEOLED_TX_FIFO => 1 -- NEOLED TX FIFO depth, 1..32k, has to be a power of two
|
||||
)
|
||||
port map (
|
||||
-- Global control --
|
||||
clk_i => clk_i, -- global clock, rising edge
|
||||
rstn_i => rstn_i, -- global reset, low-active, async
|
||||
-- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) --
|
||||
jtag_trst_i => '0', -- low-active TAP reset (optional)
|
||||
jtag_tck_i => '0', -- serial clock
|
||||
jtag_tdi_i => '0', -- serial data input
|
||||
jtag_tdo_o => open, -- serial data output
|
||||
jtag_tms_i => '0', -- mode select
|
||||
-- Wishbone bus interface (available if MEM_EXT_EN = true) --
|
||||
wb_tag_o => wb_tag_o, -- tag
|
||||
wb_adr_o => wb_adr_o, -- address
|
||||
wb_dat_i => wb_dat_i, -- read data
|
||||
wb_dat_o => wb_dat_o, -- write data
|
||||
wb_we_o => wb_we_o, -- read/write
|
||||
wb_sel_o => wb_sel_o, -- byte enable
|
||||
wb_stb_o => wb_stb_o, -- strobe
|
||||
wb_cyc_o => wb_cyc_o, -- valid cycle
|
||||
wb_lock_o => wb_lock_o, -- exclusive access request
|
||||
wb_ack_i => wb_ack_i, -- transfer acknowledge
|
||||
wb_err_i => wb_err_i, -- transfer error
|
||||
-- Advanced memory control signals (available if MEM_EXT_EN = true) --
|
||||
fence_o => open, -- indicates an executed FENCE operation
|
||||
fencei_o => open, -- indicates an executed FENCEI operation
|
||||
-- TX stream interfaces (available if SLINK_NUM_TX > 0) --
|
||||
slink_tx_dat_o => open, -- output data
|
||||
slink_tx_val_o => open, -- valid output
|
||||
slink_tx_rdy_i => (others => 'L'), -- ready to send
|
||||
-- RX stream interfaces (available if SLINK_NUM_RX > 0) --
|
||||
slink_rx_dat_i => (others => (others => 'U')), -- input data
|
||||
slink_rx_val_i => (others => 'L'), -- valid input
|
||||
slink_rx_rdy_o => open, -- ready to receive
|
||||
|
||||
-- GPIO (available if IO_GPIO_EN = true) --
|
||||
gpio_o => gpio_o_ulogic, -- parallel output
|
||||
gpio_i => gpio_i_ulogic, -- parallel input
|
||||
-- primary UART0 (available if IO_UART0_EN = true) --
|
||||
uart0_txd_o => uart0_txd_o, -- UART0 send data
|
||||
uart0_rxd_i => uart0_rxd_i, -- UART0 receive data
|
||||
uart0_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
|
||||
uart0_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional
|
||||
-- secondary UART1 (available if IO_UART1_EN = true) --
|
||||
uart1_txd_o => uart1_txd_o, -- UART1 send data
|
||||
uart1_rxd_i => uart1_rxd_i, -- UART1 receive data
|
||||
uart1_rts_o => open, -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional
|
||||
uart1_cts_i => '0', -- hw flow control: UART1.TX allowed to transmit, low-active, optional
|
||||
-- SPI (available if IO_SPI_EN = true) --
|
||||
spi_sck_o => open, -- SPI serial clock
|
||||
spi_sdo_o => open, -- controller data out, peripheral data in
|
||||
spi_sdi_i => '0', -- controller data in, peripheral data out
|
||||
spi_csn_o => open, -- SPI CS
|
||||
-- TWI (available if IO_TWI_EN = true) --
|
||||
twi_sda_io => open, -- twi serial data line
|
||||
twi_scl_io => open, -- twi serial clock line
|
||||
-- PWM (available if IO_PWM_NUM_CH > 0) --
|
||||
pwm_o => open, -- pwm channels
|
||||
-- Custom Functions Subsystem IO --
|
||||
cfs_in_i => (others => '0'), -- custom inputs
|
||||
cfs_out_o => open, -- custom outputs
|
||||
-- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
|
||||
neoled_o => open, -- async serial data line
|
||||
-- System time --
|
||||
mtime_i => (others => '0'), -- current system time from ext. MTIME (if IO_MTIME_EN = false)
|
||||
mtime_o => open, -- current system time from int. MTIME (if IO_MTIME_EN = true)
|
||||
-- External platform interrupts (available if XIRQ_NUM_CH > 0) --
|
||||
xirq_i => (others => '0'), -- IRQ channels
|
||||
-- Interrupts --
|
||||
mtime_irq_i => '0', -- machine timer interrupt, available if IO_MTIME_EN = false
|
||||
msw_irq_i => '0', -- machine software interrupt
|
||||
mext_irq_i => '0' -- machine external interrupt
|
||||
);
|
||||
|
||||
-- Convert between std_logic / std_ulogic
|
||||
gpio_o <= std_logic_vector(gpio_o_ulogic);
|
||||
gpio_i_ulogic <= std_ulogic_vector(gpio_i);
|
||||
|
||||
reset <= not(rstn_i);
|
||||
|
||||
-- Wishbone to AvalonMM brdige
|
||||
read <= '1' when (wb_stb_o = '1' and wb_we_o = '0') else '0';
|
||||
write <= '1' when (wb_stb_o = '1' and wb_we_o = '1') else '0';
|
||||
address <= std_logic_vector(wb_adr_o);
|
||||
writedata <= std_logic_vector(wb_dat_o);
|
||||
byteenable <= std_logic_vector(wb_sel_o);
|
||||
|
||||
wb_dat_i <= std_ulogic_vector(readdata);
|
||||
wb_ack_i <= not(waitrequest);
|
||||
wb_err_i <= '0';
|
||||
|
||||
end architecture;
|
||||
@ -0,0 +1,258 @@
|
||||
|
||||
#
|
||||
# request TCL package from ACDS 16.1
|
||||
#
|
||||
package require -exact qsys 16.1
|
||||
|
||||
#
|
||||
# module neorv32_qsys
|
||||
#
|
||||
set_module_property DESCRIPTION "NEORV32 RISC-V CPU"
|
||||
set_module_property NAME neorv32_qsys
|
||||
set_module_property VERSION 1.0
|
||||
set_module_property INTERNAL false
|
||||
set_module_property OPAQUE_ADDRESS_MAP true
|
||||
set_module_property GROUP "NEORV32"
|
||||
set_module_property AUTHOR "Stephan Nolting"
|
||||
set_module_property DISPLAY_NAME "NEORV32 CPU"
|
||||
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
|
||||
set_module_property EDITABLE false
|
||||
set_module_property REPORT_TO_TALKBACK false
|
||||
set_module_property ALLOW_GREYBOX_GENERATION false
|
||||
set_module_property REPORT_HIERARCHY false
|
||||
set_module_property ELABORATION_CALLBACK elaborate
|
||||
|
||||
#
|
||||
# file sets
|
||||
#
|
||||
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
|
||||
set_fileset_property QUARTUS_SYNTH TOP_LEVEL neorv32_qsys
|
||||
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
|
||||
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
|
||||
add_fileset_file neorv32_qsys.vhd VHDL PATH neorv32_qsys.vhd TOP_LEVEL_FILE
|
||||
|
||||
#
|
||||
# parameters
|
||||
#
|
||||
#add_parameter src_id INTEGER 1 ""
|
||||
#set_parameter_property src_id DEFAULT_VALUE 1
|
||||
#set_parameter_property src_id DISPLAY_NAME src_id
|
||||
#set_parameter_property src_id WIDTH ""
|
||||
#set_parameter_property src_id TYPE INTEGER
|
||||
#set_parameter_property src_id UNITS None
|
||||
#set_parameter_property src_id ALLOWED_RANGES 1:15
|
||||
#set_parameter_property src_id DESCRIPTION "Input source ID"
|
||||
#set_parameter_property src_id HDL_PARAMETER true
|
||||
|
||||
add_parameter GUI_CLOCK_FREQUENCY INTEGER 100000000
|
||||
set_parameter_property GUI_CLOCK_FREQUENCY DISPLAY_NAME "CPU Clock Frequency"
|
||||
set_parameter_property GUI_CLOCK_FREQUENCY DISPLAY_UNITS "Hz"
|
||||
set_parameter_property GUI_CLOCK_FREQUENCY DESCRIPTION "CPU clock frequency"
|
||||
set_parameter_property GUI_CLOCK_FREQUENCY ALLOWED_RANGES 1000000:250000000
|
||||
set_parameter_property GUI_CLOCK_FREQUENCY GROUP "Core"
|
||||
set_parameter_property GUI_CLOCK_FREQUENCY HDL_PARAMETER true
|
||||
|
||||
add_parameter GUI_EMABLE_INTERNAL_IMEM BOOLEAN true
|
||||
set_parameter_property GUI_EMABLE_INTERNAL_IMEM DISPLAY_NAME "Enable Internal IMEM"
|
||||
set_parameter_property GUI_EMABLE_INTERNAL_IMEM DESCRIPTION "Use interal IMEM"
|
||||
set_parameter_property GUI_EMABLE_INTERNAL_IMEM GROUP "Core"
|
||||
set_parameter_property GUI_EMABLE_INTERNAL_IMEM HDL_PARAMETER true
|
||||
|
||||
add_parameter GUI_IMEM_SIZE INTEGER 16
|
||||
set_parameter_property GUI_IMEM_SIZE DISPLAY_NAME "Internal IMEM Memory Size"
|
||||
set_parameter_property GUI_IMEM_SIZE DISPLAY_UNITS "KBytes"
|
||||
set_parameter_property GUI_IMEM_SIZE DESCRIPTION "Size of IMEM instruction memory"
|
||||
set_parameter_property GUI_IMEM_SIZE ALLOWED_RANGES {4 8 16 32 64}
|
||||
set_parameter_property GUI_IMEM_SIZE GROUP "Core"
|
||||
set_parameter_property GUI_IMEM_SIZE HDL_PARAMETER true
|
||||
|
||||
add_parameter GUI_EMABLE_INTERNAL_DMEM BOOLEAN true
|
||||
set_parameter_property GUI_EMABLE_INTERNAL_DMEM DISPLAY_NAME "Enable Internal DMEM"
|
||||
set_parameter_property GUI_EMABLE_INTERNAL_DMEM DESCRIPTION "Use interal DMEM"
|
||||
set_parameter_property GUI_EMABLE_INTERNAL_DMEM GROUP "Core"
|
||||
set_parameter_property GUI_EMABLE_INTERNAL_DMEM HDL_PARAMETER true
|
||||
|
||||
add_parameter GUI_DMEM_SIZE INTEGER 8
|
||||
set_parameter_property GUI_DMEM_SIZE DISPLAY_NAME "Internal DMEM Memory Size"
|
||||
set_parameter_property GUI_DMEM_SIZE DISPLAY_UNITS "KBytes"
|
||||
set_parameter_property GUI_DMEM_SIZE DESCRIPTION "Size of DMEM data memory"
|
||||
set_parameter_property GUI_DMEM_SIZE ALLOWED_RANGES {2 4 8 16 32 64}
|
||||
set_parameter_property GUI_DMEM_SIZE GROUP "Core"
|
||||
set_parameter_property GUI_DMEM_SIZE HDL_PARAMETER true
|
||||
|
||||
|
||||
add_parameter GUI_ENABLE_BOOTLOADER BOOLEAN false
|
||||
set_parameter_property GUI_ENABLE_BOOTLOADER DISPLAY_NAME "Enable Bootloader"
|
||||
set_parameter_property GUI_ENABLE_BOOTLOADER DESCRIPTION "Add bootloader and start bootloader"
|
||||
set_parameter_property GUI_ENABLE_BOOTLOADER GROUP "Bootloader"
|
||||
set_parameter_property GUI_ENABLE_BOOTLOADER HDL_PARAMETER true
|
||||
|
||||
|
||||
add_parameter GUI_ENABLE_AVALONMM BOOLEAN true
|
||||
set_parameter_property GUI_ENABLE_AVALONMM DISPLAY_NAME "Enable AvalonMM Interface"
|
||||
set_parameter_property GUI_ENABLE_AVALONMM DESCRIPTION "Add AvalonMM Interface for external modules"
|
||||
set_parameter_property GUI_ENABLE_AVALONMM GROUP "Peripheral"
|
||||
set_parameter_property GUI_ENABLE_AVALONMM HDL_PARAMETER true
|
||||
|
||||
add_parameter GUI_ENABLE_UART0 BOOLEAN true
|
||||
set_parameter_property GUI_ENABLE_UART0 DISPLAY_NAME "Enable UART0"
|
||||
set_parameter_property GUI_ENABLE_UART0 DESCRIPTION "Add UART0 to core"
|
||||
set_parameter_property GUI_ENABLE_UART0 GROUP "Peripheral"
|
||||
set_parameter_property GUI_ENABLE_UART0 HDL_PARAMETER true
|
||||
|
||||
add_parameter GUI_ENABLE_UART1 BOOLEAN false
|
||||
set_parameter_property GUI_ENABLE_UART1 DISPLAY_NAME "Enable UART1"
|
||||
set_parameter_property GUI_ENABLE_UART1 DESCRIPTION "Add UART1 to core"
|
||||
set_parameter_property GUI_ENABLE_UART1 GROUP "Peripheral"
|
||||
set_parameter_property GUI_ENABLE_UART1 HDL_PARAMETER true
|
||||
|
||||
add_parameter GUI_ENABLE_GPIO BOOLEAN false
|
||||
set_parameter_property GUI_ENABLE_GPIO DISPLAY_NAME "Enable GPIO"
|
||||
set_parameter_property GUI_ENABLE_GPIO DESCRIPTION "Add GPIO to core"
|
||||
set_parameter_property GUI_ENABLE_GPIO GROUP "Peripheral"
|
||||
set_parameter_property GUI_ENABLE_GPIO HDL_PARAMETER true
|
||||
|
||||
|
||||
|
||||
#
|
||||
# display items
|
||||
#
|
||||
|
||||
|
||||
#
|
||||
# connection point clk
|
||||
#
|
||||
add_interface clk clock end
|
||||
set_interface_property clk clockRate 0
|
||||
set_interface_property clk ENABLED true
|
||||
set_interface_property clk EXPORT_OF ""
|
||||
set_interface_property clk PORT_NAME_MAP ""
|
||||
set_interface_property clk CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property clk SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port clk clk_i clk Input 1
|
||||
|
||||
|
||||
#
|
||||
# connection point reset
|
||||
#
|
||||
add_interface reset reset end
|
||||
set_interface_property reset associatedClock clk
|
||||
set_interface_property reset synchronousEdges DEASSERT
|
||||
set_interface_property reset ENABLED true
|
||||
set_interface_property reset EXPORT_OF ""
|
||||
set_interface_property reset PORT_NAME_MAP ""
|
||||
set_interface_property reset CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property reset SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port reset rstn_i reset_n Input 1
|
||||
|
||||
#
|
||||
# connection point perf_gpio
|
||||
#
|
||||
add_interface perf_gpio conduit end
|
||||
set_interface_property perf_gpio associatedClock none
|
||||
set_interface_property perf_gpio associatedReset none
|
||||
set_interface_property perf_gpio ENABLED true
|
||||
set_interface_property perf_gpio EXPORT_OF ""
|
||||
set_interface_property perf_gpio PORT_NAME_MAP ""
|
||||
set_interface_property perf_gpio CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property perf_gpio SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port perf_gpio gpio_o gpio_o Output 64
|
||||
add_interface_port perf_gpio gpio_i gpio_i Input 64
|
||||
|
||||
#
|
||||
# connection point perf_uart0
|
||||
#
|
||||
add_interface perf_uart0 conduit end
|
||||
set_interface_property perf_uart0 associatedClock none
|
||||
set_interface_property perf_uart0 associatedReset none
|
||||
set_interface_property perf_uart0 ENABLED true
|
||||
set_interface_property perf_uart0 EXPORT_OF ""
|
||||
set_interface_property perf_uart0 PORT_NAME_MAP ""
|
||||
set_interface_property perf_uart0 CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property perf_uart0 SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port perf_uart0 uart0_txd_o uart0_txd_o Output 1
|
||||
add_interface_port perf_uart0 uart0_rxd_i uart0_rxd_i Input 1
|
||||
|
||||
#
|
||||
# connection point perf_uart1
|
||||
#
|
||||
add_interface perf_uart1 conduit end
|
||||
set_interface_property perf_uart1 associatedClock none
|
||||
set_interface_property perf_uart1 associatedReset none
|
||||
set_interface_property perf_uart1 ENABLED true
|
||||
set_interface_property perf_uart1 EXPORT_OF ""
|
||||
set_interface_property perf_uart1 PORT_NAME_MAP ""
|
||||
set_interface_property perf_uart1 CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property perf_uart1 SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port perf_uart1 uart1_txd_o uart1_txd_o Output 1
|
||||
add_interface_port perf_uart1 uart1_rxd_i uart1_rxd_i Input 1
|
||||
|
||||
#
|
||||
# connection point master
|
||||
#
|
||||
add_interface master avalon start
|
||||
set_interface_property master addressUnits SYMBOLS
|
||||
set_interface_property master associatedClock clk
|
||||
set_interface_property master associatedReset reset
|
||||
set_interface_property master bitsPerSymbol 8
|
||||
set_interface_property master burstOnBurstBoundariesOnly false
|
||||
set_interface_property master burstcountUnits WORDS
|
||||
set_interface_property master doStreamReads false
|
||||
set_interface_property master doStreamWrites false
|
||||
set_interface_property master holdTime 0
|
||||
set_interface_property master linewrapBursts false
|
||||
set_interface_property master maximumPendingReadTransactions 0
|
||||
set_interface_property master maximumPendingWriteTransactions 0
|
||||
set_interface_property master readLatency 0
|
||||
set_interface_property master readWaitTime 0
|
||||
set_interface_property master setupTime 0
|
||||
set_interface_property master timingUnits Cycles
|
||||
set_interface_property master writeWaitTime 0
|
||||
set_interface_property master ENABLED true
|
||||
set_interface_property master EXPORT_OF ""
|
||||
set_interface_property master PORT_NAME_MAP ""
|
||||
set_interface_property master CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property master SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port master address address Output 32
|
||||
add_interface_port master read read Output 1
|
||||
add_interface_port master write write Output 1
|
||||
add_interface_port master byteenable byteenable Output 4
|
||||
add_interface_port master writedata writedata Output 32
|
||||
add_interface_port master readdata readdata Input 32
|
||||
add_interface_port master waitrequest waitrequest Input 1
|
||||
|
||||
# Callback to enable/disable interface signals
|
||||
proc elaborate {} {
|
||||
|
||||
if { [get_parameter_value GUI_ENABLE_GPIO] == "false" } {
|
||||
set_interface_property perf_gpio ENABLED false
|
||||
} else {
|
||||
set_interface_property perf_gpio ENABLED true
|
||||
}
|
||||
|
||||
if { [get_parameter_value GUI_ENABLE_UART0] == "false" } {
|
||||
set_interface_property perf_uart0 ENABLED false
|
||||
} else {
|
||||
set_interface_property perf_uart0 ENABLED true
|
||||
}
|
||||
|
||||
if { [get_parameter_value GUI_ENABLE_UART1] == "false" } {
|
||||
set_interface_property perf_uart1 ENABLED false
|
||||
} else {
|
||||
set_interface_property perf_uart1 ENABLED true
|
||||
}
|
||||
|
||||
if { [get_parameter_value GUI_ENABLE_AVALONMM] == "false" } {
|
||||
set_interface_property master ENABLED false
|
||||
} else {
|
||||
set_interface_property master ENABLED true
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
@ -0,0 +1,65 @@
|
||||
# NEORV32 Test Setup for the Terasic Cyclone-V GX Starter Kit FPGA Board
|
||||
|
||||
This setup provides a very simple script-based "demo setup" that allows to check out the NEORV32 processor on the Terasic Cyclone-V GX Starter Kit board.
|
||||
It uses the simplified [`neorv32_test_setup_bootloader.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) top entity, which is a wrapper for the actual processor
|
||||
top entity that provides a minimalistic interface (clock, reset, UART and 8 LEDs).
|
||||
|
||||
* FPGA Board: :books: [Terasic Cyclone-V GX Starter Kit FPGA Board](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=830)
|
||||
* FPGA: Intel Cyclone-V GX `5CGXFC5C6F27C7N`
|
||||
* Toolchain: Intel Quartus Prime (tested with Quartus Prime 20.1.0 - Lite Edition)
|
||||
|
||||
|
||||
### NEORV32 Configuration
|
||||
|
||||
:information_source: See the top entity [`rtl/test_setups/neorv32_test_setup_bootloader.vhd` ](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) for
|
||||
configuration and entity details and `create_project.tcl` for the according FPGA pin mapping.
|
||||
|
||||
* CPU: `rv32imcu_Zicsr` + 4 `HPM` (hardware performance monitors, 40-bit wide)
|
||||
* Memory: 16kB instruction memory (internal IMEM), 8kB data memory (internal DMEM), bootloader ROM
|
||||
* Peripherals: `GPIO`, `MTIME`, `UART0`, `WDT`
|
||||
* Tested with version [`1.5.9.4`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md)
|
||||
* Clock: 50MHz from on-board oscillator
|
||||
* Reset: via on-board button "KEY0"
|
||||
* GPIO output port `gpio_o` (8-bit) connected to the 8 green user LEDs ("LED7" - "LED0")
|
||||
* UART0 signals `uart0_txd_o` and `uart0_rxd_i` are connected to the on-board provided USB to UART converter
|
||||
|
||||
:warning: The default [`neorv32_test_setup_bootloader.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) top entity
|
||||
is configured for a 100MHz input clock. Since the on-board clock generator of the Cyclone-V GX Starter Kit board needs I2C to be programmed, the fixed 50MHz clock on bank 5B, pin R20 is used for this test setup, and the test setup has to be modified accordingly.
|
||||
This is automatically done by the `create_project.tcl` TCL script, which makes a local copy of the original test setup VHDL file
|
||||
(in *this* folder) and uses `sed` to configure the `CLOCK_FREQUENCY` generic (in the local copy) for 50MHz. The local copy is then used as actual
|
||||
top entity.
|
||||
|
||||
### FPGA Utilization
|
||||
|
||||
```
|
||||
Logic utilization (in ALMs) 1,442 / 29,080 ( 5 % )
|
||||
Total registers 1771
|
||||
Total pins 12 / 364 ( 3 % )
|
||||
Total virtual pins 0
|
||||
Total block memory bits 231,424 / 4,567,040 ( 5 % )
|
||||
Total DSP Blocks 0 / 150 ( 0 % )
|
||||
Total HSSI RX PCSs 0 / 6 ( 0 % )
|
||||
Total HSSI PMA RX Deserializers 0 / 6 ( 0 % )
|
||||
Total HSSI TX PCSs 0 / 6 ( 0 % )
|
||||
Total HSSI PMA TX Serializers 0 / 6 ( 0 % )
|
||||
Total PLLs 0 / 12 ( 0 % )
|
||||
Total DLLs 0 / 4 ( 0 % )
|
||||
```
|
||||
|
||||
|
||||
## How To Run
|
||||
|
||||
The `create_project.tcl` TCL script in this directory can be used to create a complete Quartus project.
|
||||
If not already available, this script will create a `work` folder in this directory.
|
||||
|
||||
1. start Quartus (in GUI mode)
|
||||
2. in the menu line click "View/Utility Windows/Tcl console" to open the Tcl console
|
||||
3. use the console to navigate to **this** folder: `cd .../setups/quartus/terasic-cyclone-V-gx-starter-kit-test-setup`
|
||||
4. execute `source create_project.tcl` - this will create and open the actual Quartus project in this folder. Do NOT run the Quartus-supplied tcl setup script, as that will change all assignment names.
|
||||
5. if a "select family" prompt appears, go to the "Board" tab, select the "Cyclone V GX Starter Kit" board and click OK
|
||||
6. double click on "Compile Design" in the "Tasks" window. This will synthesize, map and place & route your design and will also generate the actual FPGA bitstream
|
||||
7. when the process is done open the programmer (for example via "Tools/Programmer") and click "Start" in the programmer window to upload the bitstream to your FPGA
|
||||
8. use a serial terminal (like :earth_asia: [Tera Term](https://ttssh2.osdn.jp/index.html.en)) to connect to the USB-UART interface using the following configuration:
|
||||
19200 Baud, 8 data bits, 1 stop bit, no parity bits, no transmission / flow control protocol (raw bytes only), newline on `\r\n` (carriage return & newline)
|
||||
9. now you can communicate with the bootloader console and upload a new program. Check out the [example programs](https://github.com/stnolting/neorv32/tree/master/sw/example)
|
||||
and see section "Let's Get It Started" of the :page_facing_up: [NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) for further resources.
|
||||
@ -0,0 +1,108 @@
|
||||
# make a local copy of original "./../../rtl/test_setups/neorv32_test_setup_bootloader.vhd " file
|
||||
# and modify the default clock frequency: set to 50MHz
|
||||
set shell_script "cp -f ./../../../rtl/test_setups/neorv32_test_setup_bootloader.vhd . && sed -i 's/100000000/50000000/g' neorv32_test_setup_bootloader.vhd "
|
||||
exec sh -c $shell_script
|
||||
|
||||
# Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and any partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel FPGA IP License Agreement, or other applicable license
|
||||
# agreement, including, without limitation, that your use is for
|
||||
# the sole purpose of programming logic devices manufactured by
|
||||
# Intel and sold by Intel or its authorized distributors. Please
|
||||
# refer to the applicable agreement for further details, at
|
||||
# https://fpgasoftware.intel.com/eula.
|
||||
|
||||
# Quartus Prime: Generate Tcl File for Project
|
||||
# File: terasic-cyclone-V-gx=starter-kit_test.tcl
|
||||
# Generated on: Sat Apr 10 16:57:48 2021
|
||||
|
||||
# Load Quartus Prime Tcl Project package
|
||||
package require ::quartus::project
|
||||
|
||||
set need_to_close_project 0
|
||||
set make_assignments 1
|
||||
|
||||
# Check that the right project is open
|
||||
if {[is_project_open]} {
|
||||
if {[string compare $quartus(project) "terasic-cyclone-V-gx-starter-kit-test-setup"]} {
|
||||
puts "Project terasic-cyclone-V-gx-starter-kit-test-setup is not open"
|
||||
set make_assignments 0
|
||||
}
|
||||
} else {
|
||||
# Only open if not already open
|
||||
if {[project_exists de0-nano-test-setup]} {
|
||||
project_open -revision terasic-cyclone-V-gx-starter-kit-setup terasic-cyclone-V-gx-starter-kit-test-setup
|
||||
} else {
|
||||
project_new -revision terasic-cyclone-V-gx-starter-kit-test-setup terasic-cyclone-V-gx-starter-kit-test-setup
|
||||
}
|
||||
set need_to_close_project 1
|
||||
}
|
||||
|
||||
# Make assignments
|
||||
if {$make_assignments} {
|
||||
set_global_assignment -name FAMILY "Cyclone V"
|
||||
set_global_assignment -name DEVICE 5CGXFC5C6F27C7
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY neorv32_test_setup_bootloader
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "TUE JUN 4 20:41:15 2013"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name BOARD "Cyclone V GX Starter Kit"
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
|
||||
|
||||
# core VHDL files
|
||||
set core_src_dir [glob ./../../../rtl/core/*.vhd]
|
||||
foreach core_src_file $core_src_dir {
|
||||
set_global_assignment -name VHDL_FILE $core_src_file -library neorv32
|
||||
}
|
||||
|
||||
# top entity: use local modified copy of the original test setup
|
||||
set_global_assignment -name VHDL_FILE "neorv32_test_setup_bootloader.vhd"
|
||||
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk_i
|
||||
set_instance_assignment -name IO_STANDARD "1.2 V" -to rstn_i
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_o[0]
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_o[1]
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_o[2]
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_o[3]
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_o[4]
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_o[5]
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_o[6]
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_o[7]
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to uart0_rxd_i
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to uart0_txd_o
|
||||
|
||||
set_location_assignment PIN_R20 -to clk_i
|
||||
set_location_assignment PIN_P11 -to rstn_i
|
||||
set_location_assignment PIN_L7 -to gpio_o[0]
|
||||
set_location_assignment PIN_K6 -to gpio_o[1]
|
||||
set_location_assignment PIN_D8 -to gpio_o[2]
|
||||
set_location_assignment PIN_E9 -to gpio_o[3]
|
||||
set_location_assignment PIN_A5 -to gpio_o[4]
|
||||
set_location_assignment PIN_B6 -to gpio_o[5]
|
||||
set_location_assignment PIN_H8 -to gpio_o[6]
|
||||
set_location_assignment PIN_H9 -to gpio_o[7]
|
||||
set_location_assignment PIN_M9 -to uart0_rxd_i
|
||||
set_location_assignment PIN_L9 -to uart0_txd_o
|
||||
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
|
||||
# Commit assignments
|
||||
export_assignments
|
||||
}
|
||||
20
Libs/RiscV/NEORV32/setups/radiant/UPduino_v3/.gitignore
vendored
Normal file
20
Libs/RiscV/NEORV32/setups/radiant/UPduino_v3/.gitignore
vendored
Normal file
@ -0,0 +1,20 @@
|
||||
/*
|
||||
|
||||
!.gitignore
|
||||
!README.md
|
||||
|
||||
!system_pll/
|
||||
system_pll/*
|
||||
!system_pll/system_pll.ipx
|
||||
!system_pll/rtl/
|
||||
system_pll/rtl/*
|
||||
!system_pll/rtl/system_pll.v
|
||||
|
||||
!source/
|
||||
source/*
|
||||
!source/impl_1.xcf
|
||||
|
||||
!*.vhd
|
||||
!*.rdf
|
||||
!*.pdc
|
||||
!*.bin
|
||||
103
Libs/RiscV/NEORV32/setups/radiant/UPduino_v3/README.md
Normal file
103
Libs/RiscV/NEORV32/setups/radiant/UPduino_v3/README.md
Normal file
@ -0,0 +1,103 @@
|
||||
# NEORV32 Example Setup for the tinyVision.ai Inc. "UPduino v3.0" FPGA Board
|
||||
|
||||
|
||||
This example setup turns the UPduino v3.0 board, which features a Lattice iCE40 UltraPlus FPGA, into a medium-scale NEORV32 *microcontroller*.
|
||||
The processor setup provides 64kB of data and instruction memory, an RTOS-capable CPU (privileged architecture)
|
||||
and a set of standard peripherals like UART, TWI and SPI.
|
||||
|
||||
|
||||
* FPGA Board: :books: [tinyVision.ai Inc. UPduino v3 FPGA Board (GitHub)](https://github.com/tinyvision-ai-inc/UPduino-v3.0/),
|
||||
:credit_card: buy on [Tindie](https://www.tindie.com/products/tinyvision_ai/upduino-v30-low-cost-lattice-ice40-fpga-board/)
|
||||
* FPGA: Lattice iCE40 UltraPlus 5k `iCE40UP5K-SG48I`
|
||||
* Toolchain: Lattice Radiant (tested with Radiant version 3.0.0), using *Lattice Synthesis Engine (LSE)*
|
||||
* Top entity: [`neorv32_upduino_v3_top.vhd`](https://github.com/stnolting/neorv32/blob/master/boards/UPduino_v3/neorv32_upduino_v3_top.vhd) (instantiates NEORV32 top entity)
|
||||
|
||||
|
||||
### Processor Configuration
|
||||
|
||||
- [x] CPU: `rv32imacu_Zicsr_Zicntr` (reduced CPU `[m]instret` & `[m]cycle` counter width!)
|
||||
- [x] Memory: 64 kB instruction memory (internal IMEM), 64 kB data memory (internal DMEM), 4 kB bootloader ROM
|
||||
- [x] Peripherals: `GPIO`, `MTIME`, `UART0`, `SPI`, `TWI`, `PWM`, `WDT`, `TRNG`
|
||||
- [x] Clock: 24 MHz from on-chip HF oscillator (via PLL)
|
||||
- [x] Reset: via PLL "locked" signal; external "reset" via FPGA re-reconfiguration pin (`creset_n`)
|
||||
- [x] Tested with processor version [`1.6.1.6`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md)
|
||||
- [x] On-board FPGA bitstream flash storage can also be used to store/load NEORV32 application software (via the bootloader)
|
||||
|
||||
:information_source: This setup uses optimized platform-specific memory modules for the internal data and instruction memories (DMEM & IMEM). Each memory uses two
|
||||
UltraPlus SPRAM primitives (total memory size per memory = 2 x 32kB = 64kB). VHDL source file for platform-specific IMEM:
|
||||
[`neorv32_imem.ice40up_spram.vhd`](https://github.com/stnolting/neorv32/blob/master/boards/UPduino_v3/neorv32_imem.ice40up_spram.vhd);
|
||||
VHDL source file for platform-specific DMEM: [`neorv32_dmem.ice40up_spram.vhd`](https://github.com/stnolting/neorv32/blob/master/boards/UPduino_v3/neorv32_dmem.ice40up_spram.vhd).
|
||||
These platform-specific memories are used *instead* of the default platform-agnostic modules from the core's `rtl/core/mem` folder.
|
||||
|
||||
|
||||
### Interface Signals
|
||||
|
||||
:information_source: See [`neorv32_upduino_v3.pdc`](https://github.com/stnolting/neorv32/blob/master/boards/UPduino_v3/neorv32_upduino_v3.pdc)
|
||||
for the FPGA pin mapping.
|
||||
|
||||
| Top Entity Signal | FPGA Pin | Package Pin | Board Header Pin |
|
||||
|:------------------------------|:----------:|:------------:|:-----------------|
|
||||
| `flash_csn_o` (spi_cs[0]) | IOB_35B | 16 | J3-1 |
|
||||
| `flash_sck_o` | IOB_34A | 15 | J3-2 |
|
||||
| `flash_sdo_o` | IOB_32A | 14 | J3-3 |
|
||||
| `flash_sdi_i` | IOB_33B | 17 | J3-4 |
|
||||
| `gpio_i(0)` | IOB_3B_G6 | 44 | J3-9 |
|
||||
| `gpio_i(1)` | IOB_8A | 4 | J3-10 |
|
||||
| `gpio_i(2)` | IOB_9B | 3 | J3-11 |
|
||||
| `gpio_i(3)` | IOB_4A | 48 | J3-12 |
|
||||
| `gpio_o(0)` (status LED) | IOB_5B | 45 | J3-13 |
|
||||
| `gpio_o(1)` | IOB_2A | 47 | J3-14 |
|
||||
| `gpio_o(2)` | IOB_0A | 46 | J3-15 |
|
||||
| `gpio_o(3)` | IOB_6A | 2 | J3-16 |
|
||||
| - | - | - | - |
|
||||
| **reconfigure FPGA** ("_reset_") | CRESET | 8 | J2-3 |
|
||||
| `pwm_o(0)` | `gpio_i(0)` (red)| RGB2 | 41 | J2-5 |
|
||||
| `pwm_o(1)` (green) | RGB0 | 39 | J2-6 |
|
||||
| `pwm_o(2)` (blue) | RGB1 | 40 | J2-7 |
|
||||
| `twi_sda_io` | IOT_42B | 31 | J2-9 |
|
||||
| `twi_scl_io` | IOT_45A_G1 | 37 | J2-10 |
|
||||
| `spi_sdo_o` | IOT_44B | 34 | J2-11 |
|
||||
| `spi_sck_o` | IOT_49A | 43 | J2-12 |
|
||||
| `spi_csn_o` (spi_cs[1]) | IOT_48B | 36 | J2-13 |
|
||||
| `spi_sdi_i` | IOT_51A | 42 | J2-14 |
|
||||
| `uart_txd_o` (UART0) | IOT_50B | 38 | J2-15 |
|
||||
| `uart_rxd_i` (UART0) | IOT_41A | 28 | J2-16 |
|
||||
|
||||
:information_source: The TWI signals (`twi_sda_io` and `twi_scl_io`) and the reset input (`rstn_i`) require an external pull-up resistor.
|
||||
GPIO output 0 (`gpio_o(0)`, also connected to the RGB drive) is used as output for a high-active **status LED** driven by the bootloader.
|
||||
|
||||
|
||||
### FPGA Utilization
|
||||
|
||||
```
|
||||
Number of slice registers: 1754 out of 5280 (33%)
|
||||
Number of I/O registers: 11 out of 117 (9%)
|
||||
Number of LUT4s: 4882 out of 5280 (92%)
|
||||
Number of DSPs: 0 out of 8 (0%)
|
||||
Number of I2Cs: 0 out of 2 (0%)
|
||||
Number of High Speed OSCs: 1 out of 1 (100%)
|
||||
Number of Low Speed OSCs: 0 out of 1 (0%)
|
||||
Number of RGB PWM: 0 out of 1 (0%)
|
||||
Number of RGB Drivers: 1 out of 1 (100%)
|
||||
Number of SCL FILTERs: 0 out of 2 (0%)
|
||||
Number of SRAMs: 4 out of 4 (100%)
|
||||
Number of WARMBOOTs: 0 out of 1 (0%)
|
||||
Number of SPIs: 0 out of 2 (0%)
|
||||
Number of EBRs: 15 out of 30 (50%)
|
||||
Number of PLLs: 1 out of 1 (100%)
|
||||
```
|
||||
|
||||
### FPGA Setup
|
||||
|
||||
1. start Lattice Radiant (in GUI mode)
|
||||
2. click on "open project" and select `neorv32_upduino_v3.rdf` from this folder
|
||||
3. click the :arrow_forward: button to synthesize, map, place and route the design and to generate a programming file
|
||||
4. when done open the programmer (for example via "Tools" -> "Programmer"); you will need a programmer configuration, which will be created in the next steps; alternatively,
|
||||
you can use the pre-build configuration `source/impl_1.xcf`
|
||||
5. in the programmer double click on the field under "Operation" (_fast configuration_ should be the default) and select "External SPI Memory" as "Target Memory"
|
||||
6. select "SPI Serial Flash" under "SPI Flash Options / Family"
|
||||
7. select "WinBond" under "SPI Flash Options / Vendor"
|
||||
8. select "W25Q32" under "SPI Flash Options / Device"
|
||||
9. close the dialog by clicking "ok"
|
||||
10. click on "Program Device"
|
||||
|
||||
@ -0,0 +1,145 @@
|
||||
-- #################################################################################################
|
||||
-- # << NEORV32 - Processor-Internal DMEM for Lattice iCE40 UltraPlus >> #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # Memory has a physical size of 64kb (2 x SPRAMs). #
|
||||
-- # Logical size DMEM_SIZE must be less or equal. #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # BSD 3-Clause License #
|
||||
-- # #
|
||||
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
|
||||
-- # #
|
||||
-- # Redistribution and use in source and binary forms, with or without modification, are #
|
||||
-- # permitted provided that the following conditions are met: #
|
||||
-- # #
|
||||
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
|
||||
-- # conditions and the following disclaimer. #
|
||||
-- # #
|
||||
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
|
||||
-- # conditions and the following disclaimer in the documentation and/or other materials #
|
||||
-- # provided with the distribution. #
|
||||
-- # #
|
||||
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
|
||||
-- # endorse or promote products derived from this software without specific prior written #
|
||||
-- # permission. #
|
||||
-- # #
|
||||
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
|
||||
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
|
||||
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
|
||||
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
|
||||
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
|
||||
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
|
||||
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
|
||||
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
|
||||
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
|
||||
-- #################################################################################################
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library neorv32;
|
||||
use neorv32.neorv32_package.all;
|
||||
|
||||
library iCE40UP;
|
||||
use iCE40UP.components.all; -- for device primitives
|
||||
|
||||
architecture neorv32_dmem_rtl of neorv32_dmem is
|
||||
|
||||
-- advanced configuration --------------------------------------------------------------------------------
|
||||
constant spram_sleep_mode_en_c : boolean := false; -- put DMEM into sleep mode when idle (for low power)
|
||||
-- -------------------------------------------------------------------------------------------------------
|
||||
|
||||
-- IO space: module base address --
|
||||
constant hi_abb_c : natural := 31; -- high address boundary bit
|
||||
constant lo_abb_c : natural := index_size_f(64*1024); -- low address boundary bit
|
||||
|
||||
-- local signals --
|
||||
signal acc_en : std_ulogic;
|
||||
signal mem_cs : std_ulogic;
|
||||
signal rdata : std_ulogic_vector(31 downto 0);
|
||||
signal rden : std_ulogic;
|
||||
|
||||
-- SPRAM signals --
|
||||
signal spram_clk : std_logic;
|
||||
signal spram_addr : std_logic_vector(13 downto 0);
|
||||
signal spram_di_lo : std_logic_vector(15 downto 0);
|
||||
signal spram_di_hi : std_logic_vector(15 downto 0);
|
||||
signal spram_do_lo : std_logic_vector(15 downto 0);
|
||||
signal spram_do_hi : std_logic_vector(15 downto 0);
|
||||
signal spram_be_lo : std_logic_vector(03 downto 0);
|
||||
signal spram_be_hi : std_logic_vector(03 downto 0);
|
||||
signal spram_we : std_logic;
|
||||
signal spram_pwr_n : std_logic;
|
||||
signal spram_cs : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
-- Sanity Checks --------------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
assert false report "NEORV32 PROCESSOR CONFIG NOTE: Using iCE40up SPRAM-based DMEM." severity note;
|
||||
assert not (DMEM_SIZE > 64*1024) report "NEORV32 PROCESSOR CONFIG ERROR: DMEM has a fixed physical size of 64kB. Logical size must be less or equal." severity error;
|
||||
|
||||
|
||||
-- Access Control -------------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = DMEM_BASE(hi_abb_c downto lo_abb_c)) else '0';
|
||||
mem_cs <= acc_en and (rden_i or wren_i);
|
||||
|
||||
|
||||
-- Memory Access --------------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
dmem_spram_lo_inst : SP256K
|
||||
port map (
|
||||
AD => spram_addr, -- I
|
||||
DI => spram_di_lo, -- I
|
||||
MASKWE => spram_be_lo, -- I
|
||||
WE => spram_we, -- I
|
||||
CS => spram_cs, -- I
|
||||
CK => spram_clk, -- I
|
||||
STDBY => '0', -- I
|
||||
SLEEP => spram_pwr_n, -- I
|
||||
PWROFF_N => '1', -- I
|
||||
DO => spram_do_lo -- O
|
||||
);
|
||||
|
||||
dmem_spram_hi_inst : SP256K
|
||||
port map (
|
||||
AD => spram_addr, -- I
|
||||
DI => spram_di_hi, -- I
|
||||
MASKWE => spram_be_hi, -- I
|
||||
WE => spram_we, -- I
|
||||
CS => spram_cs, -- I
|
||||
CK => spram_clk, -- I
|
||||
STDBY => '0', -- I
|
||||
SLEEP => spram_pwr_n, -- I
|
||||
PWROFF_N => '1', -- I
|
||||
DO => spram_do_hi -- O
|
||||
);
|
||||
|
||||
-- access logic and signal type conversion --
|
||||
spram_clk <= std_logic(clk_i);
|
||||
spram_addr <= std_logic_vector(addr_i(13+2 downto 0+2));
|
||||
spram_di_lo <= std_logic_vector(data_i(15 downto 00));
|
||||
spram_di_hi <= std_logic_vector(data_i(31 downto 16));
|
||||
spram_we <= '1' when ((acc_en and wren_i) = '1') else '0'; -- global write enable
|
||||
spram_cs <= std_logic(mem_cs);
|
||||
spram_be_lo <= std_logic(ben_i(1)) & std_logic(ben_i(1)) & std_logic(ben_i(0)) & std_logic(ben_i(0)); -- low byte write enable
|
||||
spram_be_hi <= std_logic(ben_i(3)) & std_logic(ben_i(3)) & std_logic(ben_i(2)) & std_logic(ben_i(2)); -- high byte write enable
|
||||
spram_pwr_n <= '0' when ((spram_sleep_mode_en_c = false) or (mem_cs = '1')) else '1'; -- LP mode disabled or IMEM selected
|
||||
rdata <= std_ulogic_vector(spram_do_hi) & std_ulogic_vector(spram_do_lo);
|
||||
|
||||
buffer_ff: process(clk_i)
|
||||
begin
|
||||
if rising_edge(clk_i) then
|
||||
ack_o <= mem_cs;
|
||||
rden <= acc_en and rden_i;
|
||||
end if;
|
||||
end process buffer_ff;
|
||||
|
||||
-- output gate --
|
||||
data_o <= rdata when (rden = '1') else (others => '0');
|
||||
|
||||
|
||||
end neorv32_dmem_rtl;
|
||||
@ -0,0 +1,146 @@
|
||||
-- #################################################################################################
|
||||
-- # << NEORV32 - Processor-Internal IMEM for Lattice iCE40 UltraPlus >> #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # Memory has a physical size of 64kb (2 x SPRAMs). #
|
||||
-- # Logical size IMEM_SIZE must be less or equal. #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # BSD 3-Clause License #
|
||||
-- # #
|
||||
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
|
||||
-- # #
|
||||
-- # Redistribution and use in source and binary forms, with or without modification, are #
|
||||
-- # permitted provided that the following conditions are met: #
|
||||
-- # #
|
||||
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
|
||||
-- # conditions and the following disclaimer. #
|
||||
-- # #
|
||||
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
|
||||
-- # conditions and the following disclaimer in the documentation and/or other materials #
|
||||
-- # provided with the distribution. #
|
||||
-- # #
|
||||
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
|
||||
-- # endorse or promote products derived from this software without specific prior written #
|
||||
-- # permission. #
|
||||
-- # #
|
||||
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
|
||||
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
|
||||
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
|
||||
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
|
||||
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
|
||||
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
|
||||
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
|
||||
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
|
||||
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
|
||||
-- #################################################################################################
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library neorv32;
|
||||
use neorv32.neorv32_package.all;
|
||||
|
||||
library iCE40UP;
|
||||
use iCE40UP.components.all; -- for device primitives
|
||||
|
||||
architecture neorv32_imem_rtl of neorv32_imem is
|
||||
|
||||
-- advanced configuration --------------------------------------------------------------------------------
|
||||
constant spram_sleep_mode_en_c : boolean := false; -- put IMEM into sleep mode when idle (for low power)
|
||||
-- -------------------------------------------------------------------------------------------------------
|
||||
|
||||
-- IO space: module base address --
|
||||
constant hi_abb_c : natural := 31; -- high address boundary bit
|
||||
constant lo_abb_c : natural := index_size_f(64*1024); -- low address boundary bit
|
||||
|
||||
-- local signals --
|
||||
signal acc_en : std_ulogic;
|
||||
signal mem_cs : std_ulogic;
|
||||
signal rdata : std_ulogic_vector(31 downto 0);
|
||||
signal rden : std_ulogic;
|
||||
|
||||
-- SPRAM signals --
|
||||
signal spram_clk : std_logic;
|
||||
signal spram_addr : std_logic_vector(13 downto 0);
|
||||
signal spram_di_lo : std_logic_vector(15 downto 0);
|
||||
signal spram_di_hi : std_logic_vector(15 downto 0);
|
||||
signal spram_do_lo : std_logic_vector(15 downto 0);
|
||||
signal spram_do_hi : std_logic_vector(15 downto 0);
|
||||
signal spram_be_lo : std_logic_vector(03 downto 0);
|
||||
signal spram_be_hi : std_logic_vector(03 downto 0);
|
||||
signal spram_we : std_logic;
|
||||
signal spram_pwr_n : std_logic;
|
||||
signal spram_cs : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
-- Sanity Checks --------------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
assert false report "NEORV32 PROCESSOR CONFIG NOTE: Using iCE40up SPRAM-based IMEM." severity note;
|
||||
assert not (IMEM_AS_IROM = true) report "NEORV32 PROCESSOR CONFIG ERROR: ICE40 Ultra Plus SPRAM cannot be initialized by bitstream!" severity failure;
|
||||
assert not (IMEM_SIZE > 64*1024) report "NEORV32 PROCESSOR CONFIG ERROR: IMEM has a fixed physical size of 64kB. Logical size must be less or equal." severity error;
|
||||
|
||||
|
||||
-- Access Control -------------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = IMEM_BASE(hi_abb_c downto lo_abb_c)) else '0';
|
||||
mem_cs <= acc_en and (rden_i or wren_i);
|
||||
|
||||
|
||||
-- Memory Access --------------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
imem_spram_lo_inst : SP256K
|
||||
port map (
|
||||
AD => spram_addr, -- I
|
||||
DI => spram_di_lo, -- I
|
||||
MASKWE => spram_be_lo, -- I
|
||||
WE => spram_we, -- I
|
||||
CS => spram_cs, -- I
|
||||
CK => spram_clk, -- I
|
||||
STDBY => '0', -- I
|
||||
SLEEP => spram_pwr_n, -- I
|
||||
PWROFF_N => '1', -- I
|
||||
DO => spram_do_lo -- O
|
||||
);
|
||||
|
||||
imem_spram_hi_inst : SP256K
|
||||
port map (
|
||||
AD => spram_addr, -- I
|
||||
DI => spram_di_hi, -- I
|
||||
MASKWE => spram_be_hi, -- I
|
||||
WE => spram_we, -- I
|
||||
CS => spram_cs, -- I
|
||||
CK => spram_clk, -- I
|
||||
STDBY => '0', -- I
|
||||
SLEEP => spram_pwr_n, -- I
|
||||
PWROFF_N => '1', -- I
|
||||
DO => spram_do_hi -- O
|
||||
);
|
||||
|
||||
-- access logic and signal type conversion --
|
||||
spram_clk <= std_logic(clk_i);
|
||||
spram_addr <= std_logic_vector(addr_i(13+2 downto 0+2));
|
||||
spram_di_lo <= std_logic_vector(data_i(15 downto 00));
|
||||
spram_di_hi <= std_logic_vector(data_i(31 downto 16));
|
||||
spram_we <= '1' when ((acc_en and wren_i) = '1') else '0'; -- global write enable
|
||||
spram_cs <= std_logic(mem_cs);
|
||||
spram_be_lo <= std_logic(ben_i(1)) & std_logic(ben_i(1)) & std_logic(ben_i(0)) & std_logic(ben_i(0)); -- low byte write enable
|
||||
spram_be_hi <= std_logic(ben_i(3)) & std_logic(ben_i(3)) & std_logic(ben_i(2)) & std_logic(ben_i(2)); -- high byte write enable
|
||||
spram_pwr_n <= '0' when ((spram_sleep_mode_en_c = false) or (mem_cs = '1')) else '1'; -- LP mode disabled or IMEM selected
|
||||
rdata <= std_ulogic_vector(spram_do_hi) & std_ulogic_vector(spram_do_lo);
|
||||
|
||||
buffer_ff: process(clk_i)
|
||||
begin
|
||||
if rising_edge(clk_i) then
|
||||
ack_o <= mem_cs;
|
||||
rden <= acc_en and rden_i;
|
||||
end if;
|
||||
end process buffer_ff;
|
||||
|
||||
-- output gate --
|
||||
data_o <= rdata when (rden = '1') else (others => '0');
|
||||
|
||||
|
||||
end neorv32_imem_rtl;
|
||||
@ -0,0 +1,41 @@
|
||||
# Radiant pin mapping for the "tinyvision.ai Inc. UPduino v3" FPGA board
|
||||
|
||||
## Clock (on-chip hf oscillator)
|
||||
#create_clock -period 41.666666 -name hf_osc_clk [get_nets hf_osc_clk]
|
||||
|
||||
## UART (uart0)
|
||||
ldc_set_location -site {38} [get_ports uart_txd_o]
|
||||
ldc_set_location -site {28} [get_ports uart_rxd_i]
|
||||
|
||||
## SPI - on-board flash
|
||||
ldc_set_location -site {14} [get_ports flash_sdo_o]
|
||||
ldc_set_location -site {15} [get_ports flash_sck_o]
|
||||
ldc_set_location -site {16} [get_ports flash_csn_o]
|
||||
ldc_set_location -site {17} [get_ports flash_sdi_i]
|
||||
|
||||
## SPI - user port
|
||||
ldc_set_location -site {34} [get_ports spi_sdo_o]
|
||||
ldc_set_location -site {43} [get_ports spi_sck_o]
|
||||
ldc_set_location -site {36} [get_ports spi_csn_o]
|
||||
ldc_set_location -site {42} [get_ports spi_sdi_i]
|
||||
|
||||
## TWI
|
||||
ldc_set_location -site {31} [get_ports twi_sda_io]
|
||||
ldc_set_location -site {37} [get_ports twi_scl_io]
|
||||
|
||||
## GPIO - input
|
||||
ldc_set_location -site {44} [get_ports {gpio_i[0]}]
|
||||
ldc_set_location -site {4} [get_ports {gpio_i[1]}]
|
||||
ldc_set_location -site {3} [get_ports {gpio_i[2]}]
|
||||
ldc_set_location -site {48} [get_ports {gpio_i[3]}]
|
||||
|
||||
## GPIO - output
|
||||
ldc_set_location -site {45} [get_ports {gpio_o[0]}]
|
||||
ldc_set_location -site {47} [get_ports {gpio_o[1]}]
|
||||
ldc_set_location -site {46} [get_ports {gpio_o[2]}]
|
||||
ldc_set_location -site {2} [get_ports {gpio_o[3]}]
|
||||
|
||||
## RGB power LED
|
||||
ldc_set_location -site {39} [get_ports {pwm_o[0]}]
|
||||
ldc_set_location -site {40} [get_ports {pwm_o[1]}]
|
||||
ldc_set_location -site {41} [get_ports {pwm_o[2]}]
|
||||
@ -0,0 +1,137 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<RadiantProject version="4.2" title="neorv32_upduino_v3" device="iCE40UP5K-SG48I" performance_grade="High-Performance_1.2V" default_implementation="impl_1">
|
||||
<Options/>
|
||||
<Implementation title="impl_1" dir="impl_1" description="impl_1" synthesis="lse" default_strategy="Strategy1">
|
||||
<Options def_top="neorv32_upduino_v3_top" top="neorv32_upduino_v3_top"/>
|
||||
<Source name="../../../rtl/core/neorv32_application_image.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options lib="neorv32"/>
|
||||
</Source>
|
||||
<Source name="../../../rtl/core/neorv32_boot_rom.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options lib="neorv32"/>
|
||||
</Source>
|
||||
<Source name="../../../rtl/core/neorv32_bootloader_image.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options lib="neorv32"/>
|
||||
</Source>
|
||||
<Source name="../../../rtl/core/neorv32_busswitch.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options lib="neorv32"/>
|
||||
</Source>
|
||||
<Source name="../../../rtl/core/neorv32_bus_keeper.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options lib="neorv32"/>
|
||||
</Source>
|
||||
<Source name="../../../rtl/core/neorv32_cfs.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options lib="neorv32"/>
|
||||
</Source>
|
||||
<Source name="../../../rtl/core/neorv32_cpu.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options lib="neorv32"/>
|
||||
</Source>
|
||||
<Source name="../../../rtl/core/neorv32_cpu_alu.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options lib="neorv32"/>
|
||||
</Source>
|
||||
<Source name="../../../rtl/core/neorv32_cpu_bus.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options lib="neorv32"/>
|
||||
</Source>
|
||||
<Source name="../../../rtl/core/neorv32_cpu_control.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options lib="neorv32"/>
|
||||
</Source>
|
||||
<Source name="../../../rtl/core/neorv32_cpu_cp_fpu.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options lib="neorv32"/>
|
||||
</Source>
|
||||
<Source name="../../../rtl/core/neorv32_cpu_cp_bitmanip.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options lib="neorv32"/>
|
||||
</Source>
|
||||
<Source name="../../../rtl/core/neorv32_cpu_cp_muldiv.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options lib="neorv32"/>
|
||||
</Source>
|
||||
<Source name="../../../rtl/core/neorv32_cpu_cp_shifter.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options lib="neorv32"/>
|
||||
</Source>
|
||||
<Source name="../../../rtl/core/neorv32_cpu_decompressor.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options lib="neorv32"/>
|
||||
</Source>
|
||||
<Source name="../../../rtl/core/neorv32_cpu_regfile.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options lib="neorv32"/>
|
||||
</Source>
|
||||
<Source name="../../../rtl/core/neorv32_debug_dm.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options lib="neorv32"/>
|
||||
</Source>
|
||||
<Source name="../../../rtl/core/neorv32_debug_dtm.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options lib="neorv32"/>
|
||||
</Source>
|
||||
<Source name="../../../rtl/core/neorv32_fifo.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options lib="neorv32"/>
|
||||
</Source>
|
||||
<Source name="../../../rtl/core/neorv32_gpio.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options lib="neorv32"/>
|
||||
</Source>
|
||||
<Source name="../../../rtl/core/neorv32_gptmr.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options lib="neorv32"/>
|
||||
</Source>
|
||||
<Source name="../../../rtl/core/neorv32_icache.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options lib="neorv32"/>
|
||||
</Source>
|
||||
<Source name="../../../rtl/core/neorv32_mtime.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options lib="neorv32"/>
|
||||
</Source>
|
||||
<Source name="../../../rtl/core/neorv32_neoled.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options lib="neorv32"/>
|
||||
</Source>
|
||||
<Source name="../../../rtl/core/neorv32_package.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options lib="neorv32"/>
|
||||
</Source>
|
||||
<Source name="../../../rtl/core/neorv32_pwm.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options lib="neorv32"/>
|
||||
</Source>
|
||||
<Source name="../../../rtl/core/neorv32_spi.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options lib="neorv32"/>
|
||||
</Source>
|
||||
<Source name="../../../rtl/core/neorv32_sysinfo.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options lib="neorv32"/>
|
||||
</Source>
|
||||
<Source name="../../../rtl/core/neorv32_top.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options lib="neorv32"/>
|
||||
</Source>
|
||||
<Source name="../../../rtl/core/neorv32_trng.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options lib="neorv32"/>
|
||||
</Source>
|
||||
<Source name="../../../rtl/core/neorv32_twi.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options lib="neorv32"/>
|
||||
</Source>
|
||||
<Source name="../../../rtl/core/neorv32_uart.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options lib="neorv32"/>
|
||||
</Source>
|
||||
<Source name="../../../rtl/core/neorv32_wdt.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options lib="neorv32"/>
|
||||
</Source>
|
||||
<Source name="../../../rtl/core/neorv32_wishbone.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options lib="neorv32"/>
|
||||
</Source>
|
||||
<Source name="../../../rtl/core/neorv32_xirq.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options lib="neorv32"/>
|
||||
</Source>
|
||||
<Source name="../../../rtl/core/neorv32_dmem.entity.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options lib="neorv32"/>
|
||||
</Source>
|
||||
<Source name="../../../rtl/core/neorv32_imem.entity.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options lib="neorv32"/>
|
||||
</Source>
|
||||
<Source name="neorv32_dmem.ice40up_spram.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options lib="neorv32"/>
|
||||
</Source>
|
||||
<Source name="neorv32_imem.ice40up_spram.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options lib="neorv32"/>
|
||||
</Source>
|
||||
<Source name="neorv32_upduino_v3_top.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options lib="work" top_module="neorv32_upduino_v3_top"/>
|
||||
</Source>
|
||||
<Source name="system_pll/system_pll.ipx" type="IPX_Module" type_short="IPX">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="neorv32_upduino_v3.pdc" type="Physical Constraints File" type_short="PDC">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="source/impl_1.xcf" type="Programming Project File" type_short="Programming">
|
||||
<Options/>
|
||||
</Source>
|
||||
</Implementation>
|
||||
<Strategy name="Strategy1" file="neorv32_upduino_v3.sty"/>
|
||||
</RadiantProject>
|
||||
@ -0,0 +1,248 @@
|
||||
-- #################################################################################################
|
||||
-- # << NEORV32 - Example setup for the tinyVision.ai Inc. "UPduino v3" (c) Board >> #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # BSD 3-Clause License #
|
||||
-- # #
|
||||
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
|
||||
-- # #
|
||||
-- # Redistribution and use in source and binary forms, with or without modification, are #
|
||||
-- # permitted provided that the following conditions are met: #
|
||||
-- # #
|
||||
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
|
||||
-- # conditions and the following disclaimer. #
|
||||
-- # #
|
||||
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
|
||||
-- # conditions and the following disclaimer in the documentation and/or other materials #
|
||||
-- # provided with the distribution. #
|
||||
-- # #
|
||||
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
|
||||
-- # endorse or promote products derived from this software without specific prior written #
|
||||
-- # permission. #
|
||||
-- # #
|
||||
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
|
||||
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
|
||||
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
|
||||
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
|
||||
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
|
||||
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
|
||||
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
|
||||
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
|
||||
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
|
||||
-- # ********************************************************************************************* #
|
||||
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
|
||||
-- #################################################################################################
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library neorv32;
|
||||
use neorv32.neorv32_package.all;
|
||||
|
||||
library work;
|
||||
use work.all;
|
||||
|
||||
library iCE40UP;
|
||||
use iCE40UP.components.all; -- for device primitives
|
||||
|
||||
entity neorv32_upduino_v3_top is
|
||||
port (
|
||||
-- UART (uart0) --
|
||||
uart_txd_o : out std_ulogic;
|
||||
uart_rxd_i : in std_ulogic;
|
||||
-- SPI to on-board flash --
|
||||
flash_sck_o : out std_ulogic;
|
||||
flash_sdo_o : out std_ulogic;
|
||||
flash_sdi_i : in std_ulogic;
|
||||
flash_csn_o : out std_ulogic; -- NEORV32.SPI_CS(0)
|
||||
-- SPI to IO pins --
|
||||
spi_sck_o : out std_ulogic;
|
||||
spi_sdo_o : out std_ulogic;
|
||||
spi_sdi_i : in std_ulogic;
|
||||
spi_csn_o : out std_ulogic; -- NEORV32.SPI_CS(1)
|
||||
-- TWI --
|
||||
twi_sda_io : inout std_logic;
|
||||
twi_scl_io : inout std_logic;
|
||||
-- GPIO --
|
||||
gpio_i : in std_ulogic_vector(3 downto 0);
|
||||
gpio_o : out std_ulogic_vector(3 downto 0);
|
||||
-- PWM (to on-board RGB power LED) --
|
||||
pwm_o : out std_ulogic_vector(2 downto 0)
|
||||
);
|
||||
end neorv32_upduino_v3_top;
|
||||
|
||||
architecture neorv32_upduino_v3_top_rtl of neorv32_upduino_v3_top is
|
||||
|
||||
-- configuration --
|
||||
constant f_clock_c : natural := 24000000; -- PLL output clock frequency in Hz
|
||||
|
||||
-- On-chip oscillator --
|
||||
signal hf_osc_clk : std_logic;
|
||||
|
||||
-- PLL (macro generated by radiant) --
|
||||
component system_pll
|
||||
port (
|
||||
ref_clk_i : in std_logic;
|
||||
rst_n_i : in std_logic;
|
||||
lock_o : out std_logic;
|
||||
outcore_o : out std_logic;
|
||||
outglobal_o : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
signal pll_rstn : std_logic;
|
||||
signal pll_clk : std_logic;
|
||||
|
||||
-- CPU --
|
||||
signal cpu_clk : std_ulogic;
|
||||
signal cpu_rstn : std_ulogic;
|
||||
|
||||
-- internal IO connection --
|
||||
signal con_pwm : std_ulogic_vector(02 downto 0);
|
||||
signal con_spi_sck : std_ulogic;
|
||||
signal con_spi_sdi : std_ulogic;
|
||||
signal con_spi_sdo : std_ulogic;
|
||||
signal con_spi_csn : std_ulogic_vector(07 downto 0);
|
||||
signal con_gpio_i : std_ulogic_vector(63 downto 0);
|
||||
signal con_gpio_o : std_ulogic_vector(63 downto 0);
|
||||
|
||||
-- Misc --
|
||||
signal pwm_drive : std_logic_vector(2 downto 0);
|
||||
signal pwm_driven : std_ulogic_vector(2 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
-- On-Chip HF Oscillator ------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
HSOSC_inst : HSOSC
|
||||
generic map (
|
||||
CLKHF_DIV => "0b01" -- 24 MHz
|
||||
)
|
||||
port map (
|
||||
CLKHFPU => '1',
|
||||
CLKHFEN => '1',
|
||||
CLKHF => hf_osc_clk
|
||||
);
|
||||
|
||||
|
||||
-- System PLL -----------------------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
system_pll_inst: system_pll
|
||||
port map (
|
||||
ref_clk_i => hf_osc_clk,
|
||||
rst_n_i => '1',
|
||||
lock_o => pll_rstn,
|
||||
outcore_o => open,
|
||||
outglobal_o => pll_clk
|
||||
);
|
||||
|
||||
cpu_clk <= std_ulogic(pll_clk);
|
||||
cpu_rstn <= std_ulogic(pll_rstn);
|
||||
|
||||
|
||||
-- The core of the problem ----------------------------------------------------------------
|
||||
-- -------------------------------------------------------------------------------------------
|
||||
neorv32_inst: neorv32_top
|
||||
generic map (
|
||||
-- General --
|
||||
CLOCK_FREQUENCY => f_clock_c, -- clock frequency of clk_i in Hz
|
||||
HW_THREAD_ID => 0, -- hardware thread id (32-bit)
|
||||
INT_BOOTLOADER_EN => true, -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
|
||||
|
||||
-- RISC-V CPU Extensions --
|
||||
CPU_EXTENSION_RISCV_A => true, -- implement atomic extension?
|
||||
CPU_EXTENSION_RISCV_C => true, -- implement compressed extension?
|
||||
CPU_EXTENSION_RISCV_M => true, -- implement mul/div extension?
|
||||
CPU_EXTENSION_RISCV_U => true, -- implement user mode extension?
|
||||
CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system?
|
||||
CPU_EXTENSION_RISCV_Zicntr => true, -- implement base counters?
|
||||
CPU_EXTENSION_RISCV_Zifencei => true, -- implement instruction stream sync.?
|
||||
|
||||
-- Extension Options --
|
||||
CPU_CNT_WIDTH => 34, -- total width of CPU cycle and instret counters (0..64)
|
||||
|
||||
-- Internal Instruction memory --
|
||||
MEM_INT_IMEM_EN => true, -- implement processor-internal instruction memory
|
||||
MEM_INT_IMEM_SIZE => 64*1024, -- size of processor-internal instruction memory in bytes
|
||||
|
||||
-- Internal Data memory --
|
||||
MEM_INT_DMEM_EN => true, -- implement processor-internal data memory
|
||||
MEM_INT_DMEM_SIZE => 64*1024, -- size of processor-internal data memory in bytes
|
||||
|
||||
-- Processor peripherals --
|
||||
IO_GPIO_EN => true, -- implement general purpose input/output port unit (GPIO)?
|
||||
IO_MTIME_EN => true, -- implement machine system timer (MTIME)?
|
||||
IO_UART0_EN => true, -- implement primary universal asynchronous receiver/transmitter (UART0)?
|
||||
IO_SPI_EN => true, -- implement serial peripheral interface (SPI)?
|
||||
IO_TWI_EN => true, -- implement two-wire interface (TWI)?
|
||||
IO_PWM_NUM_CH => 3, -- number of PWM channels to implement (0..60); 0 = disabled
|
||||
IO_WDT_EN => true, -- implement watch dog timer (WDT)?
|
||||
IO_TRNG_EN => true -- implement true random number generator (TRNG)?
|
||||
)
|
||||
port map (
|
||||
-- Global control --
|
||||
clk_i => cpu_clk, -- global clock, rising edge
|
||||
rstn_i => cpu_rstn, -- global reset, low-active, async
|
||||
|
||||
-- GPIO (available if IO_GPIO_EN = true) --
|
||||
gpio_o => con_gpio_o, -- parallel output
|
||||
gpio_i => con_gpio_i, -- parallel input
|
||||
|
||||
-- primary UART0 (available if IO_UART0_EN = true) --
|
||||
uart0_txd_o => uart_txd_o, -- UART0 send data
|
||||
uart0_rxd_i => uart_rxd_i, -- UART0 receive data
|
||||
|
||||
-- SPI (available if IO_SPI_EN = true) --
|
||||
spi_sck_o => con_spi_sck,
|
||||
spi_sdo_o => con_spi_sdo,
|
||||
spi_sdi_i => con_spi_sdi,
|
||||
spi_csn_o => con_spi_csn,
|
||||
|
||||
-- TWI (available if IO_TWI_EN = true) --
|
||||
twi_sda_io => twi_sda_io, -- twi serial data line
|
||||
twi_scl_io => twi_scl_io, -- twi serial clock line
|
||||
|
||||
-- PWM (available if IO_PWM_EN = true) --
|
||||
pwm_o => con_pwm -- pwm channels
|
||||
);
|
||||
|
||||
-- GPIO --
|
||||
con_gpio_i <= x"000000000000000" & gpio_i(3 downto 0);
|
||||
gpio_o(3 downto 0) <= con_gpio_o(3 downto 0);
|
||||
|
||||
-- SPI --
|
||||
flash_sck_o <= con_spi_sck;
|
||||
flash_sdo_o <= con_spi_sdo;
|
||||
flash_csn_o <= con_spi_csn(0);
|
||||
spi_sck_o <= con_spi_sck;
|
||||
spi_sdo_o <= con_spi_sdo;
|
||||
spi_csn_o <= con_spi_csn(1);
|
||||
con_spi_sdi <= flash_sdi_i when (con_spi_csn(0) = '0') else spi_sdi_i;
|
||||
|
||||
-- RGB --
|
||||
pwm_drive(0) <= std_logic(con_pwm(0) or con_gpio_o(0)); -- bit 0: red - pwm channel 0 OR gpio_o(0) [status LED]
|
||||
pwm_drive(1) <= std_logic(con_pwm(1)); -- bit 1: green - pwm channel 1
|
||||
pwm_drive(2) <= std_logic(con_pwm(2)); -- bit 2: blue - pwm channel 2
|
||||
|
||||
RGB_inst: RGB
|
||||
generic map (
|
||||
CURRENT_MODE => "1",
|
||||
RGB0_CURRENT => "0b000001",
|
||||
RGB1_CURRENT => "0b000001",
|
||||
RGB2_CURRENT => "0b000001"
|
||||
)
|
||||
port map (
|
||||
CURREN => '1', -- I
|
||||
RGBLEDEN => '1', -- I
|
||||
RGB0PWM => pwm_drive(1), -- I - green
|
||||
RGB1PWM => pwm_drive(2), -- I - blue
|
||||
RGB2PWM => pwm_drive(0), -- I - red
|
||||
RGB2 => pwm_driven(2), -- O - red
|
||||
RGB1 => pwm_driven(1), -- O - blue
|
||||
RGB0 => pwm_driven(0) -- O - green
|
||||
);
|
||||
|
||||
pwm_o <= std_ulogic_vector(pwm_driven);
|
||||
|
||||
|
||||
end neorv32_upduino_v3_top_rtl;
|
||||
108
Libs/RiscV/NEORV32/setups/radiant/UPduino_v3/source/impl_1.xcf
Normal file
108
Libs/RiscV/NEORV32/setups/radiant/UPduino_v3/source/impl_1.xcf
Normal file
@ -0,0 +1,108 @@
|
||||
<?xml version='1.0' encoding='utf-8' ?>
|
||||
<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
|
||||
<ispXCF version="R3.0">
|
||||
<Comment></Comment>
|
||||
<Chain>
|
||||
<Comm>SPI</Comm>
|
||||
<Device>
|
||||
<SelectedProg value="TRUE"/>
|
||||
<Pos>1</Pos>
|
||||
<Vendor>Lattice</Vendor>
|
||||
<Family>iCE40 UltraPlus</Family>
|
||||
<Name>iCE40UP5K</Name>
|
||||
<Package>All</Package>
|
||||
<Bypass>
|
||||
<InstrLen>8</InstrLen>
|
||||
<InstrVal>11111111</InstrVal>
|
||||
<BScanLen>1</BScanLen>
|
||||
<BScanVal>0</BScanVal>
|
||||
</Bypass>
|
||||
<File>../../impl_1/neorv32_upduino_v3_impl_1.bin</File>
|
||||
<FileTime>11/04/21 21:44:40</FileTime>
|
||||
<MemoryType>External SPI Flash Memory (SPI FLASH)</MemoryType>
|
||||
<Operation>Erase,Program,Verify</Operation>
|
||||
<Option>
|
||||
<SVFVendor>JTAG STANDARD</SVFVendor>
|
||||
<SVFProcessor>SVF Processor</SVFProcessor>
|
||||
<AccessMode>Direct Programming</AccessMode>
|
||||
</Option>
|
||||
<FPGALoader>
|
||||
<CPLDDevice>
|
||||
<Device>
|
||||
<Pos>1</Pos>
|
||||
<Vendor>Lattice</Vendor>
|
||||
<Family>iCE40 UltraPlus</Family>
|
||||
<Name>iCE40UP5K</Name>
|
||||
<IDCode>0x11200639</IDCode>
|
||||
<Package>All</Package>
|
||||
<PON>iCE40UP5K</PON>
|
||||
<Bypass>
|
||||
<InstrLen>8</InstrLen>
|
||||
<InstrVal>11111111</InstrVal>
|
||||
<BScanLen>1</BScanLen>
|
||||
<BScanVal>0</BScanVal>
|
||||
</Bypass>
|
||||
<MemoryType>Compressed Random Access Memory (CRAM)</MemoryType>
|
||||
<Operation>Bypass</Operation>
|
||||
<Option>
|
||||
<SVFVendor>JTAG STANDARD</SVFVendor>
|
||||
<IOState>HighZ</IOState>
|
||||
<IOVectorData></IOVectorData>
|
||||
<SVFProcessor>SVF Processor</SVFProcessor>
|
||||
<AccessMode>Direct Programming</AccessMode>
|
||||
</Option>
|
||||
</Device>
|
||||
</CPLDDevice>
|
||||
<FlashDevice>
|
||||
<Device>
|
||||
<Pos>1</Pos>
|
||||
<Vendor>WinBond</Vendor>
|
||||
<Family>SPI Serial Flash</Family>
|
||||
<Name>W25Q32</Name>
|
||||
<IDCode>0x15</IDCode>
|
||||
<Package>8-pin SOIC</Package>
|
||||
<Operation>Erase,Program,Verify</Operation>
|
||||
<File>../../impl_1/neorv32_upduino_v3_impl_1.bin</File>
|
||||
<AddressBase>0x00000000</AddressBase>
|
||||
<EndAddress>0x003F0000</EndAddress>
|
||||
<DeviceSize>32</DeviceSize>
|
||||
<DataSize>104156</DataSize>
|
||||
<NumberOfDevices>1</NumberOfDevices>
|
||||
<ReInitialize value="FALSE"/>
|
||||
</Device>
|
||||
</FlashDevice>
|
||||
<FPGADevice>
|
||||
<Device>
|
||||
<Pos>1</Pos>
|
||||
<Name></Name>
|
||||
<File>N:/Projects/neorv32/boards/UPduino_v3/impl_1/neorv32_upduino_v3_impl_1.bin</File>
|
||||
<LocalChainList>
|
||||
<LocalDevice index="-99"
|
||||
name="Unknown"
|
||||
file="N:/Projects/neorv32/boards/UPduino_v3/impl_1/neorv32_upduino_v3_impl_1.bin"/>
|
||||
</LocalChainList>
|
||||
<Option>
|
||||
<SVFVendor>JTAG STANDARD</SVFVendor>
|
||||
<SVFProcessor>SVF Processor</SVFProcessor>
|
||||
</Option>
|
||||
</Device>
|
||||
</FPGADevice>
|
||||
</FPGALoader>
|
||||
</Device>
|
||||
</Chain>
|
||||
<ProjectOptions>
|
||||
<Program>SEQUENTIAL</Program>
|
||||
<Process>ENTIRED CHAIN</Process>
|
||||
<OperationOverride>No Override</OperationOverride>
|
||||
<StartTAP>TLR</StartTAP>
|
||||
<EndTAP>TLR</EndTAP>
|
||||
<DisableCheckBoard value="TRUE"/>
|
||||
<VerifyUsercode value="FALSE"/>
|
||||
<TCKDelay>1</TCKDelay>
|
||||
</ProjectOptions>
|
||||
<CableOptions>
|
||||
<CableName>USB2</CableName>
|
||||
<PortAdd>FTUSB-1</PortAdd>
|
||||
<USBID>UPduino v3.0 Location 0002 Serial </USBID>
|
||||
</CableOptions>
|
||||
</ispXCF>
|
||||
@ -0,0 +1,222 @@
|
||||
|
||||
/*******************************************************************************
|
||||
Verilog netlist generated by IPGEN Lattice Radiant Software (64-bit)
|
||||
2.1.0.27.2
|
||||
Soft IP Version: 1.0.1
|
||||
Wed May 12 22:58:47 2021
|
||||
*******************************************************************************/
|
||||
/*******************************************************************************
|
||||
Wrapper Module generated per user settings.
|
||||
*******************************************************************************/
|
||||
module system_pll (ref_clk_i,
|
||||
rst_n_i,
|
||||
lock_o,
|
||||
outcore_o,
|
||||
outglobal_o) ;
|
||||
input ref_clk_i ;
|
||||
input rst_n_i ;
|
||||
output lock_o ;
|
||||
output outcore_o ;
|
||||
output outglobal_o ;
|
||||
system_pll_ipgen_lscc_pll #(.DIVR("0"),
|
||||
.FILTER_RANGE("2"),
|
||||
.FREQUENCY_PIN_REFERENCECLK("24.000000"),
|
||||
.FEEDBACK_PATH("PHASE_AND_DELAY"),
|
||||
.EXTERNAL_DIVIDE_FACTOR("NONE"),
|
||||
.DIVF("0"),
|
||||
.DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
|
||||
.FDA_FEEDBACK("0"),
|
||||
.SHIFTREG_DIV_MODE("0"),
|
||||
.PLLOUT_SELECT_PORTA("SHIFTREG_0deg"),
|
||||
.PLLOUT_SELECT_PORTB("SHIFTREG_0deg"),
|
||||
.DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
|
||||
.FDA_RELATIVE("0"),
|
||||
.DIVQ("3"),
|
||||
.ENABLE_ICEGATE_PORTA("0"),
|
||||
.ENABLE_ICEGATE_PORTB("0")) lscc_pll_inst (.ref_clk_i(ref_clk_i),
|
||||
.rst_n_i(rst_n_i),
|
||||
.feedback_i(1'b0),
|
||||
.dynamic_delay_i({4'b0000,
|
||||
4'b0000}),
|
||||
.bypass_i(1'b0),
|
||||
.latch_i(1'b0),
|
||||
.lock_o(lock_o),
|
||||
.outcore_o(outcore_o),
|
||||
.outglobal_o(outglobal_o),
|
||||
.outcoreb_o(),
|
||||
.outglobalb_o(),
|
||||
.sclk_i(),
|
||||
.sdi_i(),
|
||||
.sdo_o()) ;
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
// =============================================================================
|
||||
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
||||
// -----------------------------------------------------------------------------
|
||||
// Copyright (c) 2017 by Lattice Semiconductor Corporation
|
||||
// ALL RIGHTS RESERVED
|
||||
// -----------------------------------------------------------------------------
|
||||
//
|
||||
// Permission:
|
||||
//
|
||||
// Lattice SG Pte. Ltd. grants permission to use this code
|
||||
// pursuant to the terms of the Lattice Reference Design License Agreement.
|
||||
//
|
||||
//
|
||||
// Disclaimer:
|
||||
//
|
||||
// This VHDL or Verilog source code is intended as a design reference
|
||||
// which illustrates how these types of functions can be implemented.
|
||||
// It is the user's responsibility to verify their design for
|
||||
// consistency and functionality through the use of formal
|
||||
// verification methods. Lattice provides no warranty
|
||||
// regarding the use or functionality of this code.
|
||||
//
|
||||
// -----------------------------------------------------------------------------
|
||||
//
|
||||
// Lattice SG Pte. Ltd.
|
||||
// 101 Thomson Road, United Square #07-02
|
||||
// Singapore 307591
|
||||
//
|
||||
//
|
||||
// TEL: 1-800-Lattice (USA and Canada)
|
||||
// +65-6631-2000 (Singapore)
|
||||
// +1-503-268-8001 (other locations)
|
||||
//
|
||||
// web: http://www.latticesemi.com/
|
||||
// email: techsupport@latticesemi.com
|
||||
//
|
||||
// -----------------------------------------------------------------------------
|
||||
//
|
||||
// =============================================================================
|
||||
// FILE DETAILS
|
||||
// Project :
|
||||
// File : lscc_pll.v
|
||||
// Title :
|
||||
// Dependencies : 1. PLL_B primitive
|
||||
// Description : iCE40UP Phase-Locked Loop.
|
||||
// =============================================================================
|
||||
// REVISION HISTORY
|
||||
// Version : 1.0.0.
|
||||
// Author(s) :
|
||||
// Mod. Date : 04.20.2017
|
||||
// Changes Made : Initial release.
|
||||
// =============================================================================
|
||||
module system_pll_ipgen_lscc_pll #(parameter DIVR = "1",
|
||||
parameter DIVF = "1",
|
||||
parameter DIVQ = "1",
|
||||
parameter FEEDBACK_PATH = "SIMPLE",
|
||||
parameter FILTER_RANGE = "0",
|
||||
parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED",
|
||||
parameter FDA_FEEDBACK = "0",
|
||||
parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED",
|
||||
parameter FDA_RELATIVE = "0",
|
||||
parameter SHIFTREG_DIV_MODE = "0",
|
||||
parameter PLLOUT_SELECT_PORTA = "SHIFTREG_0deg",
|
||||
parameter PLLOUT_SELECT_PORTB = "SHIFTREG_0deg",
|
||||
parameter EXTERNAL_DIVIDE_FACTOR = "NONE",
|
||||
parameter ENABLE_ICEGATE_PORTA = "0",
|
||||
parameter ENABLE_ICEGATE_PORTB = "0",
|
||||
parameter FREQUENCY_PIN_REFERENCECLK = "10.0") (
|
||||
// -----------------------------------------------------------------------------
|
||||
// Module Parameters
|
||||
// -----------------------------------------------------------------------------
|
||||
// -----------------------------------------------------------------------------
|
||||
// Input/Output Ports
|
||||
// -----------------------------------------------------------------------------
|
||||
input ref_clk_i,
|
||||
input rst_n_i,
|
||||
input feedback_i,
|
||||
input [7:0] dynamic_delay_i,
|
||||
input bypass_i,
|
||||
input latch_i,
|
||||
output wire lock_o,
|
||||
output wire outcore_o,
|
||||
output wire outglobal_o,
|
||||
output wire outcoreb_o,
|
||||
output wire outglobalb_o,
|
||||
input sclk_i,
|
||||
input sdi_i,
|
||||
output wire sdo_o) ;
|
||||
// -----------------------------------------------------------------------------
|
||||
// Wire Declarations
|
||||
// -----------------------------------------------------------------------------
|
||||
wire [7:0] dynamic_delay_w ;
|
||||
wire feedback_w ;
|
||||
wire intfbout_w ;
|
||||
// -----------------------------------------------------------------------------
|
||||
// Generate Assign Statements
|
||||
// -----------------------------------------------------------------------------
|
||||
generate
|
||||
if ((EXTERNAL_DIVIDE_FACTOR != "NONE"))
|
||||
begin : genblk1
|
||||
assign feedback_w = feedback_i ;
|
||||
end
|
||||
else
|
||||
begin : genblk1
|
||||
assign feedback_w = intfbout_w ;
|
||||
end
|
||||
endgenerate
|
||||
generate
|
||||
if ((DELAY_ADJUSTMENT_MODE_FEEDBACK == "FIXED"))
|
||||
begin : genblk2
|
||||
assign dynamic_delay_w[3:0] = 4'b0 ;
|
||||
end
|
||||
else
|
||||
begin : genblk2
|
||||
assign dynamic_delay_w[3:0] = dynamic_delay_i[3:0] ;
|
||||
end
|
||||
if ((DELAY_ADJUSTMENT_MODE_RELATIVE == "FIXED"))
|
||||
begin : genblk3
|
||||
assign dynamic_delay_w[7:4] = 4'b0 ;
|
||||
end
|
||||
else
|
||||
begin : genblk3
|
||||
assign dynamic_delay_w[7:4] = dynamic_delay_i[7:4] ;
|
||||
end
|
||||
endgenerate
|
||||
// -----------------------------------------------------------------------------
|
||||
// PLL Primitive Instantiation
|
||||
// -----------------------------------------------------------------------------
|
||||
PLL_B #(.DIVR(DIVR),
|
||||
.DIVF(DIVF),
|
||||
.DIVQ(DIVQ),
|
||||
.FEEDBACK_PATH(FEEDBACK_PATH),
|
||||
.FILTER_RANGE(FILTER_RANGE),
|
||||
.DELAY_ADJUSTMENT_MODE_FEEDBACK(DELAY_ADJUSTMENT_MODE_FEEDBACK),
|
||||
.FDA_FEEDBACK(FDA_FEEDBACK),
|
||||
.DELAY_ADJUSTMENT_MODE_RELATIVE(DELAY_ADJUSTMENT_MODE_RELATIVE),
|
||||
.FDA_RELATIVE(FDA_RELATIVE),
|
||||
.SHIFTREG_DIV_MODE(SHIFTREG_DIV_MODE),
|
||||
.PLLOUT_SELECT_PORTA(PLLOUT_SELECT_PORTA),
|
||||
.PLLOUT_SELECT_PORTB(PLLOUT_SELECT_PORTB),
|
||||
.EXTERNAL_DIVIDE_FACTOR(EXTERNAL_DIVIDE_FACTOR),
|
||||
.ENABLE_ICEGATE_PORTA(ENABLE_ICEGATE_PORTA),
|
||||
.ENABLE_ICEGATE_PORTB(ENABLE_ICEGATE_PORTB),
|
||||
.FREQUENCY_PIN_REFERENCECLK(FREQUENCY_PIN_REFERENCECLK)) u_PLL_B (.REFERENCECLK(ref_clk_i),
|
||||
.RESET_N(rst_n_i),
|
||||
.FEEDBACK(feedback_w),
|
||||
.DYNAMICDELAY7(dynamic_delay_w[7]),
|
||||
.DYNAMICDELAY6(dynamic_delay_w[6]),
|
||||
.DYNAMICDELAY5(dynamic_delay_w[5]),
|
||||
.DYNAMICDELAY4(dynamic_delay_w[4]),
|
||||
.DYNAMICDELAY3(dynamic_delay_w[3]),
|
||||
.DYNAMICDELAY2(dynamic_delay_w[2]),
|
||||
.DYNAMICDELAY1(dynamic_delay_w[1]),
|
||||
.DYNAMICDELAY0(dynamic_delay_w[0]),
|
||||
.INTFBOUT(intfbout_w),
|
||||
.BYPASS(bypass_i),
|
||||
.LATCH(latch_i),
|
||||
.OUTCORE(outcore_o),
|
||||
.OUTGLOBAL(outglobal_o),
|
||||
.OUTCOREB(outcoreb_o),
|
||||
.OUTGLOBALB(outglobalb_o),
|
||||
.LOCK(lock_o),
|
||||
.SCLK(sclk_i),
|
||||
.SDI(sdi_i),
|
||||
.SDO(sdo_o)) ;
|
||||
endmodule
|
||||
|
||||
|
||||
@ -0,0 +1,12 @@
|
||||
<?xml version="1.0" ?>
|
||||
<RadiantModule architecture="iCE40UP" date="2021 05 12 22:58:47" device="iCE40UP5K" generator="ipgen" library="module" module="pll" name="system_pll" package="SG48" source_format="Verilog" speed="High-Performance_1.2V" vendor="latticesemi.com" version="1.0.1">
|
||||
<Package>
|
||||
<File modified="2021 05 12 22:58:47" name="rtl/system_pll_bb.v" type="black_box_verilog"/>
|
||||
<File modified="2021 05 12 22:58:47" name="system_pll.cfg" type="cfg"/>
|
||||
<File modified="2021 05 12 22:58:47" name="misc/system_pll_tmpl.v" type="template_verilog"/>
|
||||
<File modified="2021 05 12 22:58:47" name="misc/system_pll_tmpl.vhd" type="template_vhdl"/>
|
||||
<File modified="2021 05 12 22:58:47" name="rtl/system_pll.v" type="top_level_verilog"/>
|
||||
<File modified="2021 05 12 22:58:47" name="component.xml" type="IP-XACT_component"/>
|
||||
<File modified="2021 05 12 22:58:47" name="design.xml" type="IP-XACT_design"/>
|
||||
</Package>
|
||||
</RadiantModule>
|
||||
32
Libs/RiscV/NEORV32/setups/vivado/README.md
Normal file
32
Libs/RiscV/NEORV32/setups/vivado/README.md
Normal file
@ -0,0 +1,32 @@
|
||||
# NEORV32 Xilinx Vivado Example Setups
|
||||
|
||||
## How To Run
|
||||
|
||||
The `create_project.tcl` TCL script in the board subdirectories can be used for creating a complete Vivado project and for running the implementation.
|
||||
If not already available, this script will create a `work` folder in those subdirectories.
|
||||
|
||||
Note that you may need to install support for your particular development board through "XHub Stores" menu item within Vivado prior to sourcing the `create_project.tcl` script.
|
||||
|
||||
### Batch mode
|
||||
|
||||
Execute `vivado -mode batch -nojournal -nolog -source create_project.tcl` from the board subdir.
|
||||
The project will be created and implementation will be run until generation of `work/neorv32_test_setup.runs/impl_1/neorv32_test_setup.bit`.
|
||||
|
||||
### GUI
|
||||
|
||||
1. start Vivado (in GUI mode)
|
||||
2. click on "TCL Console" at the bottom
|
||||
3. use the console to naviagte to the boards folder. For example: `cd .../neorv32/setups/vivado/arty-a7-test-setup`
|
||||
4. execute `source create_project.tcl` - this will create the actual Vivado project in `work`
|
||||
5. when the Vivado project has openend, Implementation will run and a bitstream will be generated.
|
||||
6. maybe a prompt will notify about it.
|
||||
|
||||
### Programming the Bitstream
|
||||
|
||||
1. open the "Hardware Manager" (maybe a prompt will ask for that)
|
||||
2. click on "Open target/Auto Connect"
|
||||
3. click on "Program device" and select `work/neorv32_test_setup.runs/impl_1/neorv32_test_setup.bit`; click "Program"
|
||||
4. use a serial terminal (like :earth_asia: [Tera Term](https://ttssh2.osdn.jp/index.html.en)) to connect to the USB-UART interface using the following configuration:
|
||||
19200 Baud, 8 data bits, 1 stop bit, no parity bits, no transmission / flow control protocol (raw bytes only), newline on `\r\n` (carriage return & newline)
|
||||
5. now you can communicate with the bootloader console and upload a new program. Check out the [example programs](https://github.com/stnolting/neorv32/tree/master/sw/example)
|
||||
and see section "Let's Get It Started" of the :page_facing_up: [NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) for further resources.
|
||||
3
Libs/RiscV/NEORV32/setups/vivado/arty-a7-test-setup/.gitignore
vendored
Normal file
3
Libs/RiscV/NEORV32/setups/vivado/arty-a7-test-setup/.gitignore
vendored
Normal file
@ -0,0 +1,3 @@
|
||||
/vivado*
|
||||
/.Xil
|
||||
/work/*
|
||||
@ -0,0 +1,29 @@
|
||||
# NEORV32 Test Setup for the Digilent Arty A7-35 FPGA Board
|
||||
|
||||
This setup provides a very simple script-based "demo setup" that allows to check out the NEORV32 processor on the Digilent Arty A7-35 board.
|
||||
It uses the simplified [`neorv32_test_setup_bootloader.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) top entity, which is a wrapper for the actual processor
|
||||
top entity that provides a minimalistic interface (clock, reset, UART and 4 LEDs).
|
||||
|
||||
* FPGA Board: :books: [Digilent Arty A7-35 FPGA Board](https://reference.digilentinc.com/reference/programmable-logic/arty-a7/reference-manual)
|
||||
* FPGA: Xilinx Artix-7 `XC7A35TICSG324-1L`
|
||||
* Toolchain: Xilinx Vivado (tested with Vivado 2019.2)
|
||||
|
||||
|
||||
## NEORV32 Configuration
|
||||
|
||||
:information_source: See the top entity [`rtl/test_setups/neorv32_test_setup_bootloader.vhd` ](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) for
|
||||
configuration and entity details and [`arty_a7_35_test_setup.xdc`](https://github.com/stnolting/neorv32/blob/master/boards/arty-a7-35-test-setup/arty_a7_35_test_setup.xdc)
|
||||
for the according FPGA pin mapping.
|
||||
|
||||
* CPU: `rv32imcu_Zicsr` + 4 `HPM` (hardware performance monitors)
|
||||
* Memory: 16kB instruction memory (internal IMEM), 8kB data memory (internal DMEM), bootloader ROM
|
||||
* Peripherals: `GPIO`, `MTIME`, `UART0`, `WDT`
|
||||
* Tested with version [`1.5.3.3`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md)
|
||||
* Clock: 100MHz from on-board oscillator
|
||||
* Reset: Via dedicated on-board "RESET" button
|
||||
* GPIO output port `gpio_o`
|
||||
* bits 0..3 are connected to the green on-board LEDs (LD4 - LD7); LD4 is the bootloader status LED
|
||||
* bits 4..7 are (not actually used) connected to PMOD `JA` connector pins 1-4
|
||||
* UART0 signals `uart0_txd_o` and `uart0_rxd_i` are connected to the on-board USB-UART chip
|
||||
|
||||
|
||||
@ -0,0 +1,26 @@
|
||||
## This file is a general .xdc for the Arty A7-35 Rev. D
|
||||
|
||||
## For default neorv32_test_setup.vhd top entity
|
||||
|
||||
## Clock signal
|
||||
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk_i }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100]
|
||||
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { clk_i }];
|
||||
|
||||
## LEDs
|
||||
set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[0] }]; #IO_L24N_T3_35 Sch=led[4]
|
||||
set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[1] }]; #IO_25_35 Sch=led[5]
|
||||
set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[2] }]; #IO_L24P_T3_A01_D17_14 Sch=led[6]
|
||||
set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[3] }]; #IO_L24N_T3_A00_D16_14 Sch=led[7]
|
||||
|
||||
## Pmod Header JA (unused GPIO outputs)
|
||||
set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[4] }]; #IO_0_15 Sch=ja[1]
|
||||
set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[5] }]; #IO_L4P_T0_15 Sch=ja[2]
|
||||
set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[6] }]; #IO_L4N_T0_15 Sch=ja[3]
|
||||
set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[7] }]; #IO_L6P_T0_15 Sch=ja[4]
|
||||
|
||||
## USB-UART Interface
|
||||
set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { uart0_txd_o }]; #IO_L19N_T3_VREF_16 Sch=uart_rxd_out
|
||||
set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { uart0_rxd_i }]; #IO_L14N_T2_SRCC_16 Sch=uart_txd_in
|
||||
|
||||
## Misc.
|
||||
set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { rstn_i }]; #IO_L16P_T2_35 Sch=ck_rst
|
||||
@ -0,0 +1,57 @@
|
||||
set board "arty-a7-35"
|
||||
|
||||
# Create and clear output directory
|
||||
set outputdir work
|
||||
file mkdir $outputdir
|
||||
|
||||
set files [glob -nocomplain "$outputdir/*"]
|
||||
if {[llength $files] != 0} {
|
||||
puts "deleting contents of $outputdir"
|
||||
file delete -force {*}[glob -directory $outputdir *]; # clear folder contents
|
||||
} else {
|
||||
puts "$outputdir is empty"
|
||||
}
|
||||
|
||||
switch $board {
|
||||
"arty-a7-35" {
|
||||
set a7part "xc7a35ticsg324-1L"
|
||||
set a7prj ${board}-test-setup
|
||||
}
|
||||
}
|
||||
|
||||
# Create project
|
||||
create_project -part $a7part $a7prj $outputdir
|
||||
|
||||
set_property board_part digilentinc.com:${board}:part0:1.0 [current_project]
|
||||
set_property target_language VHDL [current_project]
|
||||
|
||||
# Define filesets
|
||||
|
||||
## Core: NEORV32
|
||||
add_files [glob ./../../../rtl/core/*.vhd] ./../../../rtl/core/mem/neorv32_dmem.default.vhd ./../../../rtl/core/mem/neorv32_imem.default.vhd
|
||||
set_property library neorv32 [get_files [glob ./../../../rtl/core/*.vhd]]
|
||||
set_property library neorv32 [get_files [glob ./../../../rtl/core/mem/neorv32_*mem.default.vhd]]
|
||||
|
||||
## Design: processor subsystem template, and (optionally) BoardTop and/or other additional sources
|
||||
set fileset_design ./../../../rtl/test_setups/neorv32_test_setup_bootloader.vhd
|
||||
|
||||
## Constraints
|
||||
set fileset_constraints [glob ./*.xdc]
|
||||
|
||||
## Simulation-only sources
|
||||
set fileset_sim [list ./../../../sim/simple/neorv32_tb.simple.vhd ./../../../sim/simple/uart_rx.simple.vhd]
|
||||
|
||||
# Add source files
|
||||
|
||||
## Design
|
||||
add_files $fileset_design
|
||||
|
||||
## Constraints
|
||||
add_files -fileset constrs_1 $fileset_constraints
|
||||
|
||||
## Simulation-only
|
||||
add_files -fileset sim_1 $fileset_sim
|
||||
|
||||
# Run synthesis, implementation and bitstream generation
|
||||
launch_runs impl_1 -to_step write_bitstream -jobs 4
|
||||
wait_on_run impl_1
|
||||
3
Libs/RiscV/NEORV32/setups/vivado/nexys-a7-test-setup/.gitignore
vendored
Normal file
3
Libs/RiscV/NEORV32/setups/vivado/nexys-a7-test-setup/.gitignore
vendored
Normal file
@ -0,0 +1,3 @@
|
||||
/vivado*
|
||||
/.Xil
|
||||
/work/*
|
||||
@ -0,0 +1,29 @@
|
||||
# NEORV32 Test Setup for the Digilent Nexys A7 and Nexys 4 DDR FPGA Boards
|
||||
|
||||
This setup provides a very simple script-based "demo setup" that allows to check out the NEORV32 processor on the Digilent Nexys A7 and Nexys 4 DDR boards.
|
||||
It uses the simplified [`neorv32_test_setup_bootloader.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) top entity, which is a wrapper for the actual processor
|
||||
top entity that provides a minimalistic interface (clock, reset, UART and 4 LEDs).
|
||||
|
||||
* FPGA Boards:
|
||||
* :books: [Digilent Nexys A7 FPGA Boards](https://reference.digilentinc.com/reference/programmable-logic/nexys-a7/reference-manual)
|
||||
* :books: [Digilent Nexys 4 DDR FPGA Board](https://reference.digilentinc.com/reference/programmable-logic/nexys-4-ddr/reference-manual)
|
||||
* FPGAs:
|
||||
* Xilinx Artix-7 `XC7A50TCSG324-1`
|
||||
* Xilinx Artix-7 `XC7A100TCSG324-1`
|
||||
* Toolchain: Xilinx Vivado (tested with Vivado 2020.2)
|
||||
|
||||
|
||||
## NEORV32 Configuration
|
||||
|
||||
:information_source: See the top entity [`rtl/test_setups/neorv32_test_setup_bootloader.vhd` ](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) for
|
||||
configuration and entity details and [`nexys_a7_test_setup.xdc`](https://github.com/AWenzel83/neorv32/blob/nexys_a7_example/boards/nexys-a7-test-setup/nexys_a7_test_setup.xdc)
|
||||
for the according FPGA pin mapping.
|
||||
|
||||
* CPU: `rv32imcu_Zicsr` + 4 `HPM` (hardware performance monitors)
|
||||
* Memory: 16kB instruction memory (internal IMEM), 8kB data memory (internal DMEM), bootloader ROM
|
||||
* Peripherals: `GPIO`, `MTIME`, `UART0`, `WDT`
|
||||
* Tested with version [`1.5.3.3`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md)
|
||||
* Clock: 100MHz from on-board oscillator
|
||||
* Reset: Via dedicated on-board "RESET" button
|
||||
* GPIO output port `gpio_o` bits 0..7 are connected to the green on-board LEDs (LD0 - LD7); LD0 is the bootloader status LED
|
||||
* UART0 signals `uart0_txd_o` and `uart0_rxd_i` are connected to the on-board USB-UART chip
|
||||
@ -0,0 +1,45 @@
|
||||
set board "A7-50"
|
||||
|
||||
# create and clear output directory
|
||||
set outputdir work
|
||||
file mkdir $outputdir
|
||||
|
||||
set files [glob -nocomplain "$outputdir/*"]
|
||||
if {[llength $files] != 0} {
|
||||
puts "deleting contents of $outputdir"
|
||||
file delete -force {*}[glob -directory $outputdir *]; # clear folder contents
|
||||
} else {
|
||||
puts "$outputdir is empty"
|
||||
}
|
||||
|
||||
switch $board {
|
||||
"A7-50" {
|
||||
set a7part "xc7a50tcsg324-1"
|
||||
set a7prj "nexys-a7-50-test-setup"
|
||||
}
|
||||
"A7-100" {
|
||||
set a7part "xc7a100tcsg324-1"
|
||||
set a7prj "nexys-a7-100-test-setup"
|
||||
}
|
||||
}
|
||||
|
||||
# create project
|
||||
create_project -part $a7part $a7prj $outputdir
|
||||
|
||||
# add source files: core sources
|
||||
add_files [glob ./../../../rtl/core/*.vhd] ./../../../rtl/core/mem/neorv32_dmem.default.vhd ./../../../rtl/core/mem/neorv32_imem.default.vhd
|
||||
set_property library neorv32 [get_files [glob ./../../../rtl/core/*.vhd]]
|
||||
set_property library neorv32 [get_files [glob ./../../../rtl/core/mem/neorv32_*mem.default.vhd]]
|
||||
|
||||
# add source file: top entity
|
||||
add_files [glob ./../../../rtl/test_setups/neorv32_test_setup_bootloader.vhd]
|
||||
|
||||
# add source files: simulation-only
|
||||
add_files -fileset sim_1 [list ./../../../sim/simple/neorv32_tb.simple.vhd ./../../../sim/simple/uart_rx.simple.vhd]
|
||||
|
||||
# add source files: constraints
|
||||
add_files -fileset constrs_1 [glob ./*.xdc]
|
||||
|
||||
# run synthesis, implementation and bitstream generation
|
||||
launch_runs impl_1 -to_step write_bitstream -jobs 4
|
||||
wait_on_run impl_1
|
||||
@ -0,0 +1,23 @@
|
||||
## This file is a general .xdc for the Nexys A7 and Nexys 4 DDR
|
||||
## For default neorv32_test_setup.vhd top entity
|
||||
|
||||
## Clock signal
|
||||
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk_i }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100]
|
||||
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { clk_i }];
|
||||
|
||||
## LEDs
|
||||
set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[0] }]; #IO_L18P_T2_A24_15 Sch=led[0]
|
||||
set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1]
|
||||
set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[2] }]; #IO_L17N_T2_A25_15 Sch=led[2]
|
||||
set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[3] }]; #IO_L8P_T1_D11_14 Sch=led[3]
|
||||
set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[4] }]; #IO_L7P_T1_D09_14 Sch=led[4]
|
||||
set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5]
|
||||
set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6]
|
||||
set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7]
|
||||
|
||||
## USB-UART Interface
|
||||
set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart0_txd_o }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out
|
||||
set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart0_rxd_i }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in
|
||||
|
||||
## Misc.
|
||||
set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { rstn_i }]; #IO_L3P_T0_DQS_AD1P_15 Sch=ck_rst
|
||||
Reference in New Issue
Block a user