Klagarge/SEm-Labos
Archived
1
0
Fork 0
Code Activity

Initial commit

Browse Source
This commit is contained in:
github-classroom[bot]
2024-02-23 13:01:05 +00:00
committed by GitHub
commit d212040c30
1914 changed files with 1290006 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

128
Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_AlhambraII_BoardTop_MinimalBoot.vhd Normal file
View File

@ -0,0 +1,128 @@
-- #################################################################################################
-- # << NEORV32 - Example setup including the bootloader, for the AlhambraII (c) Board >> #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library iCE40;
use iCE40.components.all; -- for device primitives and macros
entity neorv32_AlhambraII_BoardTop_MinimalBoot is
port (
-- external clock (12 MHz)
AlhambraII_CLK : in std_logic;
-- LED outputs
AlhambraII_LED0 : out std_logic;
AlhambraII_LED1 : out std_logic;
AlhambraII_LED2 : out std_logic;
AlhambraII_LED3 : out std_logic;
AlhambraII_LED4 : out std_logic;
AlhambraII_LED5 : out std_logic;
AlhambraII_LED6 : out std_logic;
AlhambraII_LED7 : out std_logic;
-- UART0
AlhambraII_RX : in std_logic;
AlhambraII_TX : out std_logic
);
end entity;
architecture neorv32_AlhambraII_BoardTop_MinimalBoot_rtl of neorv32_AlhambraII_BoardTop_MinimalBoot is
-- configuration --
constant f_clock_c : natural := 12000000; -- clock frequency in Hz
-- reset generator --
signal rst_cnt : std_logic_vector(8 downto 0) := (others => '0'); -- initialized by bitstream
signal sys_rstn : std_logic;
-- internal IO connection --
signal con_gpio_o : std_ulogic_vector(3 downto 0);
signal con_pwm : std_logic_vector(2 downto 0);
begin
-- Reset Generator ------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
reset_generator: process(AlhambraII_CLK)
begin
if rising_edge(AlhambraII_CLK) then
if (rst_cnt(rst_cnt'left) = '0') then
rst_cnt <= std_logic_vector(unsigned(rst_cnt) + 1);
end if;
end if;
end process reset_generator;
sys_rstn <= rst_cnt(rst_cnt'left);
-- The core of the problem ----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot
generic map (
CLOCK_FREQUENCY => f_clock_c, -- clock frequency of clk_i in Hz
MEM_INT_IMEM_SIZE => 4*1024, -- size of processor-internal instruction memory in bytes
MEM_INT_DMEM_SIZE => 2*1024 -- size of processor-internal data memory in bytes
)
port map (
-- Global control --
clk_i => std_ulogic(AlhambraII_CLK),
rstn_i => std_ulogic(sys_rstn),
-- GPIO --
gpio_o => con_gpio_o,
-- primary UART --
uart_txd_o => AlhambraII_TX, -- UART0 send data
uart_rxd_i => AlhambraII_RX, -- UART0 receive data
uart_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
uart_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional
-- PWM (to on-board RGB LED) --
pwm_o => con_pwm
);
-- IO Connection --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
AlhambraII_LED0 <= con_gpio_o(0);
AlhambraII_LED1 <= con_gpio_o(1);
AlhambraII_LED2 <= con_gpio_o(2);
AlhambraII_LED3 <= con_gpio_o(3);
AlhambraII_LED4 <= '0'; -- unused
AlhambraII_LED5 <= con_pwm(0);
AlhambraII_LED6 <= con_pwm(1);
AlhambraII_LED7 <= con_pwm(2);
end architecture;

149
Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_Fomu_BoardTop_Minimal.vhd Normal file
View File

@ -0,0 +1,149 @@
-- #################################################################################################
-- # << NEORV32 - Example minimal setup for the Fomu (c) Board >> #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library iCE40;
use iCE40.components.all; -- for device primitives and macros
entity neorv32_Fomu_BoardTop_Minimal is
port (
-- 48MHz Clock input
clki : in std_logic;
-- LED outputs
rgb : out std_logic_vector(2 downto 0);
-- USB Pins (which should be statically driven if not being used)
usb_dp : out std_logic;
usb_dn : out std_logic;
usb_dp_pu : out std_logic
);
end entity;
architecture neorv32_Fomu_BoardTop_Minimal_rtl of neorv32_Fomu_BoardTop_Minimal is
-- configuration --
constant f_clock_c : natural := 22000000; -- PLL output clock frequency in Hz
-- Globals
signal pll_rstn : std_logic;
signal pll_clk : std_logic;
-- internal IO connection --
signal con_pwm : std_logic_vector(2 downto 0);
begin
-- Assign USB pins to "0" so as to disconnect Fomu from
-- the host system. Otherwise it would try to talk to
-- us over USB, which wouldn't work since we have no stack.
usb_dp <= '0';
usb_dn <= '0';
usb_dp_pu <= '0';
-- System PLL -----------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- Settings generated by icepll -i 48 -o 21:
-- F_PLLIN: 48.000 MHz (given)
-- F_PLLOUT: 22.000 MHz (requested)
-- F_PLLOUT: 22.000 MHz (achieved)
-- FEEDBACK: SIMPLE
-- F_PFD: 16.000 MHz
-- F_VCO: 704.000 MHz
-- DIVR: 2 (4'b0010)
-- DIVF: 43 (7'b0101011)
-- DIVQ: 5 (3'b101)
-- FILTER_RANGE: 1 (3'b001)
Pll_inst : SB_PLL40_CORE
generic map (
FEEDBACK_PATH => "SIMPLE",
DIVR => x"2",
DIVF => 7x"2B",
DIVQ => 3x"5",
FILTER_RANGE => 3x"1"
)
port map (
REFERENCECLK => clki,
PLLOUTCORE => open,
PLLOUTGLOBAL => pll_clk,
EXTFEEDBACK => '0',
DYNAMICDELAY => x"00",
LOCK => pll_rstn,
BYPASS => '0',
RESETB => '1',
LATCHINPUTVALUE => '0',
SDO => open,
SDI => '0',
SCLK => '0'
);
-- The core of the problem ----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_inst: entity work.neorv32_ProcessorTop_Minimal
generic map (
CLOCK_FREQUENCY => f_clock_c -- clock frequency of clk_i in Hz
)
port map (
-- Global control --
clk_i => std_ulogic(pll_clk),
rstn_i => std_ulogic(pll_rstn),
-- PWM (to on-board RGB LED) --
pwm_o => con_pwm
);
-- IO Connection --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
RGB_inst: SB_RGBA_DRV
generic map (
CURRENT_MODE => "0b1",
RGB0_CURRENT => "0b000011",
RGB1_CURRENT => "0b000011",
RGB2_CURRENT => "0b000011"
)
port map (
CURREN => '1', -- I
RGBLEDEN => '1', -- I
RGB2PWM => con_pwm(2), -- I - blue - pwm channel 2
RGB1PWM => con_pwm(1), -- I - red - pwm channel 1 || BOOT blink
RGB0PWM => con_pwm(0), -- I - green - pwm channel 0
RGB2 => rgb(2), -- O - blue
RGB1 => rgb(1), -- O - red
RGB0 => rgb(0) -- O - green
);
end architecture;

174
Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_Fomu_BoardTop_MinimalBoot.vhd Normal file
View File

@ -0,0 +1,174 @@
-- #################################################################################################
-- # << NEORV32 - Example setup including the bootloader, for the Fomu (c) Board >> #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library iCE40;
use iCE40.components.all; -- for device primitives and macros
entity neorv32_Fomu_BoardTop_MinimalBoot is
port (
-- 48MHz Clock input
clki : in std_logic;
-- LED outputs
rgb : out std_logic_vector(2 downto 0);
-- USB Pins (which should be statically driven if not being used)
usb_dp : out std_logic;
usb_dn : out std_logic;
usb_dp_pu : out std_logic
);
end entity;
architecture neorv32_Fomu_BoardTop_MinimalBoot_rtl of neorv32_Fomu_BoardTop_MinimalBoot is
-- configuration --
constant f_clock_c : natural := 18000000; -- PLL output clock frequency in Hz
-- On-chip oscillator --
signal hf_osc_clk : std_logic;
-- Globals
signal pll_rstn : std_logic;
signal pll_clk : std_logic;
-- internal IO connection --
signal con_gpio_o : std_ulogic_vector(3 downto 0);
signal con_pwm : std_logic_vector(2 downto 0);
begin
-- Assign USB pins to "0" so as to disconnect Fomu from
-- the host system. Otherwise it would try to talk to
-- us over USB, which wouldn't work since we have no stack.
usb_dp <= '0';
usb_dn <= '0';
usb_dp_pu <= '0';
-- On-Chip HF Oscillator ------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
HSOSC_inst : SB_HFOSC
generic map (
CLKHF_DIV => "0b10" -- 12 MHz
)
port map (
CLKHFPU => '1',
CLKHFEN => '1',
CLKHF => hf_osc_clk
);
-- System PLL -----------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- Settings generated by icepll -i 12 -o 18:
-- F_PLLIN: 12.000 MHz (given)
-- F_PLLOUT: 18.000 MHz (requested)
-- F_PLLOUT: 18.000 MHz (achieved)
-- FEEDBACK: SIMPLE
-- F_PFD: 12.000 MHz
-- F_VCO: 576.000 MHz
-- DIVR: 0 (4'b0000)
-- DIVF: 47 (7'b0101111)
-- DIVQ: 5 (3'b101)
-- FILTER_RANGE: 1 (3'b001)
Pll_inst : SB_PLL40_CORE
generic map (
FEEDBACK_PATH => "SIMPLE",
DIVR => x"0",
DIVF => 7x"2F",
DIVQ => 3x"5",
FILTER_RANGE => 3x"1"
)
port map (
REFERENCECLK => hf_osc_clk,
PLLOUTCORE => open,
PLLOUTGLOBAL => pll_clk,
EXTFEEDBACK => '0',
DYNAMICDELAY => x"00",
LOCK => pll_rstn,
BYPASS => '0',
RESETB => '1',
LATCHINPUTVALUE => '0',
SDO => open,
SDI => '0',
SCLK => '0'
);
-- The core of the problem ----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot
generic map (
CLOCK_FREQUENCY => f_clock_c -- clock frequency of clk_i in Hz
)
port map (
-- Global control --
clk_i => std_ulogic(pll_clk),
rstn_i => std_ulogic(pll_rstn),
-- GPIO --
gpio_o => con_gpio_o,
-- primary UART --
uart_txd_o => open, -- UART0 send data
uart_rxd_i => '0', -- UART0 receive data
uart_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
uart_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional
-- PWM (to on-board RGB LED) --
pwm_o => con_pwm
);
-- IO Connection --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
RGB_inst: SB_RGBA_DRV
generic map (
CURRENT_MODE => "0b1",
RGB0_CURRENT => "0b000011",
RGB1_CURRENT => "0b000011",
RGB2_CURRENT => "0b000011"
)
port map (
CURREN => '1', -- I
RGBLEDEN => '1', -- I
RGB2PWM => con_pwm(2), -- I - blue - pwm channel 2
RGB1PWM => con_pwm(1) or con_gpio_o(0), -- I - red - pwm channel 1 || BOOT blink
RGB0PWM => con_pwm(0), -- I - green - pwm channel 0
RGB2 => rgb(2), -- O - blue
RGB1 => rgb(1), -- O - red
RGB0 => rgb(0) -- O - green
);
end architecture;

139
Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_Fomu_BoardTop_MixedLanguage.vhd Normal file
View File

@ -0,0 +1,139 @@
-- #################################################################################################
-- # << NEORV32 - Example setup including the bootloader, for the Fomu (c) Board >> #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library iCE40;
use iCE40.components.all; -- for device primitives and macros
entity neorv32_Fomu_BoardTop_MixedLanguage is
port (
-- 48MHz Clock input
clki : in std_logic;
-- LED outputs
rgb : out std_logic_vector(2 downto 0);
-- USB Pins (which should be statically driven if not being used)
usb_dp : out std_logic;
usb_dn : out std_logic;
usb_dp_pu : out std_logic
);
end entity;
architecture neorv32_Fomu_BoardTop_MixedLanguage_rtl of neorv32_Fomu_BoardTop_MixedLanguage is
-- configuration --
constant f_clock_c : natural := 18000000; -- PLL output clock frequency in Hz
component neorv32_Fomu_MixedLanguage_ClkGen
port (
clk_o : out std_logic;
rstn_o : out std_logic
);
end component;
-- Globals
signal pll_rstn : std_logic;
signal pll_clk : std_logic;
-- internal IO connection --
signal con_gpio_o : std_ulogic_vector(3 downto 0);
signal con_pwm : std_logic_vector(2 downto 0);
begin
-- Assign USB pins to "0" so as to disconnect Fomu from
-- the host system. Otherwise it would try to talk to
-- us over USB, which wouldn't work since we have no stack.
usb_dp <= '0';
usb_dn <= '0';
usb_dp_pu <= '0';
-- On-Chip HF Oscillator and System PLL -----------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
Clk_inst : neorv32_Fomu_MixedLanguage_ClkGen
port map (
clk_o => pll_clk,
rstn_o => pll_rstn
);
-- The core of the problem ----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot
generic map (
CLOCK_FREQUENCY => f_clock_c -- clock frequency of clk_i in Hz
)
port map (
-- Global control --
clk_i => std_ulogic(pll_clk),
rstn_i => std_ulogic(pll_rstn),
-- GPIO --
gpio_o => con_gpio_o,
-- primary UART --
uart_txd_o => open, -- UART0 send data
uart_rxd_i => '0', -- UART0 receive data
uart_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
uart_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional
-- PWM (to on-board RGB LED) --
pwm_o => con_pwm
);
-- IO Connection --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
RGB_inst: SB_RGBA_DRV
generic map (
CURRENT_MODE => "0b1",
RGB0_CURRENT => "0b000011",
RGB1_CURRENT => "0b000011",
RGB2_CURRENT => "0b000011"
)
port map (
CURREN => '1', -- I
RGBLEDEN => '1', -- I
RGB2PWM => con_pwm(2), -- I - blue - pwm channel 2
RGB1PWM => con_pwm(1) or con_gpio_o(0), -- I - red - pwm channel 1 || BOOT blink
RGB0PWM => con_pwm(0), -- I - green - pwm channel 0
RGB2 => rgb(2), -- O - blue
RGB1 => rgb(1), -- O - red
RGB0 => rgb(0) -- O - green
);
end architecture;

185
Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_Fomu_BoardTop_UP5KDemo.vhd Normal file
View File

@ -0,0 +1,185 @@
-- #################################################################################################
-- # << NEORV32 - Example setup for the Fomu (c) Board >> #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library iCE40;
use iCE40.components.all; -- for device primitives and macros
entity neorv32_Fomu_BoardTop_UP5KDemo is
port (
-- 48MHz Clock input
clki : in std_logic;
-- LED outputs
rgb : out std_logic_vector(2 downto 0);
-- USB Pins (which should be statically driven if not being used)
usb_dp : out std_logic;
usb_dn : out std_logic;
usb_dp_pu : out std_logic
);
end entity;
architecture neorv32_Fomu_BoardTop_UP5KDemo_rtl of neorv32_Fomu_BoardTop_UP5KDemo is
-- configuration --
constant f_clock_c : natural := 18000000; -- PLL output clock frequency in Hz
-- On-chip oscillator --
signal hf_osc_clk : std_logic;
-- Globals
signal pll_rstn : std_logic;
signal pll_clk : std_logic;
-- internal IO connection --
signal con_pwm : std_ulogic_vector(2 downto 0);
signal con_gpio_o : std_ulogic_vector(3 downto 0);
begin
-- Assign USB pins to "0" so as to disconnect Fomu from
-- the host system. Otherwise it would try to talk to
-- us over USB, which wouldn't work since we have no stack.
usb_dp <= '0';
usb_dn <= '0';
usb_dp_pu <= '0';
-- On-Chip HF Oscillator ------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
HSOSC_inst : SB_HFOSC
generic map (
CLKHF_DIV => "0b10" -- 12 MHz
)
port map (
CLKHFPU => '1',
CLKHFEN => '1',
CLKHF => hf_osc_clk
);
-- System PLL -----------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- Settings generated by icepll -i 12 -o 18:
-- F_PLLIN: 12.000 MHz (given)
-- F_PLLOUT: 18.000 MHz (requested)
-- F_PLLOUT: 18.000 MHz (achieved)
-- FEEDBACK: SIMPLE
-- F_PFD: 12.000 MHz
-- F_VCO: 576.000 MHz
-- DIVR: 0 (4'b0000)
-- DIVF: 47 (7'b0101111)
-- DIVQ: 5 (3'b101)
-- FILTER_RANGE: 1 (3'b001)
Pll_inst : SB_PLL40_CORE
generic map (
FEEDBACK_PATH => "SIMPLE",
DIVR => x"0",
DIVF => 7x"2F",
DIVQ => 3x"5",
FILTER_RANGE => 3x"1"
)
port map (
REFERENCECLK => hf_osc_clk,
PLLOUTCORE => open,
PLLOUTGLOBAL => pll_clk,
EXTFEEDBACK => '0',
DYNAMICDELAY => x"00",
LOCK => pll_rstn,
BYPASS => '0',
RESETB => '1',
LATCHINPUTVALUE => '0',
SDO => open,
SDI => '0',
SCLK => '0'
);
-- The core of the problem ----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_inst: entity work.neorv32_ProcessorTop_UP5KDemo
generic map (
CLOCK_FREQUENCY => f_clock_c -- clock frequency of clk_i in Hz
)
port map (
-- Global control --
clk_i => std_ulogic(pll_clk),
rstn_i => std_ulogic(pll_rstn),
-- primary UART --
uart_txd_o => open,
uart_rxd_i => '0',
uart_rts_o => open,
uart_cts_i => '0',
-- SPI to on-board flash --
flash_sck_o => open,
flash_sdo_o => open,
flash_sdi_i => '0',
flash_csn_o => open,
-- SPI to IO pins --
spi_sck_o => open,
spi_sdo_o => open,
spi_sdi_i => '0',
spi_csn_o => open,
-- TWI --
twi_sda_io => open,
twi_scl_io => open,
-- GPIO --
gpio_i => (others=>'0'),
gpio_o => con_gpio_o,
-- PWM (to on-board RGB LED) --
pwm_o => con_pwm
);
-- IO Connection --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
RGB_inst: SB_RGBA_DRV
generic map (
CURRENT_MODE => "0b1",
RGB0_CURRENT => "0b000011",
RGB1_CURRENT => "0b000011",
RGB2_CURRENT => "0b000011"
)
port map (
CURREN => '1', -- I
RGBLEDEN => '1', -- I
RGB2PWM => con_pwm(2), -- I - blue - pwm channel 2
RGB1PWM => con_pwm(1) or con_gpio_o(0), -- I - red - pwm channel 1 || BOOT blink
RGB0PWM => con_pwm(0), -- I - green - pwm channel 0
RGB2 => rgb(2), -- O - blue
RGB1 => rgb(1), -- O - red
RGB0 => rgb(0) -- O - green
);
end architecture;

130
Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_OrangeCrab_BoardTop_MinimalBoot.vhd Normal file
View File

@ -0,0 +1,130 @@
-- #################################################################################################
-- # << NEORV32 - Example setup including the bootloader, for the OrangeCrab (c) Board >> #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ECP5;
use ECP5.components.all; -- for device primitives and macros
entity neorv32_OrangeCrab_BoardTop_MinimalBoot is
port (
-- Clock and Reset inputs
OrangeCrab_CLK : in std_logic;
OrangeCrab_RST_N : in std_logic;
-- LED outputs
OrangeCrab_LED_RGB_R : out std_logic;
OrangeCrab_LED_RGB_G : out std_logic;
OrangeCrab_LED_RGB_B : out std_logic;
-- UART0
OrangeCrab_GPIO_0 : in std_logic;
OrangeCrab_GPIO_1 : out std_logic;
OrangeCrab_GPIO_9 : out std_logic;
-- USB Pins (which should be statically driven if not being used)
OrangeCrab_USB_D_P : out std_logic;
OrangeCrab_USB_D_N : out std_logic;
OrangeCrab_USB_DP_PU : out std_logic
);
end entity;
architecture neorv32_OrangeCrab_BoardTop_MinimalBoot_rtl of neorv32_OrangeCrab_BoardTop_MinimalBoot is
-- configuration --
constant f_clock_c : natural := 24000000; -- PLL output clock frequency in Hz
-- Globals
signal pll_clk: std_logic;
-- internal IO connection --
signal con_pwm : std_logic_vector(2 downto 0);
signal con_gpio_o : std_ulogic_vector(3 downto 0);
begin
-- Assign USB pins to "0" so as to disconnect OrangeCrab from
-- the host system. Otherwise it would try to talk to
-- us over USB, which wouldn't work since we have no stack.
OrangeCrab_USB_D_P <= '0';
OrangeCrab_USB_D_N <= '0';
OrangeCrab_USB_DP_PU <= '0';
-- System PLL -----------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
PLL_inst: EHXPLLL
generic map (
CLKI_DIV => 2, -- from `ecppll -i 48 -o 24`
CLKFB_DIV => 1,
CLKOP_DIV => 25
)
port map (
CLKI => OrangeCrab_CLK,
CLKFB => pll_clk,
ENCLKOP => '1',
CLKOP => pll_clk,
LOCK => OrangeCrab_GPIO_9
);
-- The core of the problem ----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot
generic map (
CLOCK_FREQUENCY => f_clock_c, -- clock frequency of clk_i in Hz
MEM_INT_IMEM_SIZE => 16*1024,
MEM_INT_DMEM_SIZE => 8*1024
)
port map (
-- Global control --
clk_i => std_ulogic(pll_clk),
rstn_i => std_ulogic(OrangeCrab_RST_N),
-- GPIO --
gpio_o => con_gpio_o,
-- primary UART --
uart_txd_o => OrangeCrab_GPIO_1, -- UART0 send data
uart_rxd_i => OrangeCrab_GPIO_0, -- UART0 receive data
uart_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
uart_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional
-- PWM (to on-board RGB LED) --
pwm_o => con_pwm
);
OrangeCrab_LED_RGB_R <= con_pwm(0) or not con_gpio_o(0);
OrangeCrab_LED_RGB_G <= con_pwm(1);
OrangeCrab_LED_RGB_B <= con_pwm(2);
end architecture;

110
Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_ULX3S_BoardTop_MinimalBoot.vhd Normal file
View File

@ -0,0 +1,110 @@
-- #################################################################################################
-- # << NEORV32 - Example setup including the bootloader, for the ULX3S (c) Board >> #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ECP5;
use ECP5.components.all; -- for device primitives and macros
entity neorv32_ULX3S_BoardTop_MinimalBoot is
port (
-- Clock and Reset inputs
ULX3S_CLK : in std_logic;
ULX3S_RST_N : in std_logic;
-- LED outputs
ULX3S_LED0 : out std_logic;
ULX3S_LED1 : out std_logic;
ULX3S_LED2 : out std_logic;
ULX3S_LED3 : out std_logic;
ULX3S_LED4 : out std_logic;
ULX3S_LED5 : out std_logic;
ULX3S_LED6 : out std_logic;
ULX3S_LED7 : out std_logic;
-- UART0
ULX3S_RX : in std_logic;
ULX3S_TX : out std_logic
);
end entity;
architecture neorv32_ULX3S_BoardTop_MinimalBoot_rtl of neorv32_ULX3S_BoardTop_MinimalBoot is
-- configuration --
constant f_clock_c : natural := 25000000; -- clock frequency in Hz
-- internal IO connection --
signal con_pwm : std_logic_vector(2 downto 0);
signal con_gpio_o : std_ulogic_vector(3 downto 0);
begin
-- The core of the problem ----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot
generic map (
CLOCK_FREQUENCY => f_clock_c, -- clock frequency of clk_i in Hz
MEM_INT_IMEM_SIZE => 16*1024,
MEM_INT_DMEM_SIZE => 8*1024
)
port map (
-- Global control --
clk_i => std_ulogic(ULX3S_CLK),
rstn_i => std_ulogic(ULX3S_RST_N),
-- GPIO --
gpio_o => con_gpio_o,
-- primary UART --
uart_txd_o => ULX3S_TX, -- UART0 send data
uart_rxd_i => ULX3S_RX, -- UART0 receive data
uart_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
uart_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional
-- PWM (to on-board RGB LED) --
pwm_o => con_pwm
);
-- IO Connection --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
ULX3S_LED0 <= con_gpio_o(0);
ULX3S_LED1 <= con_gpio_o(1);
ULX3S_LED2 <= con_gpio_o(2);
ULX3S_LED3 <= con_gpio_o(3);
ULX3S_LED4 <= '0'; -- unused
ULX3S_LED5 <= con_pwm(0);
ULX3S_LED6 <= con_pwm(1);
ULX3S_LED7 <= con_pwm(2);
end architecture;

163
Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_UPduino_BoardTop_MinimalBoot.vhd Normal file
View File

@ -0,0 +1,163 @@
-- #################################################################################################
-- # << NEORV32 - Example setup for the tinyVision.ai Inc. "UPduino v3" (c) Board >> #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library iCE40;
use iCE40.components.all; -- for device primitives and macros
entity neorv32_UPduino_BoardTop_MinimalBoot is
port (
-- UART (uart0) --
uart_txd_o : out std_ulogic;
uart_rxd_i : in std_ulogic;
-- GPIO --
gpio_o : out std_ulogic_vector(3 downto 0);
-- PWM (to on-board RGB power LED) --
pwm_o : out std_logic_vector(2 downto 0)
);
end entity;
architecture neorv32_UPduino_BoardTop_MinimalBoot_rtl of neorv32_UPduino_BoardTop_MinimalBoot is
-- configuration --
constant f_clock_c : natural := 18000000; -- PLL output clock frequency in Hz
-- On-chip oscillator --
signal hf_osc_clk : std_logic;
-- Globals
signal pll_rstn : std_logic;
signal pll_clk : std_logic;
-- internal IO connection --
signal con_pwm : std_logic_vector(2 downto 0);
begin
-- On-Chip HF Oscillator ------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
HSOSC_inst : SB_HFOSC
generic map (
CLKHF_DIV => "0b10" -- 12 MHz
)
port map (
CLKHFPU => '1',
CLKHFEN => '1',
CLKHF => hf_osc_clk
);
-- System PLL -----------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- Settings generated by icepll -i 12 -o 18:
-- F_PLLIN: 12.000 MHz (given)
-- F_PLLOUT: 18.000 MHz (requested)
-- F_PLLOUT: 18.000 MHz (achieved)
-- FEEDBACK: SIMPLE
-- F_PFD: 12.000 MHz
-- F_VCO: 576.000 MHz
-- DIVR: 0 (4'b0000)
-- DIVF: 47 (7'b0101111)
-- DIVQ: 5 (3'b101)
-- FILTER_RANGE: 1 (3'b001)
Pll_inst : SB_PLL40_CORE
generic map (
FEEDBACK_PATH => "SIMPLE",
DIVR => x"0",
DIVF => 7x"2F",
DIVQ => 3x"5",
FILTER_RANGE => 3x"1"
)
port map (
REFERENCECLK => hf_osc_clk,
PLLOUTCORE => open,
PLLOUTGLOBAL => pll_clk,
EXTFEEDBACK => '0',
DYNAMICDELAY => x"00",
LOCK => pll_rstn,
BYPASS => '0',
RESETB => '1',
LATCHINPUTVALUE => '0',
SDO => open,
SDI => '0',
SCLK => '0'
);
-- The core of the problem ----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot
generic map (
CLOCK_FREQUENCY => f_clock_c -- clock frequency of clk_i in Hz
)
port map (
-- Global control --
clk_i => std_ulogic(pll_clk),
rstn_i => std_ulogic(pll_rstn),
-- GPIO --
gpio_o => gpio_o,
-- primary UART --
uart_txd_o => uart_txd_o, -- UART0 send data
uart_rxd_i => uart_rxd_i, -- UART0 receive data
uart_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
uart_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional
-- PWM (to on-board RGB LED) --
pwm_o => con_pwm
);
-- IO Connection --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
RGB_inst: SB_RGBA_DRV
generic map (
CURRENT_MODE => "0b1",
RGB0_CURRENT => "0b000011",
RGB1_CURRENT => "0b000011",
RGB2_CURRENT => "0b000011"
)
port map (
CURREN => '1', -- I
RGBLEDEN => '1', -- I
RGB0PWM => con_pwm(1), -- I - green - pwm channel 1
RGB1PWM => con_pwm(2), -- I - blue - pwm channel 2
RGB2PWM => con_pwm(0), -- I - red - pwm channel 0
RGB2 => pwm_o(2), -- O - red
RGB1 => pwm_o(1), -- O - blue
RGB0 => pwm_o(0) -- O - green
);
end architecture;

204
Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_UPduino_BoardTop_UP5KDemo.vhd Normal file
View File

@ -0,0 +1,204 @@
-- #################################################################################################
-- # << NEORV32 - Example setup for the tinyVision.ai Inc. "UPduino v3" (c) Board >> #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library iCE40;
use iCE40.components.all; -- for device primitives and macros
entity neorv32_UPduino_BoardTop_UP5KDemo is
port (
-- UART (uart0) --
uart_txd_o : out std_ulogic;
uart_rxd_i : in std_ulogic;
-- SPI to on-board flash --
flash_sck_o : out std_ulogic;
flash_sdo_o : out std_ulogic;
flash_sdi_i : in std_ulogic;
flash_csn_o : out std_ulogic; -- NEORV32.SPI_CS(0)
-- SPI to IO pins --
spi_sck_o : out std_ulogic;
spi_sdo_o : out std_ulogic;
spi_sdi_i : in std_ulogic;
spi_csn_o : out std_ulogic; -- NEORV32.SPI_CS(1)
-- TWI --
twi_sda_io : inout std_logic;
twi_scl_io : inout std_logic;
-- GPIO --
gpio_i : in std_ulogic_vector(3 downto 0);
gpio_o : out std_ulogic_vector(3 downto 0);
-- PWM (to on-board RGB power LED) --
pwm_o : out std_ulogic_vector(2 downto 0)
);
end entity;
architecture neorv32_UPduino_BoardTop_UP5KDemo_rtl of neorv32_UPduino_BoardTop_UP5KDemo is
-- configuration --
constant f_clock_c : natural := 18000000; -- PLL output clock frequency in Hz
-- On-chip oscillator --
signal hf_osc_clk : std_logic;
-- Globals
signal pll_rstn : std_logic;
signal pll_clk : std_logic;
-- internal IO connection --
signal con_pwm : std_ulogic_vector(2 downto 0);
signal con_spi_sdi : std_ulogic;
signal con_spi_csn : std_ulogic;
begin
-- On-Chip HF Oscillator ------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
HSOSC_inst : SB_HFOSC
generic map (
CLKHF_DIV => "0b10" -- 12 MHz
)
port map (
CLKHFPU => '1',
CLKHFEN => '1',
CLKHF => hf_osc_clk
);
-- System PLL -----------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- Settings generated by icepll -i 12 -o 18:
-- F_PLLIN: 12.000 MHz (given)
-- F_PLLOUT: 18.000 MHz (requested)
-- F_PLLOUT: 18.000 MHz (achieved)
-- FEEDBACK: SIMPLE
-- F_PFD: 12.000 MHz
-- F_VCO: 576.000 MHz
-- DIVR: 0 (4'b0000)
-- DIVF: 47 (7'b0101111)
-- DIVQ: 5 (3'b101)
-- FILTER_RANGE: 1 (3'b001)
Pll_inst : SB_PLL40_CORE
generic map (
FEEDBACK_PATH => "SIMPLE",
DIVR => x"0",
DIVF => 7x"2F",
DIVQ => 3x"5",
FILTER_RANGE => 3x"1"
)
port map (
REFERENCECLK => hf_osc_clk,
PLLOUTCORE => open,
PLLOUTGLOBAL => pll_clk,
EXTFEEDBACK => '0',
DYNAMICDELAY => x"00",
LOCK => pll_rstn,
BYPASS => '0',
RESETB => '1',
LATCHINPUTVALUE => '0',
SDO => open,
SDI => '0',
SCLK => '0'
);
-- The core of the problem ----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_inst: entity work.neorv32_ProcessorTop_UP5KDemo
generic map (
CLOCK_FREQUENCY => f_clock_c -- clock frequency of clk_i in Hz
)
port map (
-- Global control --
clk_i => std_ulogic(pll_clk),
rstn_i => std_ulogic(pll_rstn),
-- primary UART --
uart_txd_o => uart_txd_o,
uart_rxd_i => uart_rxd_i,
uart_rts_o => open,
uart_cts_i => '0',
-- SPI to on-board flash --
flash_sck_o => flash_sck_o,
flash_sdo_o => flash_sdo_o,
flash_sdi_i => flash_sdi_i,
flash_csn_o => flash_csn_o,
-- SPI to IO pins --
spi_sck_o => spi_sck_o,
spi_sdo_o => spi_sdo_o,
spi_sdi_i => con_spi_sdi,
spi_csn_o => con_spi_csn,
-- TWI --
twi_sda_io => twi_sda_io,
twi_scl_io => twi_scl_io,
-- GPIO --
gpio_i => gpio_i,
gpio_o => gpio_o,
-- PWM (to on-board RGB power LED) --
pwm_o => con_pwm
);
-- IO Connection --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- SPI sdi read-back --
spi_csn_o <= con_spi_csn;
con_spi_sdi <= flash_sdi_i when (con_spi_csn = '0') else spi_sdi_i;
-- RGB --
RGB_inst: SB_RGBA_DRV
generic map (
CURRENT_MODE => "0b1",
RGB0_CURRENT => "0b000001",
RGB1_CURRENT => "0b000001",
RGB2_CURRENT => "0b000001"
)
port map (
CURREN => '1', -- I
RGBLEDEN => '1', -- I
RGB0PWM => con_pwm(1), -- I - green - pwm channel 1
RGB1PWM => con_pwm(2), -- I - bluee - pwm channel 2
RGB2PWM => con_pwm(0), -- I - red - pwm channel 0
RGB2 => pwm_o(2), -- O - red
RGB1 => pwm_o(1), -- O - blue
RGB0 => pwm_o(0) -- O - green
);
end architecture;

163
Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_iCEBreaker_BoardTop_MinimalBoot.vhd Normal file
View File

@ -0,0 +1,163 @@
-- #################################################################################################
-- # << NEORV32 - Example setup for the tinyVision.ai Inc. "UPduino v3" (c) Board >> #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library iCE40;
use iCE40.components.all; -- for device primitives and macros
entity neorv32_iCEBreaker_BoardTop_MinimalBoot is
port (
-- UART (uart0) --
uart_txd_o : out std_ulogic;
uart_rxd_i : in std_ulogic;
-- GPIO --
gpio_o : out std_ulogic_vector(3 downto 0);
-- PWM (to on-board RGB power LED) --
pwm_o : out std_logic_vector(2 downto 0)
);
end entity;
architecture neorv32_iCEBreaker_BoardTop_MinimalBoot_rtl of neorv32_iCEBreaker_BoardTop_MinimalBoot is
-- configuration --
constant f_clock_c : natural := 18000000; -- PLL output clock frequency in Hz
-- On-chip oscillator --
signal hf_osc_clk : std_logic;
-- Globals
signal pll_rstn : std_logic;
signal pll_clk : std_logic;
-- internal IO connection --
signal con_pwm : std_logic_vector(2 downto 0);
begin
-- On-Chip HF Oscillator ------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
HSOSC_inst : SB_HFOSC
generic map (
CLKHF_DIV => "0b10" -- 12 MHz
)
port map (
CLKHFPU => '1',
CLKHFEN => '1',
CLKHF => hf_osc_clk
);
-- System PLL -----------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- Settings generated by icepll -i 12 -o 18:
-- F_PLLIN: 12.000 MHz (given)
-- F_PLLOUT: 18.000 MHz (requested)
-- F_PLLOUT: 18.000 MHz (achieved)
-- FEEDBACK: SIMPLE
-- F_PFD: 12.000 MHz
-- F_VCO: 576.000 MHz
-- DIVR: 0 (4'b0000)
-- DIVF: 47 (7'b0101111)
-- DIVQ: 5 (3'b101)
-- FILTER_RANGE: 1 (3'b001)
Pll_inst : SB_PLL40_CORE
generic map (
FEEDBACK_PATH => "SIMPLE",
DIVR => x"0",
DIVF => 7x"2F",
DIVQ => 3x"5",
FILTER_RANGE => 3x"1"
)
port map (
REFERENCECLK => hf_osc_clk,
PLLOUTCORE => open,
PLLOUTGLOBAL => pll_clk,
EXTFEEDBACK => '0',
DYNAMICDELAY => x"00",
LOCK => pll_rstn,
BYPASS => '0',
RESETB => '1',
LATCHINPUTVALUE => '0',
SDO => open,
SDI => '0',
SCLK => '0'
);
-- The core of the problem ----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot
generic map (
CLOCK_FREQUENCY => f_clock_c -- clock frequency of clk_i in Hz
)
port map (
-- Global control --
clk_i => std_ulogic(pll_clk),
rstn_i => std_ulogic(pll_rstn),
-- GPIO --
gpio_o => gpio_o,
-- primary UART --
uart_txd_o => uart_txd_o, -- UART0 send data
uart_rxd_i => uart_rxd_i, -- UART0 receive data
uart_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
uart_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional
-- PWM (to on-board RGB LED) --
pwm_o => con_pwm
);
-- IO Connection --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
RGB_inst: SB_RGBA_DRV
generic map (
CURRENT_MODE => "0b1",
RGB0_CURRENT => "0b000011",
RGB1_CURRENT => "0b000011",
RGB2_CURRENT => "0b000011"
)
port map (
CURREN => '1', -- I
RGBLEDEN => '1', -- I
RGB0PWM => con_pwm(1), -- I - green - pwm channel 1
RGB1PWM => con_pwm(2), -- I - blue - pwm channel 2
RGB2PWM => con_pwm(0), -- I - red - pwm channel 0
RGB2 => pwm_o(2), -- O - red
RGB1 => pwm_o(1), -- O - blue
RGB0 => pwm_o(0) -- O - green
);
end architecture;

205
Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_iCEBreaker_BoardTop_UP5KDemo.vhd Normal file
View File

@ -0,0 +1,205 @@
-- #################################################################################################
-- # << NEORV32 - Example setup for the tinyVision.ai Inc. "UPduino v3" (c) Board >> #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library iCE40;
use iCE40.components.all; -- for device primitives and macros
entity neorv32_iCEBreaker_BoardTop_UP5KDemo is
port (
user_reset_btn : in std_ulogic;
-- UART (uart0) --
uart_txd_o : out std_ulogic;
uart_rxd_i : in std_ulogic;
-- SPI to on-board flash --
flash_sck_o : out std_ulogic;
flash_sdo_o : out std_ulogic;
flash_sdi_i : in std_ulogic;
flash_csn_o : out std_ulogic; -- NEORV32.SPI_CS(0)
-- SPI to IO pins --
spi_sck_o : out std_ulogic;
spi_sdo_o : out std_ulogic;
spi_sdi_i : in std_ulogic;
spi_csn_o : out std_ulogic; -- NEORV32.SPI_CS(1)
-- TWI --
twi_sda_io : inout std_logic;
twi_scl_io : inout std_logic;
-- GPIO --
gpio_i : in std_ulogic_vector(3 downto 0);
gpio_o : out std_ulogic_vector(3 downto 0);
-- PWM (to on-board RGB power LED) --
pwm_o : out std_ulogic_vector(2 downto 0)
);
end entity;
architecture neorv32_iCEBreaker_BoardTop_UP5KDemo_rtl of neorv32_iCEBreaker_BoardTop_UP5KDemo is
-- configuration --
constant f_clock_c : natural := 18000000; -- PLL output clock frequency in Hz
-- On-chip oscillator --
signal hf_osc_clk : std_logic;
-- Globals
signal pll_rstn : std_logic;
signal pll_clk : std_logic;
-- internal IO connection --
signal con_pwm : std_ulogic_vector(2 downto 0);
signal con_spi_sdi : std_ulogic;
signal con_spi_csn : std_ulogic;
begin
-- On-Chip HF Oscillator ------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
HSOSC_inst : SB_HFOSC
generic map (
CLKHF_DIV => "0b10" -- 12 MHz
)
port map (
CLKHFPU => '1',
CLKHFEN => '1',
CLKHF => hf_osc_clk
);
-- System PLL -----------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- Settings generated by icepll -i 12 -o 18:
-- F_PLLIN: 12.000 MHz (given)
-- F_PLLOUT: 18.000 MHz (requested)
-- F_PLLOUT: 18.000 MHz (achieved)
-- FEEDBACK: SIMPLE
-- F_PFD: 12.000 MHz
-- F_VCO: 576.000 MHz
-- DIVR: 0 (4'b0000)
-- DIVF: 47 (7'b0101111)
-- DIVQ: 5 (3'b101)
-- FILTER_RANGE: 1 (3'b001)
Pll_inst : SB_PLL40_CORE
generic map (
FEEDBACK_PATH => "SIMPLE",
DIVR => x"0",
DIVF => 7x"2F",
DIVQ => 3x"5",
FILTER_RANGE => 3x"1"
)
port map (
REFERENCECLK => hf_osc_clk,
PLLOUTCORE => open,
PLLOUTGLOBAL => pll_clk,
EXTFEEDBACK => '0',
DYNAMICDELAY => x"00",
LOCK => pll_rstn,
BYPASS => '0',
RESETB => user_reset_btn,
LATCHINPUTVALUE => '0',
SDO => open,
SDI => '0',
SCLK => '0'
);
-- The core of the problem ----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_inst: entity work.neorv32_ProcessorTop_UP5KDemo
generic map (
CLOCK_FREQUENCY => f_clock_c -- clock frequency of clk_i in Hz
)
port map (
-- Global control --
clk_i => std_ulogic(pll_clk),
rstn_i => std_ulogic(pll_rstn),
-- primary UART --
uart_txd_o => uart_txd_o,
uart_rxd_i => uart_rxd_i,
uart_rts_o => open,
uart_cts_i => '0',
-- SPI to on-board flash --
flash_sck_o => flash_sck_o,
flash_sdo_o => flash_sdo_o,
flash_sdi_i => flash_sdi_i,
flash_csn_o => flash_csn_o,
-- SPI to IO pins --
spi_sck_o => spi_sck_o,
spi_sdo_o => spi_sdo_o,
spi_sdi_i => con_spi_sdi,
spi_csn_o => con_spi_csn,
-- TWI --
twi_sda_io => twi_sda_io,
twi_scl_io => twi_scl_io,
-- GPIO --
gpio_i => gpio_i,
gpio_o => gpio_o,
-- PWM (to on-board RGB power LED) --
pwm_o => con_pwm
);
-- IO Connection --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- SPI sdi read-back --
spi_csn_o <= con_spi_csn;
con_spi_sdi <= flash_sdi_i when (con_spi_csn = '0') else spi_sdi_i;
-- RGB --
RGB_inst: SB_RGBA_DRV
generic map (
CURRENT_MODE => "0b1",
RGB0_CURRENT => "0b000001",
RGB1_CURRENT => "0b000001",
RGB2_CURRENT => "0b000001"
)
port map (
CURREN => '1', -- I
RGBLEDEN => '1', -- I
RGB0PWM => con_pwm(1), -- I - green - pwm channel 1
RGB1PWM => con_pwm(2), -- I - bluee - pwm channel 2
RGB2PWM => con_pwm(0), -- I - red - pwm channel 0
RGB2 => pwm_o(2), -- O - red
RGB1 => pwm_o(1), -- O - blue
RGB0 => pwm_o(0) -- O - green
);
end architecture;

172
Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_iCESugar_BoardTop_Minimal.vhd Normal file
View File

@ -0,0 +1,172 @@
-- #################################################################################################
-- # << NEORV32 - Example setup with an external clock, for the iCESugar (c) Board >> #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library iCE40;
use iCE40.components.all; -- for device primitives and macros
entity neorv32_iCESugar_BoardTop_Minimal is
port (
-- 48MHz Clock input
iCESugarv15_CLK : in std_logic;
-- UART0
iCESugarv15_RX : in std_logic;
iCESugarv15_TX : out std_logic;
-- LED outputs
iCESugarv15_LED_R : out std_logic;
iCESugarv15_LED_G : out std_logic;
iCESugarv15_LED_B : out std_logic;
-- USB Pins (which should be statically driven if not being used)
iCESugarv15_USB_DP : out std_logic;
iCESugarv15_USB_DN : out std_logic;
iCESugarv15_USB_DP_PU : out std_logic
);
end entity;
architecture neorv32_iCESugar_BoardTop_Minimal_rtl of neorv32_iCESugar_BoardTop_Minimal is
-- configuration --
constant f_clock_c : natural := 22000000; -- PLL output clock frequency in Hz
-- Globals
signal pll_rstn : std_logic;
signal pll_clk : std_logic;
-- internal IO connection --
signal con_gpio_o : std_ulogic_vector(3 downto 0);
signal con_pwm : std_logic_vector(2 downto 0);
begin
-- Assign USB pins to "0" so as to disconnect iCESugar from
-- the host system. Otherwise it would try to talk to
-- us over USB, which wouldn't work since we have no stack.
iCESugarv15_USB_DP <= '0';
iCESugarv15_USB_DN <= '0';
iCESugarv15_USB_DP_PU <= '0';
-- System PLL -----------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- Settings generated by icepll -i 12 -o 22:
-- F_PLLIN: 12.000 MHz (given)
-- F_PLLOUT: 22.000 MHz (requested)
-- F_PLLOUT: 22.000 MHz (achieved)
-- FEEDBACK: SIMPLE
-- F_PFD: 12.000 MHz
-- F_VCO: 708.000 MHz
-- DIVR: 0 (4'b0000)
-- DIVF: 58 (7'b0111010)
-- DIVQ: 5 (3'b101)
-- FILTER_RANGE: 1 (3'b001)
Pll_inst : SB_PLL40_PAD
generic map (
FEEDBACK_PATH => "SIMPLE",
DIVR => x"0",
DIVF => 7x"3A",
DIVQ => 3x"5",
FILTER_RANGE => 3x"1"
)
port map (
PACKAGEPIN => iCESugarv15_CLK,
PLLOUTCORE => open,
PLLOUTGLOBAL => pll_clk,
EXTFEEDBACK => '0',
DYNAMICDELAY => x"00",
LOCK => pll_rstn,
BYPASS => '0',
RESETB => '1',
LATCHINPUTVALUE => '0',
SDO => open,
SDI => '0',
SCLK => '0'
);
-- The core of the problem ----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot
generic map (
CLOCK_FREQUENCY => f_clock_c, -- clock frequency of clk_i in Hz
CPU_EXTENSION_RISCV_A => false,
CPU_EXTENSION_RISCV_C => false,
CPU_EXTENSION_RISCV_E => false,
CPU_EXTENSION_RISCV_M => false,
CPU_EXTENSION_RISCV_U => false,
CPU_EXTENSION_RISCV_Zfinx => false,
CPU_EXTENSION_RISCV_Zicsr => true,
CPU_EXTENSION_RISCV_Zifencei => false
)
port map (
-- Global control --
clk_i => std_ulogic(pll_clk),
rstn_i => std_ulogic(pll_rstn),
-- GPIO --
gpio_o => con_gpio_o,
-- primary UART --
uart_txd_o => iCESugarv15_TX, -- UART0 send data
uart_rxd_i => iCESugarv15_RX, -- UART0 receive data
uart_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
uart_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional
-- PWM (to on-board RGB LED) --
pwm_o => con_pwm
);
-- IO Connection --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
RGB_inst: SB_RGBA_DRV
generic map (
CURRENT_MODE => "0b1",
RGB0_CURRENT => "0b000011",
RGB1_CURRENT => "0b000011",
RGB2_CURRENT => "0b000011"
)
port map (
CURREN => '1', -- I
RGBLEDEN => '1', -- I
RGB2PWM => con_pwm(2), -- I - blue - pwm channel 2
RGB1PWM => con_pwm(1) or con_gpio_o(0), -- I - red - pwm channel 1 || BOOT blink
RGB0PWM => con_pwm(0), -- I - green - pwm channel 0
RGB2 => iCESugarv15_LED_B, -- O - blue
RGB1 => iCESugarv15_LED_R, -- O - red
RGB0 => iCESugarv15_LED_G -- O - green
);
end architecture;

177
Libs/RiscV/NEORV32/setups/osflow/board_tops/neorv32_iCESugar_BoardTop_MinimalBoot.vhd Normal file
View File

@ -0,0 +1,177 @@
-- #################################################################################################
-- # << NEORV32 - Example setup including the bootloader, for the iCESugar (c) Board >> #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library iCE40;
use iCE40.components.all; -- for device primitives and macros
entity neorv32_iCESugar_BoardTop_MinimalBoot is
port (
-- LED outputs
iCESugarv15_LED_R : out std_logic;
iCESugarv15_LED_G : out std_logic;
iCESugarv15_LED_B : out std_logic;
-- UART0
iCESugarv15_RX : in std_logic;
iCESugarv15_TX : out std_logic;
-- USB Pins (which should be statically driven if not being used)
iCESugarv15_USB_DP : out std_logic;
iCESugarv15_USB_DN : out std_logic;
iCESugarv15_USB_DP_PU : out std_logic
);
end entity;
architecture neorv32_iCESugar_BoardTop_MinimalBoot_rtl of neorv32_iCESugar_BoardTop_MinimalBoot is
-- configuration --
constant f_clock_c : natural := 18000000; -- PLL output clock frequency in Hz
-- On-chip oscillator --
signal hf_osc_clk : std_logic;
-- Globals
signal pll_rstn : std_logic;
signal pll_clk : std_logic;
-- internal IO connection --
signal con_gpio_o : std_ulogic_vector(3 downto 0);
signal con_pwm : std_logic_vector(2 downto 0);
begin
-- Assign USB pins to "0" so as to disconnect iCESugar from
-- the host system. Otherwise it would try to talk to
-- us over USB, which wouldn't work since we have no stack.
iCESugarv15_USB_DP <= '0';
iCESugarv15_USB_DN <= '0';
iCESugarv15_USB_DP_PU <= '0';
-- On-Chip HF Oscillator ------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
HSOSC_inst : SB_HFOSC
generic map (
CLKHF_DIV => "0b10" -- 12 MHz
)
port map (
CLKHFPU => '1',
CLKHFEN => '1',
CLKHF => hf_osc_clk
);
-- System PLL -----------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
-- Settings generated by icepll -i 12 -o 18:
-- F_PLLIN: 12.000 MHz (given)
-- F_PLLOUT: 18.000 MHz (requested)
-- F_PLLOUT: 18.000 MHz (achieved)
-- FEEDBACK: SIMPLE
-- F_PFD: 12.000 MHz
-- F_VCO: 576.000 MHz
-- DIVR: 0 (4'b0000)
-- DIVF: 47 (7'b0101111)
-- DIVQ: 5 (3'b101)
-- FILTER_RANGE: 1 (3'b001)
Pll_inst : SB_PLL40_CORE
generic map (
FEEDBACK_PATH => "SIMPLE",
DIVR => x"0",
DIVF => 7x"2F",
DIVQ => 3x"5",
FILTER_RANGE => 3x"1"
)
port map (
REFERENCECLK => hf_osc_clk,
PLLOUTCORE => open,
PLLOUTGLOBAL => pll_clk,
EXTFEEDBACK => '0',
DYNAMICDELAY => x"00",
LOCK => pll_rstn,
BYPASS => '0',
RESETB => '1',
LATCHINPUTVALUE => '0',
SDO => open,
SDI => '0',
SCLK => '0'
);
-- The core of the problem ----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_inst: entity work.neorv32_ProcessorTop_MinimalBoot
generic map (
CLOCK_FREQUENCY => f_clock_c -- clock frequency of clk_i in Hz
)
port map (
-- Global control --
clk_i => std_ulogic(pll_clk),
rstn_i => std_ulogic(pll_rstn),
-- GPIO --
gpio_o => con_gpio_o,
-- primary UART --
uart_txd_o => iCESugarv15_TX, -- UART0 send data
uart_rxd_i => iCESugarv15_RX, -- UART0 receive data
uart_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
uart_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional
-- PWM (to on-board RGB LED) --
pwm_o => con_pwm
);
-- IO Connection --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
RGB_inst: SB_RGBA_DRV
generic map (
CURRENT_MODE => "0b1",
RGB0_CURRENT => "0b000011",
RGB1_CURRENT => "0b000011",
RGB2_CURRENT => "0b000011"
)
port map (
CURREN => '1', -- I
RGBLEDEN => '1', -- I
RGB2PWM => con_pwm(2), -- I - blue - pwm channel 2
RGB1PWM => con_pwm(1) or con_gpio_o(0), -- I - red - pwm channel 1 || BOOT blink
RGB0PWM => con_pwm(0), -- I - green - pwm channel 0
RGB2 => iCESugarv15_LED_B, -- O - blue
RGB1 => iCESugarv15_LED_R, -- O - red
RGB0 => iCESugarv15_LED_G -- O - green
);
end architecture;