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db
incremental_db
output_files
greybox_tmp
*.qws

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# NEORV32 Test Setup using the NEORV32 with AvalonMM Master Interface wrapper
This setup provides a very simple "demo setup" that uses the NEORV32 with a AvalonMM
Interface wrapper. This makes if possible to connect you own modules using a simple
version of the AvalonMM Master interface.
Note that the AvalonMM Master is a very simple version providing only basic features:
* Single read and write access
* Flow control (variable wait-states)
* 8/16/32 bit data access
* Aligned and unaligned access supported
The AvalonMM Master does **not** support:
* Burst access
* Pipeline transfer
* Pending reads
The design is based on the de0-nano-test-setup, but added a AvalonMM Master wrapper.
The wrapper file can be found here [`AvalonMM wrapper`](../../../rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd).
As a test an "external" DMEM is conneced to the NEORV32 over the AvalonMM Master Interface.
It uses the simplified and simple example top entity that provides a minimalistic interface (clock, reset, UART and 8 LEDs).
* FPGA Board: :books: [Terasic DE0-Nano FPGA Board](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593)
* FPGA: Intel Cyclone-IV `EP4CE22F17C6N`
* Toolchain: Intel Quartus Prime (tested with Quartus Prime 18.1.1 - Lite Edition)
### NEORV32 Configuration
For NEORV32 configuration the default values of the neorv32_top in version 1.6.0 are used
with a few exceptions:
* Memory: 16kB instruction memory (internal IMEM), 8kB data memory (external DMEM), No bootloader
* Tested with version [`1.6.0`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md)
* Clock: 50MHz from on-board oscillator
* Reset: via on-board button "KEY0"
* GPIO output port `gpio_o` (8-bit) connected to the 8 green user LEDs ("LED7" - "LED0")
* UART0 signals `uart0_txd_o` and `uart0_rxd_i` are connected to the 40-pin **GPIO_0** header
* `uart0_txd_o:` output, connected to FPGA pin `C3` - header pin `GPIO_01` (pin number "4")
* `uart0_rxd_i:` input, connected to FPGA pin `A3` - header pin `GPIO_03` (pin number "6")
### FPGA Utilization
```
Total logic elements 3,439 / 22,320 ( 15 % )
Total registers 1674
Total pins 12 / 154 ( 8 % )
Total virtual pins 0
Total memory bits 197,632 / 608,256 ( 32 % )
Embedded Multiplier 9-bit elements 0 / 132 ( 0 % )
Total PLLs 0 / 4 ( 0 % )
```
## How To Run
Open the Quartus project file, compile and upload to FPGA.

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2019 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
# Date created = 20:23:30 September 13, 2021
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "18.1"
DATE = "20:23:30 September 13, 2021"
# Revisions
PROJECT_REVISION = "de0-nano-test-setup"

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2019 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
# Date created = 20:23:30 September 13, 2021
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# de0-nano-test-setup_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE22F17C6
set_global_assignment -name TOP_LEVEL_ENTITY neorv32_test_setup_avalonmm
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:40:53 APRIL 10, 2021"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.1 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_application_image.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_bootloader_image.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_boot_rom.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_busswitch.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_bus_keeper.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cfs.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_alu.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_bus.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_control.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_cp_bitmanip.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_cp_fpu.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_cp_muldiv.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_cp_shifter.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_decompressor.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_cpu_regfile.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_debug_dm.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_debug_dtm.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_fifo.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_gpio.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_icache.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_mtime.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_neoled.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_package.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_pwm.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_slink.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_spi.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_sysinfo.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_top.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_trng.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_twi.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_uart.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_wdt.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_wishbone.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_xirq.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_dmem.entity.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_imem.entity.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/mem/neorv32_dmem.default.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/mem/neorv32_imem.default.vhd -library neorv32
set_global_assignment -name VHDL_FILE neorv32_test_setup_avalonmm.vhd
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_location_assignment PIN_R8 -to clk_i
set_location_assignment PIN_L3 -to gpio_o[7]
set_location_assignment PIN_B1 -to gpio_o[6]
set_location_assignment PIN_F3 -to gpio_o[5]
set_location_assignment PIN_D1 -to gpio_o[4]
set_location_assignment PIN_A11 -to gpio_o[3]
set_location_assignment PIN_B13 -to gpio_o[2]
set_location_assignment PIN_A13 -to gpio_o[1]
set_location_assignment PIN_A15 -to gpio_o[0]
set_location_assignment PIN_J15 -to rstn_i
set_location_assignment PIN_C3 -to uart0_txd_o
set_location_assignment PIN_A3 -to uart0_rxd_i
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "18.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "dmem_ram.vhd"]

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-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: dmem_ram.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 18.1.1 Build 646 04/11/2019 SJ Lite Edition
-- ************************************************************
--Copyright (C) 2019 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and any partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel FPGA IP License Agreement, or other applicable license
--agreement, including, without limitation, that your use is for
--the sole purpose of programming logic devices manufactured by
--Intel and sold by Intel or its authorized distributors. Please
--refer to the applicable agreement for further details, at
--https://fpgasoftware.intel.com/eula.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY dmem_ram IS
PORT
(
address : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
byteena : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END dmem_ram;
ARCHITECTURE SYN OF dmem_ram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
q <= sub_wire0(31 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
byte_size => 8,
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone IV E",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 2048,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => 11,
width_a => 32,
width_byteena_a => 4
)
PORT MAP (
address_a => address,
byteena_a => byteena,
clock0 => clock,
data_a => data,
wren_a => wren,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
-- Retrieval info: PRIVATE: WidthData NUMERIC "32"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4"
-- Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
-- Retrieval info: USED_PORT: byteena 0 0 4 0 INPUT VCC "byteena[3..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
-- Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena 0 0 4 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL dmem_ram.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dmem_ram.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dmem_ram.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dmem_ram.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL dmem_ram_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf

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-- #################################################################################################
-- # << NEORV32 - Test Setup using the AvalonMM Interface >> #
-- # ********************************************************************************************* #
-- # (c) "AvalonMM", "NIOS-2", "Qsys", "MegaWizard" and "Platform Designer" #
-- # are trademarks of Intel #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.ALL;
library neorv32;
use neorv32.neorv32_package.all;
entity neorv32_test_setup_avalonmm is
generic (
-- adapt these for your setup --
CLOCK_FREQUENCY : natural := 50000000; -- clock frequency of clk_i in Hz
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
MEM_INT_DMEM_SIZE : natural := 8*1024 -- size of processor-internal data memory in bytes
);
port (
-- Global control --
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
-- GPIO --
gpio_o : out std_ulogic_vector(7 downto 0); -- parallel output
-- UART0 --
uart0_txd_o : out std_ulogic; -- UART0 send data
uart0_rxd_i : in std_ulogic -- UART0 receive data
);
end entity;
architecture neorv32_test_setup_avalonmm_rtl of neorv32_test_setup_avalonmm is
component neorv32_top_avalonmm is
generic (
-- General --
CLOCK_FREQUENCY : natural; -- clock frequency of clk_i in Hz
HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit)
INT_BOOTLOADER_EN : boolean := false; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
-- On-Chip Debugger (OCD) --
ON_CHIP_DEBUGGER_EN : boolean := false; -- implement on-chip debugger
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit-manipulation extension?
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M : boolean := false; -- implement mul/div extension?
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT regs!)
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
CPU_EXTENSION_RISCV_Zmmul : boolean := false; -- implement multiply-only M sub-extension?
-- Extension Options --
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
CPU_CNT_WIDTH : natural := 64; -- total width of CPU cycle and instret counters (0..64)
CPU_IPB_ENTRIES : natural := 2; -- entries is instruction prefetch buffer, has to be a power of 2
-- Physical Memory Protection (PMP) --
PMP_NUM_REGIONS : natural := 0; -- number of regions (0..64)
PMP_MIN_GRANULARITY : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
-- Hardware Performance Monitors (HPM) --
HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29)
HPM_CNT_WIDTH : natural := 40; -- total size of HPM counters (0..64)
-- Internal Instruction memory (IMEM) --
MEM_INT_IMEM_EN : boolean := false; -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
-- Internal Data memory (DMEM) --
MEM_INT_DMEM_EN : boolean := false; -- implement processor-internal data memory
MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes
-- Internal Cache memory (iCACHE) --
ICACHE_EN : boolean := false; -- implement instruction cache
ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2
ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2
ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
-- Stream link interface (SLINK) --
SLINK_NUM_TX : natural := 0; -- number of TX links (0..8)
SLINK_NUM_RX : natural := 0; -- number of TX links (0..8)
SLINK_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two
SLINK_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two
-- External Interrupts Controller (XIRQ) --
XIRQ_NUM_CH : natural := 0; -- number of external IRQ channels (0..32)
XIRQ_TRIGGER_TYPE : std_ulogic_vector(31 downto 0) := x"ffffffff"; -- trigger type: 0=level, 1=edge
XIRQ_TRIGGER_POLARITY : std_ulogic_vector(31 downto 0) := x"ffffffff"; -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
-- Processor peripherals --
IO_GPIO_EN : boolean := false; -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_EN : boolean := false; -- implement machine system timer (MTIME)?
IO_UART0_EN : boolean := false; -- implement primary universal asynchronous receiver/transmitter (UART0)?
IO_UART1_EN : boolean := false; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
IO_SPI_EN : boolean := false; -- implement serial peripheral interface (SPI)?
IO_TWI_EN : boolean := false; -- implement two-wire interface (TWI)?
IO_PWM_NUM_CH : natural := 0; -- number of PWM channels to implement (0..60); 0 = disabled
IO_WDT_EN : boolean := false; -- implement watch dog timer (WDT)?
IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)?
IO_CFS_EN : boolean := false; -- implement custom functions subsystem (CFS)?
IO_CFS_CONFIG : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic
IO_CFS_IN_SIZE : positive := 32; -- size of CFS input conduit in bits
IO_CFS_OUT_SIZE : positive := 32; -- size of CFS output conduit in bits
IO_NEOLED_EN : boolean := false; -- implement NeoPixel-compatible smart LED interface (NEOLED)?
IO_NEOLED_TX_FIFO : natural := 1 -- NEOLED TX FIFO depth, 1..32k, has to be a power of two
);
port (
-- Global control --
clk_i : in std_ulogic; -- global clock, rising edge
rstn_i : in std_ulogic; -- global reset, low-active, async
-- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) --
jtag_trst_i : in std_ulogic := 'U'; -- low-active TAP reset (optional)
jtag_tck_i : in std_ulogic := 'U'; -- serial clock
jtag_tdi_i : in std_ulogic := 'U'; -- serial data input
jtag_tdo_o : out std_ulogic; -- serial data output
jtag_tms_i : in std_ulogic := 'U'; -- mode select
-- AvalonMM interface
read_o : out std_logic;
write_o : out std_logic;
waitrequest_i : in std_logic := '0';
byteenable_o : out std_logic_vector(3 downto 0);
address_o : out std_logic_vector(31 downto 0);
writedata_o : out std_logic_vector(31 downto 0);
readdata_i : in std_logic_vector(31 downto 0) := (others => '0');
-- Advanced memory control signals (available if MEM_EXT_EN = true) --
fence_o : out std_ulogic; -- indicates an executed FENCE operation
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation
-- TX stream interfaces (available if SLINK_NUM_TX > 0) --
slink_tx_dat_o : out sdata_8x32_t; -- output data
slink_tx_val_o : out std_ulogic_vector(7 downto 0); -- valid output
slink_tx_rdy_i : in std_ulogic_vector(7 downto 0) := (others => 'L'); -- ready to send
-- RX stream interfaces (available if SLINK_NUM_RX > 0) --
slink_rx_dat_i : in sdata_8x32_t := (others => (others => 'U')); -- input data
slink_rx_val_i : in std_ulogic_vector(7 downto 0) := (others => 'L'); -- valid input
slink_rx_rdy_o : out std_ulogic_vector(7 downto 0); -- ready to receive
-- GPIO (available if IO_GPIO_EN = true) --
gpio_o : out std_ulogic_vector(63 downto 0); -- parallel output
gpio_i : in std_ulogic_vector(63 downto 0) := (others => 'U'); -- parallel input
-- primary UART0 (available if IO_UART0_EN = true) --
uart0_txd_o : out std_ulogic; -- UART0 send data
uart0_rxd_i : in std_ulogic := 'U'; -- UART0 receive data
uart0_rts_o : out std_ulogic; -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
uart0_cts_i : in std_ulogic := 'L'; -- hw flow control: UART0.TX allowed to transmit, low-active, optional
-- secondary UART1 (available if IO_UART1_EN = true) --
uart1_txd_o : out std_ulogic; -- UART1 send data
uart1_rxd_i : in std_ulogic := 'U'; -- UART1 receive data
uart1_rts_o : out std_ulogic; -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional
uart1_cts_i : in std_ulogic := 'L'; -- hw flow control: UART1.TX allowed to transmit, low-active, optional
-- SPI (available if IO_SPI_EN = true) --
spi_sck_o : out std_ulogic; -- SPI serial clock
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
spi_sdi_i : in std_ulogic := 'U'; -- controller data in, peripheral data out
spi_csn_o : out std_ulogic_vector(07 downto 0); -- chip-select
-- TWI (available if IO_TWI_EN = true) --
twi_sda_io : inout std_logic := 'U'; -- twi serial data line
twi_scl_io : inout std_logic := 'U'; -- twi serial clock line
-- PWM (available if IO_PWM_NUM_CH > 0) --
pwm_o : out std_ulogic_vector(IO_PWM_NUM_CH-1 downto 0); -- pwm channels
-- Custom Functions Subsystem IO (available if IO_CFS_EN = true) --
cfs_in_i : in std_ulogic_vector(IO_CFS_IN_SIZE-1 downto 0) := (others => 'U'); -- custom CFS inputs conduit
cfs_out_o : out std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom CFS outputs conduit
-- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
neoled_o : out std_ulogic; -- async serial data line
-- System time --
mtime_i : in std_ulogic_vector(63 downto 0) := (others => 'U'); -- current system time from ext. MTIME (if IO_MTIME_EN = false)
mtime_o : out std_ulogic_vector(63 downto 0); -- current system time from int. MTIME (if IO_MTIME_EN = true)
-- External platform interrupts (available if XIRQ_NUM_CH > 0) --
xirq_i : in std_ulogic_vector(XIRQ_NUM_CH-1 downto 0) := (others => 'L'); -- IRQ channels
-- CPU interrupts --
mtime_irq_i : in std_ulogic := 'L'; -- machine timer interrupt, available if IO_MTIME_EN = false
msw_irq_i : in std_ulogic := 'L'; -- machine software interrupt
mext_irq_i : in std_ulogic := 'L' -- machine external interrupt
);
end component neorv32_top_avalonmm;
-- Intel/Altera RAM module created by MegaWizard
COMPONENT dmem_ram IS
PORT
(
address : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
byteena : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT dmem_ram;
signal con_gpio_o : std_ulogic_vector(63 downto 0);
signal read_o : std_logic;
signal write_o : std_logic;
signal waitrequest_i : std_logic;
signal byteenable_o : std_logic_vector(3 downto 0);
signal address_o : std_logic_vector(31 downto 0);
signal writedata_o : std_logic_vector(31 downto 0);
signal readdata_i : std_logic_vector(31 downto 0);
signal read_wait_cnt : std_logic_vector(1 downto 0);
begin
-- The Core Of The Problem ----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_top_inst: neorv32_top_avalonmm
generic map (
-- General --
CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz
INT_BOOTLOADER_EN => false, -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_C => true, -- implement compressed extension?
CPU_EXTENSION_RISCV_M => true, -- implement mul/div extension?
CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system?
-- Internal Instruction memory --
MEM_INT_IMEM_EN => true, -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes
-- Internal Data memory --
MEM_INT_DMEM_EN => false, -- implement processor-internal data memory
MEM_INT_DMEM_SIZE => 0, -- size of processor-internal data memory in bytes
-- Processor peripherals --
IO_GPIO_EN => true, -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_EN => true, -- implement machine system timer (MTIME)?
IO_UART0_EN => true -- implement primary universal asynchronous receiver/transmitter (UART0)?
)
port map (
-- Global control --
clk_i => clk_i, -- global clock, rising edge
rstn_i => rstn_i, -- global reset, low-active, async
-- GPIO (available if IO_GPIO_EN = true) --
gpio_o => con_gpio_o, -- parallel output
-- primary UART0 (available if IO_UART0_EN = true) --
uart0_txd_o => uart0_txd_o, -- UART0 send data
uart0_rxd_i => uart0_rxd_i, -- UART0 receive data
-- AvalonMM Interface
read_o => read_o,
write_o => write_o,
waitrequest_i => waitrequest_i,
byteenable_o => byteenable_o,
address_o => address_o,
writedata_o => writedata_o,
readdata_i => readdata_i
);
-- Simple example hooking up RAM module to AvalonMM Interface
-- and using this RAM as DMEM
my_dmem_ram : dmem_ram
port map(
address => address_o(12 downto 2),
byteena => byteenable_o,
clock => clk_i,
data => writedata_o,
wren => write_o,
q => readdata_i);
-- Very simple AvalonMM control signals
-- Write has 0 wait-states
-- Read has 2 wait-states
waitrequest_i <= '1' when (read_o = '1' and read_wait_cnt /= "10") else '0';
process(clk_i, rstn_i)
begin
if rstn_i = '0' then
read_wait_cnt <= "00";
elsif rising_edge(clk_i) then
if read_o = '0' then
read_wait_cnt <= "00";
else
read_wait_cnt <= read_wait_cnt + '1';
end if;
end if;
end process;
-- GPIO output --
gpio_o <= con_gpio_o(7 downto 0);
end architecture;

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/.qsys_edit
/db
/neorv32_test_qsys
/*.sopcinfo
/*.rpt
/output_files
/incremental_db
/*.qws

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# NEORV32 Test Setup using the NEORV32 as a Nios II drop-in replacement
This setup provides a very simple "demo setup" that uses the NEORV32 Qsys/Platform Designer component
so that the NEORV32 can be used as a drop-in replacement of the Nios II soft CPU from Intel.
The demo is running on the Terasic DE0-Nano FPGA Board.
The design is based on the de0-nano-test-setup, but the NEORV32 cpu is added as a QSys/Platform Designer
component. As an example the DMEM is "external" and uses an Platform Designer SRAM block.
![NEORV32 in Platform Designer](figures/neorv32_platform_designer.png)
For details about the design and use of the NEORV32 as a Qsys/Platform Designer component please
look at the Qsys component files and documentation here [`NEORV32 Qsys Component`](../neorv32_qsys_component)
It uses the simplified simple example top entity that provides a minimalistic interface (clock, reset, UART and 8 LEDs).
* FPGA Board: :books: [Terasic DE0-Nano FPGA Board](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593)
* FPGA: Intel Cyclone-IV `EP4CE22F17C6N`
* Toolchain: Intel Quartus Prime (tested with Quartus Prime 18.1.1 - Lite Edition)
### NEORV32 Configuration
For NEORV32 configuration the default values of the neorv32_top in version 1.6.0 are used
with a few exceptions:
* Memory: 16kB instruction memory (internal IMEM), 8kB data memory (external DMEM), No bootloader
* Tested with version [`1.6.0`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md)
* Clock: 50MHz from on-board oscillator
* Reset: via on-board button "KEY0"
* GPIO output port `gpio_o` (8-bit) connected to the 8 green user LEDs ("LED7" - "LED0")
* UART0 signals `uart0_txd_o` and `uart0_rxd_i` are connected to the 40-pin **GPIO_0** header
* `uart0_txd_o:` output, connected to FPGA pin `C3` - header pin `GPIO_01` (pin number "4")
* `uart0_rxd_i:` input, connected to FPGA pin `A3` - header pin `GPIO_03` (pin number "6")
### FPGA Utilization
```
Total logic elements 4,064 / 22,320 ( 18 % )
Total registers 1932
Total pins 12 / 154 ( 8 % )
Total virtual pins 0
Total memory bits 230,400 / 608,256 ( 38 % )
Embedded Multiplier 9-bit elements 0 / 132 ( 0 % )
Total PLLs 0 / 4 ( 0 % )
```
## How To Run
Open the Quartus project file, compile and upload to FPGA.

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<library>
<path path="../neorv32_qsys_component/**/*" />
</library>

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2019 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
# Date created = 21:29:54 June 08, 2021
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "18.1"
DATE = "21:29:54 June 08, 2021"
# Revisions
PROJECT_REVISION = "de0-nano-test-setup"

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2019 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
# Date created = 21:29:54 June 08, 2021
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# de0-nano-test-setup_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE22F17C6
set_global_assignment -name TOP_LEVEL_ENTITY neorv32_ProcessorTop_Test
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:40:53 APRIL 10, 2021"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.1 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id neorv32_ProcessorTop_Test
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id neorv32_ProcessorTop_Test
set_global_assignment -name PARTITION_COLOR 16764057 -section_id neorv32_ProcessorTop_Test
set_location_assignment PIN_R8 -to clk_i
set_location_assignment PIN_J15 -to rstn_i
set_location_assignment PIN_C3 -to uart0_txd_o
set_location_assignment PIN_A3 -to uart0_rxd_i
set_location_assignment PIN_L3 -to gpio_o[7]
set_location_assignment PIN_B1 -to gpio_o[6]
set_location_assignment PIN_F3 -to gpio_o[5]
set_location_assignment PIN_D1 -to gpio_o[4]
set_location_assignment PIN_A11 -to gpio_o[3]
set_location_assignment PIN_B13 -to gpio_o[2]
set_location_assignment PIN_A13 -to gpio_o[1]
set_location_assignment PIN_A15 -to gpio_o[0]
set_global_assignment -name QSYS_FILE neorv32_test_qsys.qsys
set_global_assignment -name QIP_FILE ../neorv32_qsys_component/neorv32_qsys.qip
set_global_assignment -name VHDL_FILE ../../../rtl/core/neorv32_application_image.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/core/neorv32_bootloader_image.vhd
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_dmem.entity.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/neorv32_imem.entity.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/mem/neorv32_dmem.default.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/mem/neorv32_imem.default.vhd -library neorv32
set_global_assignment -name VHDL_FILE neorv32_ProcessorTop_Test.vhd
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id neorv32_ProcessorTop_Test

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#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {altera_reserved_tck} -period 100.000 -waveform { 0.000 50.000 } [get_ports {altera_reserved_tck}]
create_clock -name {clk_i} -period 20.0 -waveform { 0.0 10.0 } [get_ports {clk_i}]

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
entity neorv32_ProcessorTop_Test is port (
clk_i : in std_logic;
rstn_i : in std_logic;
gpio_o : out std_logic_vector(7 downto 0);
uart0_txd_o : out std_logic;
uart0_rxd_i : in std_logic);
end neorv32_ProcessorTop_Test;
----------------------------------------------------------------------------------------------------
architecture rtl of neorv32_ProcessorTop_Test is
----------------------------------------------------------------------------------------------------
component neorv32_test_qsys is
port (
clk_clk : in std_logic;
perf_uart0_uart0_txd_o : out std_logic;
perf_uart0_uart0_rxd_i : in std_logic;
perf_gpio_gpio_o : out std_logic_vector(31 downto 0);
perf_gpio_gpio_i : in std_logic_vector(31 downto 0);
reset_reset_n : in std_logic);
end component;
signal perf_gpio_gpio_o : std_logic_vector(31 downto 0);
begin
gpio_o <= perf_gpio_gpio_o(7 downto 0);
my_riscv_core : neorv32_test_qsys
port map (
clk_clk => clk_i,
perf_gpio_gpio_o => perf_gpio_gpio_o,
perf_gpio_gpio_i => (others => '0'),
perf_uart0_uart0_txd_o => uart0_txd_o,
perf_uart0_uart0_rxd_i => uart0_rxd_i,
reset_reset_n => rstn_i);
end rtl;

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db
incremental_db
output_files
*.qpf
*.qsf
*.qws
*.vhd

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# NEORV32 Test Setup for the Terasic DE0-Nano FPGA Board
This setup provides a very simple script-based "demo setup" that allows to check out the NEORV32 processor on the Terasic DE0-Nano board.
It uses the simplified [`neorv32_test_setup_bootloader.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) top entity, which is a wrapper for the actual processor
top entity that provides a minimalistic interface (clock, reset, UART and 8 LEDs).
* FPGA Board: :books: [Terasic DE0-Nano FPGA Board](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593)
* FPGA: Intel Cyclone-IV `EP4CE22F17C6N`
* Toolchain: Intel Quartus Prime (tested with Quartus Prime 20.1.0 - Lite Edition)
### NEORV32 Configuration
:information_source: See the top entity [`rtl/test_setups/neorv32_test_setup_bootloader.vhd` ](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) for
configuration and entity details and `create_project.tcl` for the according FPGA pin mapping.
* CPU: `rv32imcu_Zicsr` + 4 `HPM` (hardware performance monitors, 40-bit wide)
* Memory: 16kB instruction memory (internal IMEM), 8kB data memory (internal DMEM), bootloader ROM
* Peripherals: `GPIO`, `MTIME`, `UART0`, `WDT`
* Tested with version [`1.5.7.6`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md)
* Clock: 50MHz from on-board oscillator
* Reset: via on-board button "KEY0"
* GPIO output port `gpio_o` (8-bit) connected to the 8 green user LEDs ("LED7" - "LED0")
* UART0 signals `uart0_txd_o` and `uart0_rxd_i` are connected to the 40-pin **GPIO_0** header
* `uart0_txd_o:` output, connected to FPGA pin `C3` - header pin `GPIO_01` (pin number "4")
* `uart0_rxd_i:` input, connected to FPGA pin `A3` - header pin `GPIO_03` (pin number "6")
:warning: The default [`neorv32_test_setup_bootloader.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) top entity
is configured for a 100MHz input clock. Since the on-board oscillator of the DE0-nano board generates a 50MHz clock, the test setup has to be modified.
This is automatically done by the `create_project.tcl` TCL script, which makes a local copy of the original test setup VHDL file
(in *this* folder) and uses `sed` to configure the `CLOCK_FREQUENCY` generic (in the local copy) for 50MHz. The local copy is then used as actual
top entity.
### FPGA Utilization
```
Total logic elements 4,009 / 22,320 ( 18 % )
Total registers 1860
Total pins 12 / 154 ( 8 % )
Total virtual pins 0
Total memory bits 230,400 / 608,256 ( 38 % )
Embedded Multiplier 9-bit elements 0 / 132 ( 0 % )
Total PLLs 0 / 4 ( 0 % )
```
## How To Run
The `create_project.tcl` TCL script in this directory can be used to create a complete Quartus project.
If not already available, this script will create a `work` folder in this directory.
1. start Quartus (in GUI mode)
2. in the menu line click "View/Utility Windows/Tcl console" to open the Tcl console
3. use the console to naviagte to **this** folder: `cd .../neorv32/boards/de0-nano-test-setup`
4. execute `source create_project.tcl` - this will create and open the actual Quartus project in this folder
5. if a "select family" prompt appears select the "Cyclone IV E" family and click OK
6. double click on "Compile Design" in the "Tasks" window. This will synthesize, map and place & route your design and will also generate the actual FPGA bitstream
7. when the process is done open the programmer (for example via "Tools/Programmer") and click "Start" in the programmer window to upload the bitstream to your FPGA
8. use a serial terminal (like :earth_asia: [Tera Term](https://ttssh2.osdn.jp/index.html.en)) to connect to the USB-UART interface using the following configuration:
19200 Baud, 8 data bits, 1 stop bit, no parity bits, no transmission / flow control protocol (raw bytes only), newline on `\r\n` (carriage return & newline)
9. now you can communicate with the bootloader console and upload a new program. Check out the [example programs](https://github.com/stnolting/neorv32/tree/master/sw/example)
and see section "Let's Get It Started" of the :page_facing_up: [NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) for further resources.

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# make a local copy of original "./../../rtl/test_setups/neorv32_test_setup_bootloader.vhd " file
# and modify the default clock frequency: set to 50MHz
set shell_script "cp -f ./../../../rtl/test_setups/neorv32_test_setup_bootloader.vhd . && sed -i 's/100000000/50000000/g' neorv32_test_setup_bootloader.vhd "
exec sh -c $shell_script
# Copyright (C) 2020 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
# Quartus Prime: Generate Tcl File for Project
# File: de0_nano_test.tcl
# Generated on: Sat Apr 10 16:57:48 2021
# Load Quartus Prime Tcl Project package
package require ::quartus::project
set need_to_close_project 0
set make_assignments 1
# Check that the right project is open
if {[is_project_open]} {
if {[string compare $quartus(project) "de0-nano-test-setup"]} {
puts "Project de0-nano-test-setup is not open"
set make_assignments 0
}
} else {
# Only open if not already open
if {[project_exists de0-nano-test-setup]} {
project_open -revision de0-nano-test-setup de0-nano-test-setup
} else {
project_new -revision de0-nano-test-setup de0-nano-test-setup
}
set need_to_close_project 1
}
# Make assignments
if {$make_assignments} {
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE22F17C6
set_global_assignment -name TOP_LEVEL_ENTITY neorv32_test_setup_bootloader
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:40:53 APRIL 10, 2021"
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
# core VHDL files
set core_src_dir [glob ./../../../rtl/core/*.vhd]
foreach core_src_file $core_src_dir {
set_global_assignment -name VHDL_FILE $core_src_file -library neorv32
}
set_global_assignment -name VHDL_FILE ./../../../rtl/core/mem/neorv32_dmem.default.vhd -library neorv32
set_global_assignment -name VHDL_FILE ./../../../rtl/core/mem/neorv32_imem.default.vhd -library neorv32
# top entity: use local modified copy of the original test setup
set_global_assignment -name VHDL_FILE "neorv32_test_setup_bootloader.vhd"
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_location_assignment PIN_R8 -to clk_i
set_location_assignment PIN_L3 -to gpio_o[7]
set_location_assignment PIN_B1 -to gpio_o[6]
set_location_assignment PIN_F3 -to gpio_o[5]
set_location_assignment PIN_D1 -to gpio_o[4]
set_location_assignment PIN_A11 -to gpio_o[3]
set_location_assignment PIN_B13 -to gpio_o[2]
set_location_assignment PIN_A13 -to gpio_o[1]
set_location_assignment PIN_A15 -to gpio_o[0]
set_location_assignment PIN_J15 -to rstn_i
set_location_assignment PIN_C3 -to uart0_txd_o
set_location_assignment PIN_A3 -to uart0_rxd_i
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
# Commit assignments
export_assignments
}

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# NEORV32 Platform Designer Component
This folder contains a Qsys/Platform Designer wrapper for the NEORV32 together with
an Wishbone to AvalonMM bridge. This makes the NEORV32 a drop-in replacement for the
Altera/Intel Nios II soft CPU.
This is just a quick template showing a possible solution, and not a feature complete
solution. All parameters in the Generic section could be added to the GUI.
Only some peripherals (UART0, UART1 and GPIO) are connected, but other peripheral
could easily be connected.
## Solution overview
The solution is made up of 3 files. One VHDL file for the component implementation
(neorv32_qsys.vhd), one file for the Qsys component (neorv32_qsys_hw.tcl) and one file
listing files to include (neorv32_qsys.qip) to simplify the Quartus setup (.qsf) file.
The figure below shows how the component is implemented.
![NEORV32 Qsys Component Solution](figures/overview.png)
## GUI Settings
The Qsys component is created so that some parameters can be set in the Platform Design
GUI. More settings could be added as needed.
![NEORV32 GUI Settings](figures/gui_settings.png)
## Implementation notes
The Platform Designer has a bug (feature?) that makes boolean parameters from the Platform
Designer GUI being port mapped to the VHDL component generic as 0/1 instead of true/false.
This is a known bug/feature.
A workaround for this is made by making the generic (boolean) parameters in the VHDL
as "integer", and then use a "integer2bool" function to make the parameter boolean
again to fit the NEORV32 top.
## How to use
To use the Qsys component in your Platform Designer design, you will just need to
make a "User_Components.ipx" file in your Qsys folder, and reference this (rtl/system_integration/neorv32_qsys_component) folder.
Example "User_Components.ipx" content:
```
<library>
<path path="../neorv32_qsys_component/**/*" />
</library>
```
You will also need to add 3 lines in your Quartus project file (QSF-file) in order to
get the correct source files.
Example QSF-file info:
```
......
set_global_assignment -name QIP_FILE ../neorv32_qsys_component/neorv32_qsys.qip
set_global_assignment -name VHDL_FILE ../../../rtl/core/neorv32_application_image.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/core/neorv32_bootloader_image.vhd
......
```
Having seperate links for the bootloader and application images makes it easy to include images
from your own project folders.
# NEORV32 Platform Designer Component - Example Design
The branch contains an example design using the Qsys/Platform designer component
and running on the DE0 Nano board.
The example design can be found here [setups/quartus/de0-nano-test-setup-qsys`](../de0-nano-test-setup-qsys)
The example design will run the software examples.

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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_package.vhd"] -library neorv32
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_boot_rom.vhd"] -library neorv32
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_busswitch.vhd"] -library neorv32
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_bus_keeper.vhd"] -library neorv32
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_cfs.vhd"] -library neorv32
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_cpu.vhd"] -library neorv32
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_cpu_alu.vhd"] -library neorv32
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_cpu_bus.vhd"] -library neorv32
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_cpu_control.vhd"] -library neorv32
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_cpu_cp_fpu.vhd"] -library neorv32
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_cpu_cp_muldiv.vhd"] -library neorv32
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_cpu_decompressor.vhd"] -library neorv32
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_cpu_regfile.vhd"] -library neorv32
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_debug_dm.vhd"] -library neorv32
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_debug_dtm.vhd"] -library neorv32
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_gpio.vhd"] -library neorv32
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_icache.vhd"] -library neorv32
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_mtime.vhd"] -library neorv32
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_nco.vhd"] -library neorv32
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_neoled.vhd"] -library neorv32
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_package.vhd"] -library neorv32
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_pwm.vhd"] -library neorv32
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_spi.vhd"] -library neorv32
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_sysinfo.vhd"] -library neorv32
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_top.vhd"] -library neorv32
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_trng.vhd"] -library neorv32
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_twi.vhd"] -library neorv32
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_uart.vhd"] -library neorv32
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_wdt.vhd"] -library neorv32
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_wishbone.vhd"] -library neorv32
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_fifo.vhd"] -library neorv32
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "../../../rtl/core/neorv32_cpu_cp_shifter.vhd"] -library neorv32

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-- #################################################################################################
-- # << NEORV32 - Processor Top Qsys component with AvalonMM Compatible Master Interface >> #
-- # ********************************************************************************************* #
-- # (c) "NIOS-2", "Qsys", "Platform Designer" and "AvalonMM" are trademarks of Intel. #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neorv32;
use neorv32.neorv32_package.all;
entity neorv32_qsys is
generic (
GUI_CLOCK_FREQUENCY : integer := 100000000;
GUI_EMABLE_INTERNAL_IMEM : integer := 1;
GUI_IMEM_SIZE : integer := 16;
GUI_EMABLE_INTERNAL_DMEM : integer := 1;
GUI_DMEM_SIZE : integer := 8;
GUI_ENABLE_BOOTLOADER : integer := 0;
GUI_ENABLE_AVALONMM : integer := 1;
GUI_ENABLE_UART0 : integer := 1;
GUI_ENABLE_UART1 : integer := 0;
GUI_ENABLE_GPIO : integer := 0
);
port (
-- Global control --
clk_i : in std_logic := '0'; -- global clock, rising edge
rstn_i : in std_logic := '0'; -- global reset, low-active, async
-- GPIO --
gpio_o : out std_logic_vector(63 downto 0); -- parallel output
gpio_i : in std_logic_vector(63 downto 0) := (others => '0'); -- parallel output
-- UART0 --
uart0_txd_o : out std_logic; -- UART0 send data
uart0_rxd_i : in std_logic := '0'; -- UART0 receive data
-- UART1 --
uart1_txd_o : out std_logic; -- UART0 send data
uart1_rxd_i : in std_logic := '0'; -- UART0 receive data
-- AvalonMM interface
read : out std_logic;
write : out std_logic;
waitrequest : in std_logic := '0';
byteenable : out std_logic_vector(3 downto 0);
address : out std_logic_vector(31 downto 0);
writedata : out std_logic_vector(31 downto 0);
readdata : in std_logic_vector(31 downto 0) := (others => '0')
);
end entity;
architecture neorv32_qsys_rtl of neorv32_qsys is
signal gpio_i_ulogic : std_ulogic_vector(63 downto 0);
signal gpio_o_ulogic : std_ulogic_vector(63 downto 0);
-- Wishbone bus interface (available if MEM_EXT_EN = true) --
signal wb_tag_o : std_ulogic_vector(02 downto 0); -- request tag
signal wb_adr_o : std_ulogic_vector(31 downto 0); -- address
signal wb_dat_i : std_ulogic_vector(31 downto 0); -- read data
signal wb_dat_o : std_ulogic_vector(31 downto 0); -- write data
signal wb_we_o : std_ulogic; -- read/write
signal wb_sel_o : std_ulogic_vector(03 downto 0); -- byte enable
signal wb_stb_o : std_ulogic; -- strobe
signal wb_cyc_o : std_ulogic; -- valid cycle
signal wb_lock_o : std_ulogic; -- exclusive access request
signal wb_ack_i : std_ulogic; -- transfer acknowledge
signal wb_err_i : std_ulogic; -- transfer error
signal reset : std_logic;
function integer2bool(integer_value : integer := 0) return boolean is
begin
if integer_value = 0 then
return false;
else
return true;
end if;
end function;
begin
-- The Core Of The Problem ----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_top_inst: neorv32_top
generic map (
-- General --
CLOCK_FREQUENCY => GUI_CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz
INT_BOOTLOADER_EN => integer2bool(GUI_ENABLE_BOOTLOADER), -- implement processor-internal bootloader?
HW_THREAD_ID => 0, -- hardware thread id (hartid)
-- On-Chip Debugger (OCD) --
ON_CHIP_DEBUGGER_EN => false, -- implement on-chip debugger
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_A => false, -- implement atomic extension?
CPU_EXTENSION_RISCV_C => true, -- implement compressed extension?
CPU_EXTENSION_RISCV_E => false, -- implement embedded RF extension?
CPU_EXTENSION_RISCV_M => true, -- implement muld/div extension?
CPU_EXTENSION_RISCV_U => true, -- implement user mode extension?
CPU_EXTENSION_RISCV_Zfinx => false, -- implement 32-bit floating-point extension (using INT reg!)
CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system?
CPU_EXTENSION_RISCV_Zifencei => false, -- implement instruction stream sync.?
CPU_EXTENSION_RISCV_Zmmul => false, -- implement multiply-only M sub-extension?
-- Extension Options --
FAST_MUL_EN => false, -- use DSPs for M extension's multiplier
FAST_SHIFT_EN => false, -- use barrel shifter for shift operations
CPU_CNT_WIDTH => 64, -- total width of CPU cycle and instret counters (0..64)
CPU_IPB_ENTRIES => 2, -- entries is instruction prefetch buffer, has to be a power of 2
-- Physical Memory Protection (PMP) --
PMP_NUM_REGIONS => 0, -- number of regions (0..64)
PMP_MIN_GRANULARITY => 64*1024, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
-- Hardware Performance Monitors (HPM) --
HPM_NUM_CNTS => 4, -- number of implemented HPM counters (0..29)
HPM_CNT_WIDTH => 40, -- total size of HPM counters (0..64)
-- Internal Instruction memory --
MEM_INT_IMEM_EN => integer2bool(GUI_EMABLE_INTERNAL_IMEM), -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE => GUI_IMEM_SIZE*1024, -- size of processor-internal instruction memory in bytes
-- Internal Data memory --
MEM_INT_DMEM_EN => integer2bool(GUI_EMABLE_INTERNAL_DMEM), -- implement processor-internal data memory
MEM_INT_DMEM_SIZE => GUI_DMEM_SIZE*1024, -- size of processor-internal data memory in bytes
-- Internal Cache memory --
ICACHE_EN => false, -- implement instruction cache
ICACHE_NUM_BLOCKS => 4, -- i-cache: number of blocks (min 1), has to be a power of 2
ICACHE_BLOCK_SIZE => 64, -- i-cache: block size in bytes (min 4), has to be a power of 2
ICACHE_ASSOCIATIVITY => 1, -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
-- External memory interface --
MEM_EXT_EN => integer2bool(GUI_ENABLE_AVALONMM), -- implement external memory bus interface?
MEM_EXT_TIMEOUT => 0, -- cycles after a pending bus access auto-terminates (0 = disabled)
MEM_EXT_PIPE_MODE => false, -- protocol: false=classic/standard wishbone mode, true=pipelined wishbone mode
MEM_EXT_BIG_ENDIAN => false, -- byte order: true=big-endian, false=little-endian
MEM_EXT_ASYNC_RX => false, -- use register buffer for RX data when false
-- Stream link interface (SLINK) --
SLINK_NUM_TX => 0, -- number of TX links (0..8)
SLINK_NUM_RX => 0, -- number of TX links (0..8)
SLINK_TX_FIFO => 1, -- TX fifo depth, has to be a power of two
SLINK_RX_FIFO => 1, -- RX fifo depth, has to be a power of two
-- External Interrupts Controller (XIRQ) --
XIRQ_NUM_CH => 0, -- number of external IRQ channels (0..32)
XIRQ_TRIGGER_TYPE => (x"FFFFFFFF"), -- trigger type: 0=level, 1=edge
XIRQ_TRIGGER_POLARITY => (x"FFFFFFFF"), -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
-- Processor peripherals --
IO_GPIO_EN => integer2bool(GUI_ENABLE_GPIO), -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_EN => true, -- implement machine system timer (MTIME)?
IO_UART0_EN => integer2bool(GUI_ENABLE_UART0), -- implement primary universal asynchronous receiver/transmitter (UART0)?
IO_UART1_EN => integer2bool(GUI_ENABLE_UART1), -- implement secondary universal asynchronous receiver/transmitter (UART1)?
IO_SPI_EN => false, -- implement serial peripheral interface (SPI)?
IO_TWI_EN => false, -- implement two-wire interface (TWI)?
IO_PWM_NUM_CH => 0, -- number of PWM channels to implement (0..60); 0 = disabled
IO_WDT_EN => true, -- implement watch dog timer (WDT)?
IO_TRNG_EN => false, -- implement true random number generator (TRNG)?
IO_CFS_EN => false, -- implement custom functions subsystem (CFS)?
IO_CFS_CONFIG => x"00000000", -- custom CFS configuration generic
IO_CFS_IN_SIZE => 32, -- size of CFS input conduit in bits
IO_CFS_OUT_SIZE => 32, -- size of CFS output conduit in bits
IO_NEOLED_EN => false, -- implement NeoPixel-compatible smart LED interface (NEOLED)?
IO_NEOLED_TX_FIFO => 1 -- NEOLED TX FIFO depth, 1..32k, has to be a power of two
)
port map (
-- Global control --
clk_i => clk_i, -- global clock, rising edge
rstn_i => rstn_i, -- global reset, low-active, async
-- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) --
jtag_trst_i => '0', -- low-active TAP reset (optional)
jtag_tck_i => '0', -- serial clock
jtag_tdi_i => '0', -- serial data input
jtag_tdo_o => open, -- serial data output
jtag_tms_i => '0', -- mode select
-- Wishbone bus interface (available if MEM_EXT_EN = true) --
wb_tag_o => wb_tag_o, -- tag
wb_adr_o => wb_adr_o, -- address
wb_dat_i => wb_dat_i, -- read data
wb_dat_o => wb_dat_o, -- write data
wb_we_o => wb_we_o, -- read/write
wb_sel_o => wb_sel_o, -- byte enable
wb_stb_o => wb_stb_o, -- strobe
wb_cyc_o => wb_cyc_o, -- valid cycle
wb_lock_o => wb_lock_o, -- exclusive access request
wb_ack_i => wb_ack_i, -- transfer acknowledge
wb_err_i => wb_err_i, -- transfer error
-- Advanced memory control signals (available if MEM_EXT_EN = true) --
fence_o => open, -- indicates an executed FENCE operation
fencei_o => open, -- indicates an executed FENCEI operation
-- TX stream interfaces (available if SLINK_NUM_TX > 0) --
slink_tx_dat_o => open, -- output data
slink_tx_val_o => open, -- valid output
slink_tx_rdy_i => (others => 'L'), -- ready to send
-- RX stream interfaces (available if SLINK_NUM_RX > 0) --
slink_rx_dat_i => (others => (others => 'U')), -- input data
slink_rx_val_i => (others => 'L'), -- valid input
slink_rx_rdy_o => open, -- ready to receive
-- GPIO (available if IO_GPIO_EN = true) --
gpio_o => gpio_o_ulogic, -- parallel output
gpio_i => gpio_i_ulogic, -- parallel input
-- primary UART0 (available if IO_UART0_EN = true) --
uart0_txd_o => uart0_txd_o, -- UART0 send data
uart0_rxd_i => uart0_rxd_i, -- UART0 receive data
uart0_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
uart0_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional
-- secondary UART1 (available if IO_UART1_EN = true) --
uart1_txd_o => uart1_txd_o, -- UART1 send data
uart1_rxd_i => uart1_rxd_i, -- UART1 receive data
uart1_rts_o => open, -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional
uart1_cts_i => '0', -- hw flow control: UART1.TX allowed to transmit, low-active, optional
-- SPI (available if IO_SPI_EN = true) --
spi_sck_o => open, -- SPI serial clock
spi_sdo_o => open, -- controller data out, peripheral data in
spi_sdi_i => '0', -- controller data in, peripheral data out
spi_csn_o => open, -- SPI CS
-- TWI (available if IO_TWI_EN = true) --
twi_sda_io => open, -- twi serial data line
twi_scl_io => open, -- twi serial clock line
-- PWM (available if IO_PWM_NUM_CH > 0) --
pwm_o => open, -- pwm channels
-- Custom Functions Subsystem IO --
cfs_in_i => (others => '0'), -- custom inputs
cfs_out_o => open, -- custom outputs
-- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
neoled_o => open, -- async serial data line
-- System time --
mtime_i => (others => '0'), -- current system time from ext. MTIME (if IO_MTIME_EN = false)
mtime_o => open, -- current system time from int. MTIME (if IO_MTIME_EN = true)
-- External platform interrupts (available if XIRQ_NUM_CH > 0) --
xirq_i => (others => '0'), -- IRQ channels
-- Interrupts --
mtime_irq_i => '0', -- machine timer interrupt, available if IO_MTIME_EN = false
msw_irq_i => '0', -- machine software interrupt
mext_irq_i => '0' -- machine external interrupt
);
-- Convert between std_logic / std_ulogic
gpio_o <= std_logic_vector(gpio_o_ulogic);
gpio_i_ulogic <= std_ulogic_vector(gpio_i);
reset <= not(rstn_i);
-- Wishbone to AvalonMM brdige
read <= '1' when (wb_stb_o = '1' and wb_we_o = '0') else '0';
write <= '1' when (wb_stb_o = '1' and wb_we_o = '1') else '0';
address <= std_logic_vector(wb_adr_o);
writedata <= std_logic_vector(wb_dat_o);
byteenable <= std_logic_vector(wb_sel_o);
wb_dat_i <= std_ulogic_vector(readdata);
wb_ack_i <= not(waitrequest);
wb_err_i <= '0';
end architecture;

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#
# request TCL package from ACDS 16.1
#
package require -exact qsys 16.1
#
# module neorv32_qsys
#
set_module_property DESCRIPTION "NEORV32 RISC-V CPU"
set_module_property NAME neorv32_qsys
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP "NEORV32"
set_module_property AUTHOR "Stephan Nolting"
set_module_property DISPLAY_NAME "NEORV32 CPU"
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE false
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
set_module_property ELABORATION_CALLBACK elaborate
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL neorv32_qsys
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file neorv32_qsys.vhd VHDL PATH neorv32_qsys.vhd TOP_LEVEL_FILE
#
# parameters
#
#add_parameter src_id INTEGER 1 ""
#set_parameter_property src_id DEFAULT_VALUE 1
#set_parameter_property src_id DISPLAY_NAME src_id
#set_parameter_property src_id WIDTH ""
#set_parameter_property src_id TYPE INTEGER
#set_parameter_property src_id UNITS None
#set_parameter_property src_id ALLOWED_RANGES 1:15
#set_parameter_property src_id DESCRIPTION "Input source ID"
#set_parameter_property src_id HDL_PARAMETER true
add_parameter GUI_CLOCK_FREQUENCY INTEGER 100000000
set_parameter_property GUI_CLOCK_FREQUENCY DISPLAY_NAME "CPU Clock Frequency"
set_parameter_property GUI_CLOCK_FREQUENCY DISPLAY_UNITS "Hz"
set_parameter_property GUI_CLOCK_FREQUENCY DESCRIPTION "CPU clock frequency"
set_parameter_property GUI_CLOCK_FREQUENCY ALLOWED_RANGES 1000000:250000000
set_parameter_property GUI_CLOCK_FREQUENCY GROUP "Core"
set_parameter_property GUI_CLOCK_FREQUENCY HDL_PARAMETER true
add_parameter GUI_EMABLE_INTERNAL_IMEM BOOLEAN true
set_parameter_property GUI_EMABLE_INTERNAL_IMEM DISPLAY_NAME "Enable Internal IMEM"
set_parameter_property GUI_EMABLE_INTERNAL_IMEM DESCRIPTION "Use interal IMEM"
set_parameter_property GUI_EMABLE_INTERNAL_IMEM GROUP "Core"
set_parameter_property GUI_EMABLE_INTERNAL_IMEM HDL_PARAMETER true
add_parameter GUI_IMEM_SIZE INTEGER 16
set_parameter_property GUI_IMEM_SIZE DISPLAY_NAME "Internal IMEM Memory Size"
set_parameter_property GUI_IMEM_SIZE DISPLAY_UNITS "KBytes"
set_parameter_property GUI_IMEM_SIZE DESCRIPTION "Size of IMEM instruction memory"
set_parameter_property GUI_IMEM_SIZE ALLOWED_RANGES {4 8 16 32 64}
set_parameter_property GUI_IMEM_SIZE GROUP "Core"
set_parameter_property GUI_IMEM_SIZE HDL_PARAMETER true
add_parameter GUI_EMABLE_INTERNAL_DMEM BOOLEAN true
set_parameter_property GUI_EMABLE_INTERNAL_DMEM DISPLAY_NAME "Enable Internal DMEM"
set_parameter_property GUI_EMABLE_INTERNAL_DMEM DESCRIPTION "Use interal DMEM"
set_parameter_property GUI_EMABLE_INTERNAL_DMEM GROUP "Core"
set_parameter_property GUI_EMABLE_INTERNAL_DMEM HDL_PARAMETER true
add_parameter GUI_DMEM_SIZE INTEGER 8
set_parameter_property GUI_DMEM_SIZE DISPLAY_NAME "Internal DMEM Memory Size"
set_parameter_property GUI_DMEM_SIZE DISPLAY_UNITS "KBytes"
set_parameter_property GUI_DMEM_SIZE DESCRIPTION "Size of DMEM data memory"
set_parameter_property GUI_DMEM_SIZE ALLOWED_RANGES {2 4 8 16 32 64}
set_parameter_property GUI_DMEM_SIZE GROUP "Core"
set_parameter_property GUI_DMEM_SIZE HDL_PARAMETER true
add_parameter GUI_ENABLE_BOOTLOADER BOOLEAN false
set_parameter_property GUI_ENABLE_BOOTLOADER DISPLAY_NAME "Enable Bootloader"
set_parameter_property GUI_ENABLE_BOOTLOADER DESCRIPTION "Add bootloader and start bootloader"
set_parameter_property GUI_ENABLE_BOOTLOADER GROUP "Bootloader"
set_parameter_property GUI_ENABLE_BOOTLOADER HDL_PARAMETER true
add_parameter GUI_ENABLE_AVALONMM BOOLEAN true
set_parameter_property GUI_ENABLE_AVALONMM DISPLAY_NAME "Enable AvalonMM Interface"
set_parameter_property GUI_ENABLE_AVALONMM DESCRIPTION "Add AvalonMM Interface for external modules"
set_parameter_property GUI_ENABLE_AVALONMM GROUP "Peripheral"
set_parameter_property GUI_ENABLE_AVALONMM HDL_PARAMETER true
add_parameter GUI_ENABLE_UART0 BOOLEAN true
set_parameter_property GUI_ENABLE_UART0 DISPLAY_NAME "Enable UART0"
set_parameter_property GUI_ENABLE_UART0 DESCRIPTION "Add UART0 to core"
set_parameter_property GUI_ENABLE_UART0 GROUP "Peripheral"
set_parameter_property GUI_ENABLE_UART0 HDL_PARAMETER true
add_parameter GUI_ENABLE_UART1 BOOLEAN false
set_parameter_property GUI_ENABLE_UART1 DISPLAY_NAME "Enable UART1"
set_parameter_property GUI_ENABLE_UART1 DESCRIPTION "Add UART1 to core"
set_parameter_property GUI_ENABLE_UART1 GROUP "Peripheral"
set_parameter_property GUI_ENABLE_UART1 HDL_PARAMETER true
add_parameter GUI_ENABLE_GPIO BOOLEAN false
set_parameter_property GUI_ENABLE_GPIO DISPLAY_NAME "Enable GPIO"
set_parameter_property GUI_ENABLE_GPIO DESCRIPTION "Add GPIO to core"
set_parameter_property GUI_ENABLE_GPIO GROUP "Peripheral"
set_parameter_property GUI_ENABLE_GPIO HDL_PARAMETER true
#
# display items
#
#
# connection point clk
#
add_interface clk clock end
set_interface_property clk clockRate 0
set_interface_property clk ENABLED true
set_interface_property clk EXPORT_OF ""
set_interface_property clk PORT_NAME_MAP ""
set_interface_property clk CMSIS_SVD_VARIABLES ""
set_interface_property clk SVD_ADDRESS_GROUP ""
add_interface_port clk clk_i clk Input 1
#
# connection point reset
#
add_interface reset reset end
set_interface_property reset associatedClock clk
set_interface_property reset synchronousEdges DEASSERT
set_interface_property reset ENABLED true
set_interface_property reset EXPORT_OF ""
set_interface_property reset PORT_NAME_MAP ""
set_interface_property reset CMSIS_SVD_VARIABLES ""
set_interface_property reset SVD_ADDRESS_GROUP ""
add_interface_port reset rstn_i reset_n Input 1
#
# connection point perf_gpio
#
add_interface perf_gpio conduit end
set_interface_property perf_gpio associatedClock none
set_interface_property perf_gpio associatedReset none
set_interface_property perf_gpio ENABLED true
set_interface_property perf_gpio EXPORT_OF ""
set_interface_property perf_gpio PORT_NAME_MAP ""
set_interface_property perf_gpio CMSIS_SVD_VARIABLES ""
set_interface_property perf_gpio SVD_ADDRESS_GROUP ""
add_interface_port perf_gpio gpio_o gpio_o Output 64
add_interface_port perf_gpio gpio_i gpio_i Input 64
#
# connection point perf_uart0
#
add_interface perf_uart0 conduit end
set_interface_property perf_uart0 associatedClock none
set_interface_property perf_uart0 associatedReset none
set_interface_property perf_uart0 ENABLED true
set_interface_property perf_uart0 EXPORT_OF ""
set_interface_property perf_uart0 PORT_NAME_MAP ""
set_interface_property perf_uart0 CMSIS_SVD_VARIABLES ""
set_interface_property perf_uart0 SVD_ADDRESS_GROUP ""
add_interface_port perf_uart0 uart0_txd_o uart0_txd_o Output 1
add_interface_port perf_uart0 uart0_rxd_i uart0_rxd_i Input 1
#
# connection point perf_uart1
#
add_interface perf_uart1 conduit end
set_interface_property perf_uart1 associatedClock none
set_interface_property perf_uart1 associatedReset none
set_interface_property perf_uart1 ENABLED true
set_interface_property perf_uart1 EXPORT_OF ""
set_interface_property perf_uart1 PORT_NAME_MAP ""
set_interface_property perf_uart1 CMSIS_SVD_VARIABLES ""
set_interface_property perf_uart1 SVD_ADDRESS_GROUP ""
add_interface_port perf_uart1 uart1_txd_o uart1_txd_o Output 1
add_interface_port perf_uart1 uart1_rxd_i uart1_rxd_i Input 1
#
# connection point master
#
add_interface master avalon start
set_interface_property master addressUnits SYMBOLS
set_interface_property master associatedClock clk
set_interface_property master associatedReset reset
set_interface_property master bitsPerSymbol 8
set_interface_property master burstOnBurstBoundariesOnly false
set_interface_property master burstcountUnits WORDS
set_interface_property master doStreamReads false
set_interface_property master doStreamWrites false
set_interface_property master holdTime 0
set_interface_property master linewrapBursts false
set_interface_property master maximumPendingReadTransactions 0
set_interface_property master maximumPendingWriteTransactions 0
set_interface_property master readLatency 0
set_interface_property master readWaitTime 0
set_interface_property master setupTime 0
set_interface_property master timingUnits Cycles
set_interface_property master writeWaitTime 0
set_interface_property master ENABLED true
set_interface_property master EXPORT_OF ""
set_interface_property master PORT_NAME_MAP ""
set_interface_property master CMSIS_SVD_VARIABLES ""
set_interface_property master SVD_ADDRESS_GROUP ""
add_interface_port master address address Output 32
add_interface_port master read read Output 1
add_interface_port master write write Output 1
add_interface_port master byteenable byteenable Output 4
add_interface_port master writedata writedata Output 32
add_interface_port master readdata readdata Input 32
add_interface_port master waitrequest waitrequest Input 1
# Callback to enable/disable interface signals
proc elaborate {} {
if { [get_parameter_value GUI_ENABLE_GPIO] == "false" } {
set_interface_property perf_gpio ENABLED false
} else {
set_interface_property perf_gpio ENABLED true
}
if { [get_parameter_value GUI_ENABLE_UART0] == "false" } {
set_interface_property perf_uart0 ENABLED false
} else {
set_interface_property perf_uart0 ENABLED true
}
if { [get_parameter_value GUI_ENABLE_UART1] == "false" } {
set_interface_property perf_uart1 ENABLED false
} else {
set_interface_property perf_uart1 ENABLED true
}
if { [get_parameter_value GUI_ENABLE_AVALONMM] == "false" } {
set_interface_property master ENABLED false
} else {
set_interface_property master ENABLED true
}
}

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# NEORV32 Test Setup for the Terasic Cyclone-V GX Starter Kit FPGA Board
This setup provides a very simple script-based "demo setup" that allows to check out the NEORV32 processor on the Terasic Cyclone-V GX Starter Kit board.
It uses the simplified [`neorv32_test_setup_bootloader.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) top entity, which is a wrapper for the actual processor
top entity that provides a minimalistic interface (clock, reset, UART and 8 LEDs).
* FPGA Board: :books: [Terasic Cyclone-V GX Starter Kit FPGA Board](https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=830)
* FPGA: Intel Cyclone-V GX `5CGXFC5C6F27C7N`
* Toolchain: Intel Quartus Prime (tested with Quartus Prime 20.1.0 - Lite Edition)
### NEORV32 Configuration
:information_source: See the top entity [`rtl/test_setups/neorv32_test_setup_bootloader.vhd` ](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) for
configuration and entity details and `create_project.tcl` for the according FPGA pin mapping.
* CPU: `rv32imcu_Zicsr` + 4 `HPM` (hardware performance monitors, 40-bit wide)
* Memory: 16kB instruction memory (internal IMEM), 8kB data memory (internal DMEM), bootloader ROM
* Peripherals: `GPIO`, `MTIME`, `UART0`, `WDT`
* Tested with version [`1.5.9.4`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md)
* Clock: 50MHz from on-board oscillator
* Reset: via on-board button "KEY0"
* GPIO output port `gpio_o` (8-bit) connected to the 8 green user LEDs ("LED7" - "LED0")
* UART0 signals `uart0_txd_o` and `uart0_rxd_i` are connected to the on-board provided USB to UART converter
:warning: The default [`neorv32_test_setup_bootloader.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/test_setups/neorv32_test_setup_bootloader.vhd) top entity
is configured for a 100MHz input clock. Since the on-board clock generator of the Cyclone-V GX Starter Kit board needs I2C to be programmed, the fixed 50MHz clock on bank 5B, pin R20 is used for this test setup, and the test setup has to be modified accordingly.
This is automatically done by the `create_project.tcl` TCL script, which makes a local copy of the original test setup VHDL file
(in *this* folder) and uses `sed` to configure the `CLOCK_FREQUENCY` generic (in the local copy) for 50MHz. The local copy is then used as actual
top entity.
### FPGA Utilization
```
Logic utilization (in ALMs) 1,442 / 29,080 ( 5 % )
Total registers 1771
Total pins 12 / 364 ( 3 % )
Total virtual pins 0
Total block memory bits 231,424 / 4,567,040 ( 5 % )
Total DSP Blocks 0 / 150 ( 0 % )
Total HSSI RX PCSs 0 / 6 ( 0 % )
Total HSSI PMA RX Deserializers 0 / 6 ( 0 % )
Total HSSI TX PCSs 0 / 6 ( 0 % )
Total HSSI PMA TX Serializers 0 / 6 ( 0 % )
Total PLLs 0 / 12 ( 0 % )
Total DLLs 0 / 4 ( 0 % )
```
## How To Run
The `create_project.tcl` TCL script in this directory can be used to create a complete Quartus project.
If not already available, this script will create a `work` folder in this directory.
1. start Quartus (in GUI mode)
2. in the menu line click "View/Utility Windows/Tcl console" to open the Tcl console
3. use the console to navigate to **this** folder: `cd .../setups/quartus/terasic-cyclone-V-gx-starter-kit-test-setup`
4. execute `source create_project.tcl` - this will create and open the actual Quartus project in this folder. Do NOT run the Quartus-supplied tcl setup script, as that will change all assignment names.
5. if a "select family" prompt appears, go to the "Board" tab, select the "Cyclone V GX Starter Kit" board and click OK
6. double click on "Compile Design" in the "Tasks" window. This will synthesize, map and place & route your design and will also generate the actual FPGA bitstream
7. when the process is done open the programmer (for example via "Tools/Programmer") and click "Start" in the programmer window to upload the bitstream to your FPGA
8. use a serial terminal (like :earth_asia: [Tera Term](https://ttssh2.osdn.jp/index.html.en)) to connect to the USB-UART interface using the following configuration:
19200 Baud, 8 data bits, 1 stop bit, no parity bits, no transmission / flow control protocol (raw bytes only), newline on `\r\n` (carriage return & newline)
9. now you can communicate with the bootloader console and upload a new program. Check out the [example programs](https://github.com/stnolting/neorv32/tree/master/sw/example)
and see section "Let's Get It Started" of the :page_facing_up: [NEORV32 data sheet](https://raw.githubusercontent.com/stnolting/neorv32/master/docs/NEORV32.pdf) for further resources.

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# make a local copy of original "./../../rtl/test_setups/neorv32_test_setup_bootloader.vhd " file
# and modify the default clock frequency: set to 50MHz
set shell_script "cp -f ./../../../rtl/test_setups/neorv32_test_setup_bootloader.vhd . && sed -i 's/100000000/50000000/g' neorv32_test_setup_bootloader.vhd "
exec sh -c $shell_script
# Copyright (C) 2020 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
# Quartus Prime: Generate Tcl File for Project
# File: terasic-cyclone-V-gx=starter-kit_test.tcl
# Generated on: Sat Apr 10 16:57:48 2021
# Load Quartus Prime Tcl Project package
package require ::quartus::project
set need_to_close_project 0
set make_assignments 1
# Check that the right project is open
if {[is_project_open]} {
if {[string compare $quartus(project) "terasic-cyclone-V-gx-starter-kit-test-setup"]} {
puts "Project terasic-cyclone-V-gx-starter-kit-test-setup is not open"
set make_assignments 0
}
} else {
# Only open if not already open
if {[project_exists de0-nano-test-setup]} {
project_open -revision terasic-cyclone-V-gx-starter-kit-setup terasic-cyclone-V-gx-starter-kit-test-setup
} else {
project_new -revision terasic-cyclone-V-gx-starter-kit-test-setup terasic-cyclone-V-gx-starter-kit-test-setup
}
set need_to_close_project 1
}
# Make assignments
if {$make_assignments} {
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CGXFC5C6F27C7
set_global_assignment -name TOP_LEVEL_ENTITY neorv32_test_setup_bootloader
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "TUE JUN 4 20:41:15 2013"
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name BOARD "Cyclone V GX Starter Kit"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
# core VHDL files
set core_src_dir [glob ./../../../rtl/core/*.vhd]
foreach core_src_file $core_src_dir {
set_global_assignment -name VHDL_FILE $core_src_file -library neorv32
}
# top entity: use local modified copy of the original test setup
set_global_assignment -name VHDL_FILE "neorv32_test_setup_bootloader.vhd"
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk_i
set_instance_assignment -name IO_STANDARD "1.2 V" -to rstn_i
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_o[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_o[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_o[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_o[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_o[4]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_o[5]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_o[6]
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_o[7]
set_instance_assignment -name IO_STANDARD "2.5 V" -to uart0_rxd_i
set_instance_assignment -name IO_STANDARD "2.5 V" -to uart0_txd_o
set_location_assignment PIN_R20 -to clk_i
set_location_assignment PIN_P11 -to rstn_i
set_location_assignment PIN_L7 -to gpio_o[0]
set_location_assignment PIN_K6 -to gpio_o[1]
set_location_assignment PIN_D8 -to gpio_o[2]
set_location_assignment PIN_E9 -to gpio_o[3]
set_location_assignment PIN_A5 -to gpio_o[4]
set_location_assignment PIN_B6 -to gpio_o[5]
set_location_assignment PIN_H8 -to gpio_o[6]
set_location_assignment PIN_H9 -to gpio_o[7]
set_location_assignment PIN_M9 -to uart0_rxd_i
set_location_assignment PIN_L9 -to uart0_txd_o
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
# Commit assignments
export_assignments
}